CN106776376B - Buffer memory management method, memory control circuit unit and storage device - Google Patents

Abstract

The present invention provides a buffer memory management method, a memory control circuit unit and a storage device. The method includes: dividing a first area and a second area in the buffer memory to temporarily store a plurality of logical address-physical address mapping tables, and performing a restore operation on the first area. The method also includes: receiving a write instruction, wherein the logical address-physical address mapping table to which the logical address indicated by the write instruction belongs has been temporarily stored in the first area. The method also includes: copying the logical address-physical address mapping table to the second area, and updating the logical address-physical address mapping table in the second area. The present invention can improve the operating efficiency and system stability when restoring the logical address-physical address mapping table from the buffer memory to a rewritable non-volatile memory module.

Description

Buffer memory management method, memory control circuit unit and storage device

technical field

The present invention relates to a buffer memory management method, and in particular to a buffer memory management method, a memory control circuit unit and a storage device.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in the various memory modules listed above. in portable multimedia devices.

Generally speaking, in a memory storage device that uses a rewritable non-volatile memory module as a storage medium, a buffer memory is also usually configured to temporarily store program codes and data or to be used in the execution background of the memory storage device ( The temporary storage area for data during background) work. For example, the controller of the memory storage device loads the logical address-physical address mapping table into the buffer memory to facilitate data access. When receiving a write command and performing a write operation, the controller of the memory storage device will update the logical address-physical address mapping table temporarily stored in the buffer memory. And when a large number of updated logical address-physical address mapping tables have been temporarily stored in the buffer memory, the controller of the memory storage device will return the updated logical address-physical address mapping table in the buffer memory to the rewritable type non-volatile memory module. Since the updated logical address-physical address mapping table may not be temporarily stored in continuous cache units in the buffer memory, and the rewritable non-volatile memory module uses the physical programming unit as the minimum write unit, therefore, The updated logical address-physical address mapping table must first be copied to the temporary storage area in the buffer memory so as to be concentrated into a size equivalent to one physical programming unit before being stored back into the rewritable non-volatile memory module. However, a large number of copy operations will cause the system to be overloaded, and the restore time will be too long, which will reduce the overall performance.

In addition, during the period when the updated logical address-physical address mapping table in the buffer memory is stored back to the rewritable non-volatile memory module, if a write command is received again, the above-mentioned memory-backed mapping table needs to be updated again. The logical address-physical address mapping table, at this time, the controller of the memory storage device will first suspend receiving the data of the write command and executing the write operation. As a result, writing may fail due to a long waiting time. Therefore, how to improve the operating efficiency and system stability when restoring the logical address-physical address mapping table from the buffer memory to the rewritable non-volatile memory module is a topic concerned by those skilled in the art.

Contents of the invention

The present invention provides a buffer memory management method, a memory control circuit unit and a storage device, which can improve the operating efficiency and system when restoring the logical address-physical address mapping table from the buffer memory to a rewritable non-volatile memory module stability.

An exemplary embodiment of the present invention provides a cache memory management method for a cache memory of a memory storage device. The memory storage device has a rewritable non-volatile memory module. The buffer memory management method includes dividing a first area and a second area in the buffer memory, wherein the first area and the second area respectively have a plurality of consecutive cache units, and the cache units in the first area and the second area At least some of the cache units have temporarily stored multiple logical address-physical address mapping tables. The buffer memory management method also includes performing a store-back operation on the cache units in the first area to store back the logical address-physical address mapping table stored in the first area into the rewritable non-volatile memory module. The buffer memory management method further includes receiving a first write instruction from the host system, and the first write instruction indicates to write the first data to the first logical address, and the first logical address-physical address to which the first logical address belongs The mapping table has been temporarily stored in the first cache unit among the cache units in the first area. The buffer memory management method also includes writing the first data to the rewritable non-volatile memory module, and copying the first logical address-physical address mapping table in the first area to the cache unit in the second area in the second cache unit. The buffer memory management method further includes updating the first logical address-physical address mapping table temporarily stored in the second cache unit in the second area.

In an exemplary embodiment of the present invention, the step of updating the first logical address-physical address mapping table temporarily stored in the second cache unit in the second area further includes marking the second cache unit as an updated state, and The second area is set as an update area, and the update area is used to temporarily store a plurality of updated logical address-physical address mapping tables.

In an exemplary embodiment of the present invention, the above buffer memory management method further includes when all the cache units in the second area are in the updated state, converting the logical address-physical address mapping table in all the cache units in the second area to Store back to the rewritable non-volatile memory module.

In an exemplary embodiment of the present invention, the above buffer memory management method further includes selecting the first cache unit in the second area as the second cache unit according to the order of the cache units in the second area, and setting the first cache unit A pointer points to the second cache unit. Furthermore, after the first logical address-physical address mapping table is copied to the second cache unit in the second area, the first pointer is set to point to another cache unit among the cache units in the second area, wherein the other A cache unit is a cache unit that is not in an updated state after the second cache unit.

In an exemplary embodiment of the present invention, the above buffer memory management method further includes receiving a second write command from the host system, and the second write command indicates to write the second data to the second logical address, and the second The second logical address-physical address mapping table to which the logical address belongs has been temporarily stored in the third cache unit among the cache units in the second area. Furthermore, the second data is written into the rewritable non-volatile memory module, and the second logical address-physical address mapping table temporarily stored in the third cache unit in the second area is updated.

In an exemplary embodiment of the present invention, the above buffer memory management method further includes receiving a third write command from the host system, wherein the third write command indicates to write third data to a third logical address, and the third The third logical address-physical address mapping table to which the logical address belongs has not been loaded into the mapping table area. Furthermore, the third logical address-physical address mapping table is loaded from the rewritable non-volatile memory module, and the third logical address-physical address mapping table is temporarily stored in the fourth cache unit in the second area. in the cache unit. In addition, the third data is written into the rewritable non-volatile memory module, and the third logical address-physical address mapping table temporarily stored in the fourth cache unit in the second area is updated.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, a buffer memory and a memory management circuit. The host interface is electrically connected to the host system, the memory interface is electrically connected to the rewritable non-volatile memory module, the buffer memory is electrically connected to the host interface and the memory interface, and the memory management circuit is electrically connected to the host interface, the memory interface and the buffer memory. The memory management circuit divides the buffer memory into a first area and a second area, wherein the first area and the second area respectively have a plurality of continuous cache units, and the cache units in the first area and the second area have At least some of the cache units have temporarily stored multiple logical address-physical address mapping tables. Furthermore, the memory management circuit performs a store-back operation on the cache units in the first area to store back the logical address-physical address mapping table stored in the first area into the rewritable non-volatile memory module. Moreover, the memory management circuit further receives a first write command from the host system, the first write command indicates to write the first data to the first logical address, and the first logical address-physical address mapping to which the first logical address belongs The table has been temporarily stored in the first cache unit among the cache units in the first region. And, the memory management circuit further writes the first data to the rewritable non-volatile memory module, and copies the first logical address-physical address mapping table in the first area to the cache unit in the second area. in the second cache unit. In addition, the memory management circuit updates the first logical address-physical address mapping table temporarily stored in the second cache unit in the second area.

In an exemplary embodiment of the present invention, the above-mentioned memory management circuit also marks the second cache unit as an updated state, sets the second area as an update area, and the update area is used to temporarily store a plurality of updated Logical address-physical address mapping table.

In an exemplary embodiment of the present invention, the above-mentioned memory management circuit also restores the logical address-physical address mapping tables in all the cache units in the second area when all the cache units in the second area are in the updated state to the rewritable non-volatile memory module.

In an exemplary embodiment of the present invention, the above-mentioned memory management circuit further selects the first cache unit in the second area as the second cache unit according to the order of the cache units in the second area, and sets the first index Points to the second cache location. Moreover, after copying the first logical address-physical address mapping table in the first area to the second cache unit in the second area, the above-mentioned memory management circuit further sets the first index to point to the cache in the second area Another cache unit among the units, and this other cache unit is a cache unit that is not in an updated state after the second cache unit.

In an exemplary embodiment of the present invention, the above-mentioned memory management circuit further receives a second write command from the host system, the second write command indicates to write the second data to the second logical address, and the second logical address The associated second logical address-physical address mapping table has been temporarily stored in the third cache unit among the cache units in the second area. Furthermore, the above-mentioned memory management circuit is also used to write the second data into the rewritable non-volatile memory module, and update the second logical address-physical address mapping temporarily stored in the third cache unit in the second area surface.

In an exemplary embodiment of the present invention, the above-mentioned memory management circuit further receives a third write command from the host system, the third write command indicates to write the third data to the third logical address, and the third logical address The associated third logical address-physical address mapping table has not been loaded into the mapping table area. Furthermore, the above-mentioned memory management circuit further loads a third logical address-physical address mapping table from the rewritable non-volatile memory module, and the third logical address-physical address mapping table is temporarily stored in the cache of the second area In the fourth cache unit among the units. In addition, the above-mentioned memory management circuit also writes the third data into the rewritable non-volatile memory module, and updates the third logical address-physical address mapping table temporarily stored in the fourth cache unit in the second area.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and the above-mentioned memory control circuit unit. The connection interface unit is electrically connected to the host system, and the memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module, and includes a buffer memory.

Based on the above, the memory control circuit unit, the memory storage device and the buffer memory management method proposed by the exemplary embodiments of the present invention can effectively save the storage of the logical address-physical address mapping table to the rewritable non-volatile memory module time, and continue to receive write data from the host system during the restore period, which can improve the operating efficiency and stability of the overall system.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment;

FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment;

3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment;

FIG. 6 and FIG. 7 are exemplary schematic diagrams showing management of physical erase units according to an exemplary embodiment;

Fig. 8 is a schematic diagram of a buffer memory according to an exemplary embodiment;

9A-9F are schematic diagrams of a buffer memory management method according to an exemplary embodiment;

10A-10D are schematic diagrams of a buffer memory management method according to another exemplary embodiment;

11A and 11B are flowcharts of a cache memory management method according to an exemplary embodiment.

Explanation of reference signs:

10: memory storage device;

11: host system;

12: computer;

13: input/output device;

122: microprocessor;

124: random access memory (RAM);

126: system bus;

128: data transmission interface;

21: mouse;

22: keyboard;

23: Display;

24: printer;

25: Pen drive;

26: memory card;

27: SSD;

31: digital camera;

32: SD card;

33: MMC card;

34: memory stick;

35: CF card;

36: embedded storage device;

402: connect the interface unit;

404: memory control circuit unit;

406: a rewritable non-volatile memory module;

410(0)～410(N): physical erasing unit;

502: memory management circuit;

504: host interface;

506: memory interface;

508: buffer memory;

510: power management circuit;

512: error checking and correction circuit;

602: data area;

604: idle area;

606: system area;

608: replace area;

LBA(0)～LBA(H): logic unit;

LZ(0)～LZ(M): logical area;

810(1-0)～810(1-n), 810(2-0)～810(2-n): cache unit;

MTZ: mapping table zone;

Z1: the first zone;

Z2: second zone;

P1: the first index;

P2: the second index;

MT(0)～MT(2n), MT(k), MT(k)', MT(s), MT(x): logical address-physical address mapping table;

S1101, S1103, S1105, S1107, S1109, S1111, S1113, S1115, S1117, S1119, S1121, S1123, S1125, S1127, S1129: steps in the buffer memory management method.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit unit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment, and FIG. 2 is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment.

Referring to FIG. 1 , the host system 11 generally includes a computer 12 and an input/output (input/output, I/O for short) device 13 . The computer 12 includes a microprocessor 122 , a random access memory (random access memory, RAM for short) 124 , a system bus 126 and a data transmission interface 128 . The input/output device 13 includes a mouse 21 , a keyboard 22 , a monitor 23 and a printer 24 as shown in FIG. 2 . It must be understood that the device shown in FIG. 2 is not limited to the input/output device 13, and the input/output device 13 may also include other devices.

In this exemplary embodiment, the memory storage device 10 is electrically connected to other components of the host system 11 through the data transmission interface 128 . Data can be written into the memory storage device 10 or read from the memory storage device 10 through the operation of the microprocessor 122 , the random access memory 124 and the input/output device 13 . For example, the memory storage device 10 may be a rewritable non-volatile memory storage device such as a flash drive 25 , a memory card 26 or a solid state drive (Solid State Drive, SSD for short) 27 as shown in FIG. 2 .

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

In general, host system 11 is any system that can cooperate substantially with memory storage device 10 to store data. Although in this exemplary embodiment, the host system 11 is described as a computer system, however, in another exemplary embodiment, the host system 11 may be a system such as a digital camera, a video camera, a communication device, an audio player, or a video player. . For example, when the host computer system is a digital camera (video camera) 31 in FIG. CF card 35 or embedded storage device 36 (as shown in FIG. 3 ). The embedded storage device 36 includes an embedded multimedia card (Embedded MMC, eMMC for short) and a universal flash memory (Universal Flash Storage, UFS for short). It is worth mentioning that the embedded multimedia card or the universal flash memory is directly electrically connected to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, referred to as: PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, referred to as: IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express for short) standard, Universal Serial Bus (Universal Serial Bus, USB for short) standard, Ultra High Speed-I (UHS-I for short) ) interface standard, Ultra High Speed-II (UHS-II for short) interface standard, Secure Digital (Secure Digital, SD for short) interface standard, Memory Stick (MS for short) interface standard, Multi Media Card (MMC for short) interface standard, Compact Flash (CF for short) interface standard, Integrated Device Electronics (IDE for short) standard or other suitable standards. In this exemplary embodiment, the connection interface unit and the memory control circuit unit can be packaged in a chip, or arranged outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or software, and write data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11, Operations such as reading and erasing.

The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 has physical erasing units 410(0)˜410(N). For example, the physical erase units 410(0)˜410(N) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. The physical programming unit is the smallest unit of programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming unit generally includes a data bit area and a redundant bit area. The data bit area contains multiple physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data bit area of each physical programming unit includes 8 physical access addresses, and the size of one physical access address is 512 bytes. However, in other exemplary embodiments, the data bit area may also include more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the invention is not limited thereto.

In this exemplary embodiment, the rewritable non-volatile memory module 406 is a multilevel memory cell (MultiLevel Cell, referred to as: MLC) NAND flash memory module (that is, a memory cell that can store 2 data bits flash memory module). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a single-level memory cell (Single Level Cell, referred to as: SLC) NAND flash memory module (that is, one memory cell can store one data bit flash memory module), multi-level memory cell (Trinary Level Cell, referred to as: TLC) NAND flash memory module (that is, a flash memory module that can store 3 data bits in a storage unit), other fast flash memory module or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment.

Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 , a buffer memory 508 , a power management circuit 510 and an error checking and correction circuit 512 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in software. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIG. 6 and FIG. 7 are schematic diagrams showing examples of managing physical erase units according to an example embodiment.

It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 406, words such as "extract", "group", "divide", and "associate" are used to operate physical erasure. A unit is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable nonvolatile memory module is not changed, but the physical erasing unit of the rewritable nonvolatile memory module is logically operated.

Please refer to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) will logically group the physical erasing units 410(0)-410(N) into a data area 602, an idle area 604, a system area 606, and a replacement area. 608.

The physical erase units logically belonging to the data area 602 and the spare area 604 are used to store data from the host system 11 . Specifically, the physical erasing unit of the data area 602 is regarded as a physical erasing unit of stored data, and the physical erasing unit of the spare area 604 is a physical erasing unit used to replace the data area 602 . That is to say, when receiving the write instruction and the data to be written from the host system 11, the memory management circuit 502 will extract the physical erase unit from the spare area 604, and write the data into the extracted physical erase unit. unit to replace the physical erase unit of the data area 602.

The physical erase units logically belonging to the system area 606 are used to record system data. For example, the system data includes the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased units of the rewritable nonvolatile memory module, the number of physically programmed units per physically erased unit, and the like.

Physically erased units that logically belong to the replacement area 608 are used in the bad physically erased unit replacement process to replace damaged physically erased units. Specifically, if there are still normal physical erasing units in the replacement area 608 and the physical erasing units in the data area 602 are damaged, the memory management circuit 502 will extract normal physical erasing units from the replacement area 608 to replace the damaged ones. physical erase unit.

In particular, the number of physical erase units in the data area 602 , the spare area 604 , the system area 606 and the replacement area 608 varies according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 10 , the grouping relationship of the physical erase unit associated with the data area 602 , the spare area 604 , the system area 606 and the replacement area 608 will change dynamically. For example, when a physically erased unit in the spare area 604 is damaged and replaced by a physically erased unit in the replacement area 608 , the original physically erased unit in the replacement area 608 will be associated with the spare area 604 .

Please refer to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) will configure the logical units LBA(0)-LBA(H) to map the physical erasing units of the data area 602, wherein each logical unit has multiple logic The subunits are mapped to the physical programming units of the corresponding physical erasing units. And, when the host system 11 intends to write data to the logic unit or update the data stored in the logic unit, the memory control circuit unit 404 (or the memory management circuit 502) will extract a physical erase unit from the idle area 604 to write input data to rotate the physical erasing units of the data area 602. In this exemplary embodiment, a logical subunit may be a logical page or a logical sector.

In order to identify which physical erasing unit the data of each logical unit is stored in, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) records the mapping between the logical unit and the physical erasing unit. Moreover, when the host system 11 intends to access data in the logical subunit, the memory control circuit unit 404 (or the memory management circuit 502) will confirm the logical unit to which the logical subunit belongs, and the physical erase mapped to the logical unit In addition to the unit to access data. For example, in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical address-physical address mapping table in the rewritable non-volatile memory module 406 to record the mapping of each logical unit The physical erase unit, and when data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502 ) will load the logical address-physical address mapping table into the buffer memory 508 for maintenance.

It is worth mentioning that, due to the limited capacity of the buffer memory 508, it is impossible to store a mapping table that records the mapping relationship of all logic units. Therefore, in this exemplary embodiment, the memory control circuit unit 404 (or memory management circuit 502) will Units LBA(0)-LBA(H) are grouped into a plurality of logical zones LZ(0)-LZ(M), and a logical address-physical address mapping table is configured for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) intends to update the mapping of a certain logical unit, the logical address-physical address mapping table corresponding to the logical area to which the logical unit belongs will be loaded into the buffer memory 508 to be updated.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the driver code segment to store the data stored in the rewritable non-volatile memory module 406 The control instructions are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. Wherein, the storage unit management circuit is used to manage the physical erasing unit of the rewritable non-volatile memory module 406; the memory writing circuit is used to issue a write instruction to the rewritable non-volatile memory module 406 to write data into the rewritable nonvolatile memory module 406; the memory read circuit is used to issue a read instruction to the rewritable nonvolatile memory module 406 to read from the rewritable nonvolatile memory module 406 Data; the memory erasing circuit is used to issue an erase command to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to process the data to be written Data input to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406.

Referring to FIG. 5 again, the host interface 504 is electrically connected to the memory management circuit 502 and used to electrically connect to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 502 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 .

The buffer memory 508 is electrically connected to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 .

The power management circuit 510 is electrically connected to the memory management circuit 502 and used to control the power of the memory storage device 10 .

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 512 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command. , referred to as: ECC Code), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error checking and correction code into the rewritable non-volatile memory module 406 . Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 512 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

FIG. 8 is a schematic diagram of a buffer memory according to an exemplary embodiment.

Please refer to FIG. 8 , in this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) divides the mapping table zone MTZ in the buffer memory 508 for temporarily storing data from the rewritable non-volatile memory module. 406 the loaded logical address-physical address mapping table. In particular, the memory control circuit unit 404 (or the memory management circuit 502) further divides the mapping table zone MTZ into a first zone Z1 and a second zone Z2, and the first zone Z1 and the second zone Z2 respectively have a plurality of continuous cache unit. Each cache unit is used to temporarily store a logical address-physical address mapping table, and each cache unit can be marked as a different state, such as updated (dirty) state, not updated (clean) state, invalid (invalid) state, A saving state or a loading state, etc., are used to represent the state of the data in the cache unit. In this exemplary embodiment, the size of a logical address-physical address mapping table is 512B, therefore, the size of each cache unit is 512B. The size of the first zone Z1 and the second zone Z2 can be a specific value, such as 64MB or 128MB. However, it must be understood that, in other exemplary embodiments, the size of the cache unit may be determined according to the actual logical address-physical address mapping table, and the sizes of the first zone Z1 and the second zone Z2 may also be determined according to actual usage requirements Rather, the present invention is not limited.

As shown in FIG. 8 , the first zone Z1 has cache units 810(1-0)˜810(1-n), and the second zone Z2 has cache units 810(2-0)˜810(2-n). In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) can preload multiple logical address-physical address mapping tables from the rewritable non-volatile memory module 406 into the buffer memory 508 The mapping table zone MTZ, and temporarily store these logical address-physical address mapping tables in the cache units of the first zone Z1 and the second zone Z2 respectively.

9A-9F are schematic diagrams of a buffer memory management method according to an exemplary embodiment.

Please refer to FIG. 9A, cache units 810(1-0)-810(1-n) in the first zone Z1 temporarily store logical address-physical address mapping tables MT(0)-MT(n), respectively, and the second zone Z2 The cache units 810 ( 2 - 0 )˜ 810 ( 2 - n ) temporarily store logical address-physical address mapping tables MT(n+1)˜MT(2n) respectively. For the convenience of description, the present exemplary embodiment begins with the fact that neither the cache units in the first zone Z1 nor the second zone Z2 are updated. When a write instruction is received from the host system 11, the write instruction indicates that the write data is written to a logical address, and the memory control circuit unit 404 (or memory management circuit 502) will convert the logical address-physical address to which the logical address belongs The mapping table is temporarily stored in the first zone Z1 of the mapping table zone MTZ for maintenance. More specifically, the memory control circuit unit 404 (or the memory management circuit 502) will first determine whether the logical address-physical address mapping table to which the logical address to be written belongs has been temporarily stored in the cache of the first zone Z1 or the second zone Z2 in the unit.

In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) sets an update area for temporarily storing the updated logical address-physical address mapping table. In this exemplary embodiment, when the memory storage device 10 is first powered on, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the update zone as the first zone Z1. In another exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) may also initially set the update zone as the second zone Z2.

When receiving a write instruction indicating to write data to a logical address belonging to the logical address-physical address mapping table MT(n+2) from the host system, the memory control circuit unit 404 (or the memory management circuit 502) will determine the logical The address-physical address mapping table MT(n+2) has been loaded into the mapping table zone MTZ in the buffer memory 508, and is temporarily stored in the cache unit 810(2-1) of the second zone Z2. Therefore, the memory control circuit unit 404 (or memory management circuit 502) will write data to the physical programming unit mapped to the logical address in the rewritable non-volatile memory module 406, and update the temporary cache unit 810 ( 2-1) logical address-physical address mapping table MT(n+2). Next, the memory control circuit unit 404 (or the memory management circuit 502) will move the updated logical address-physical address mapping table MT(n+2) from the cache unit 810(2-1) of the second zone Z2 to the current In the first zone Z1 which is set as the update zone.

In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) also sets the first pointer P1 to point to one of the cache units in the first zone Z1, and the pointed cache unit is not updated state. Specifically, the memory control circuit unit 404 (or the memory management circuit 502 ) judges from front to back according to the order of the multiple cache units in the first zone Z1 whether they are not in the updated state. As shown in FIG. 9A , at this time, all cache units in the first zone Z1 are not in the updated state. Therefore, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the first index P1 to point to the first cache unit 810 (1-0) in the first zone Z1. Afterwards, the memory control circuit unit 404 (or the memory management circuit 502 ) stores the updated logical address-physical address mapping table according to the first index P1. For example, the memory control circuit unit 404 (or the memory management circuit 502) will transfer the updated logical address-physical address mapping table MT(n+2) from the cache unit 810(2-1 ) is moved to the cache unit 810(1-0) of the first zone Z1.

Please refer to FIG. 9B, after the updated logical address-physical address mapping table MT(n+2) is moved to the cache unit 810(1-0) of the first zone Z1, the memory control circuit unit 404 (or memory management circuit 502) will mark the cache unit 810(1-0) as updated. In addition, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the first pointer P1 to point to the last cache unit of the cache units 810 ( 1 - 0 ) in the first zone Z1 that is not in the updated state. In this exemplary embodiment, the subsequent cache unit 810(1-1) of the cache unit 810(1-0) is not in the updated state. Therefore, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the first index P1 to point to the cache unit 810(1-1). In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) can further temporarily store the logical address-physical address mapping table MT(0) in the cache unit 810(1-0) of the first zone Z1 ) is moved to the cache unit 810(2-1) in the second zone Z2. In another exemplary embodiment, the logical address-physical address mapping table MT(0) may also be directly overwritten without being moved.

At this time, if another write instruction indicating to write data to a logical address belonging to the logical address-physical address mapping table MT(n) is received from the host system, the memory control circuit unit 404 (or the memory management circuit 502) It will be determined that the logical address-physical address mapping table MT(n) has been loaded into the mapping table zone MTZ in the buffer memory 508, and is temporarily stored in the cache units 810(1-n) in the first zone Z1. As shown in FIG. 9C, the memory control circuit unit 404 (or the memory management circuit 502) will write data to the physical programming unit mapped to the logical address in the rewritable non-volatile memory module 406, and update the temporary cache The logical address-physical address mapping table MT(n) in the unit 810(1-n) marks the cache unit 810(1-n) as an updated state.

At this time, if another write command indicating to write data to a logical address belonging to the logical address-physical address mapping table MT(k) is received from the host system, the memory control circuit unit 404 (or the memory management circuit 502) It is determined that the logical address-physical address mapping table MT(k) has not been loaded into the mapping table zone MTZ in the buffer memory 508 . Therefore, the memory control circuit unit 404 (or the memory management circuit 502) will load the logical address-physical address mapping table MT(k) from the rewritable non-volatile memory module 406 into the mapping table zone MTZ, and use the first The cache unit 810(1-1) in the first zone Z1 pointed to by a pointer P1 temporarily stores the logical address-physical address mapping table MT(k). As shown in FIG. 9D, the logical address-physical address mapping table MT(k) is temporarily stored in the cache unit 810(1-1) in the first zone Z1, and the memory control circuit unit 404 (or the memory management circuit 502) will Data is written into the rewritable non-volatile memory module 406 . In addition, the memory control circuit unit 404 (or the memory management circuit 502 ) updates the logical address-physical address mapping table MT(k), and marks the cache unit 810(1-1) as an updated state. Furthermore, the memory control circuit unit 404 (or the memory management circuit 502) will select the next cache unit 810(1-2) of the cache unit 810(1-1) in the first zone Z1 that is not in the updated state for The next updated logical address-physical address mapping table is temporarily stored, and the first pointer P1 is set to point to the cache unit 810 (1-2).

In this exemplary embodiment, if all cache units 810(1-0)˜810(1-n) in the first zone Z1 are marked as updated, the memory control circuit unit 404 (or the memory management circuit 502) A store-back operation will be started to store back the logical address-physical address mapping tables temporarily stored in all cache units 810(1-0)-810(1-n) in the first zone Z1 to the rewritable non-volatile memory module 406. However, it should be understood that the memory control circuit unit 404 (or the memory management circuit 502 ) will also start the store back operation at other time points. For example, when performing background operations such as data consolidation or garbage collection (Garbage collection), or before the memory storage device is powered off, or does not receive a write command from the host system 11 after a period of time, the memory control The circuit unit 404 (or the memory management circuit 502 ) will also start a store-back operation, and store the updated logical address-physical address mapping table back into the rewritable non-volatile memory module 406 .

In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) further sets the second index P2 to point to one of the cache units in the second zone Z2. Specifically, the memory control circuit unit 404 (or the memory management circuit 502 ) determines the cache unit to be pointed to by the second pointer P2 from the back to the front according to the order of the multiple cache units in the second zone Z2. As shown in FIG. 9E , the second pointer P2 can be set to point to the cache unit 810 ( 2 - n ) starting from the last cache unit 810 ( 2 - n ) in the second zone Z2 .

At this time, if a read instruction indicating to read data belonging to a logical address of the logical address-physical address mapping table MT(s) is received from the host system, the memory control circuit unit 404 (or the memory management circuit 502) will judge the logical The address-physical address mapping table MT(s) has not been loaded into the mapping table zone MTZ in the buffer memory 508 . Therefore, the memory control circuit unit 404 (or the memory management circuit 502) will load the logical address-physical address mapping table MT(s) from the rewritable non-volatile memory module 406 into the mapping table zone MTZ, and use the first The cache unit 810(2-n) pointed to by the two pointers P2 temporarily stores the logical address-physical address mapping table MT(s). As shown in FIG. 9F, after the logical address-physical address mapping table MT(s) is temporarily stored in the cache unit 810(2-n) in the second zone Z2, the memory control circuit unit 404 (or the memory management circuit 502) Then the data stored in the rewritable non-volatile memory module can be read according to the logical address-physical address mapping table MT(s). In addition, the memory control circuit unit 404 (or the memory management circuit 502) will also set the second index P2 to point to the previous cache unit of the cache unit 810(2-n) in the second zone Z2, that is, the cache unit 810(2-( n-1)). In this exemplary embodiment, if the second pointer P2 points to the first cache unit 810 (2-0) in the second zone Z2, the memory control circuit unit 404 (or the memory management circuit 502) will select the second zone Z2 The last cache unit 810(2-n) of is used as the next cache unit to be pointed to by the second index P2.

At this time, if another read command indicating to read data belonging to a logical address of the logical address-physical address mapping table MT(n+1) is received from the host system, the memory control circuit unit 404 (or the memory management circuit 502 ) will determine that the logical address-physical address mapping table MT(n+1) has been loaded into the mapping table zone MTZ in the buffer memory 508, and is temporarily stored in the cache unit 810(2-0) of the second zone Z2. As shown in FIG. 9F, the memory control circuit unit 404 (or the memory management circuit 502) directly stores the logical address-physical address mapping table MT(n+1) in the cache unit 810(2-0) of the second zone Z2 directly. Read the data in the rewritable non-volatile memory module 406 .

10A-10D are schematic diagrams of a buffer memory management method according to another exemplary embodiment. 10A to 10D are related to the buffer memory management method when a write command is received during the restore operation of the first zone Z1.

Please refer to FIG. 10A. In this exemplary embodiment, if all cache units 810(1-0)-810(1-n) in the first zone Z1 set as the update zone are marked as updated, The memory control circuit unit 404 (or the memory management circuit 502 ) initiates a store-back operation to store back the logical address-physical address mapping table temporarily stored in the first zone Z1 into the rewritable non-volatile memory module. However, the memory control circuit unit 404 (or the memory management circuit 502 ) will also start the store back operation at other time points, which have been illustrated in the foregoing content, and will not be repeated here. In addition, when starting the store back operation to store back the logical address-physical address mapping table temporarily stored in the first zone Z1 to the rewritable non-volatile memory module, the memory control circuit unit 404 (or the memory management circuit 502) The update area will be reset to the second area Z2. Therefore, when a write command is received from the host system 11, the memory control circuit unit 404 (or memory management circuit 502) temporarily stores the logical address-physical address mapping table to be updated in the mapping table area according to the received write command The second zone Z2 of the MTZ, ie the update zone, is for maintenance. In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) points the first pointer P1 to one of the cache units in the second zone Z2, and the pointed cache unit is not in an updated state. As shown in FIG. 10A, since all cache units in the second zone Z2 are not in the updated state at this time, the memory control circuit unit 404 (or the memory management circuit 502) will set the first index P1 to point to the second zone The first cache unit 810(2-0) in Z2.

During the memory back operation, if an instruction is received from the host system 11 to write data (hereinafter also referred to as the first data) into the logical address-physical address mapping table MT(k) (hereinafter also referred to as the first logical address- physical address mapping table) logical address write instruction (hereinafter also referred to as the first write instruction), the memory control circuit unit 404 (or memory management circuit 502) will determine the logical address-physical address mapping table MT (k) It has been loaded into the mapping table zone MTZ in the buffer memory 508 and temporarily stored in the cache unit 810 ( 1 - 1 ) of the first zone Z1 (hereinafter also referred to as the first cache unit). At this point, the memory control circuit unit 404 (or the memory management circuit 502) will write data to the physical programming unit mapped to the logical address in the rewritable non-volatile memory module 406, and convert the logical address-physical address The mapping table MT(k) is copied to the second zone Z2 and temporarily stored in the cache unit 810 ( 2 - 0 ) pointed to by the first pointer P1 (hereinafter also referred to as the second cache unit). The memory control circuit unit 404 (or the memory management circuit 502) copies the logical address-physical address mapping table MT(k) into a logical address-physical address mapping table MT(k)', and as shown in FIG. 10B, converts the logical address- The physical address mapping table MT(k)' is temporarily stored in the cache unit 810(2-0) of the second zone Z2. Moreover, the memory control circuit unit 404 (or the memory management circuit 502) will update the logical address-physical address mapping table MT(k)' temporarily stored in the cache unit 810(2-0) in the second zone Z2, and cache Cell 810(2-0) is marked as updated. In addition, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the first pointer P1 to point to the next cache unit of the cache unit 810 ( 2 - 0 ) in the second zone Z2 that is not in the updated state. In this exemplary embodiment, the subsequent cache unit 810(2-1) of the cache unit 810(2-0) is not in the updated state. Therefore, the memory control circuit unit 404 (or the memory management circuit 502 ) sets the first index P1 to point to the cache unit 810 ( 2 - 1 ).

At this point, if an instruction is received from the host system to write data (hereinafter also referred to as the second data) into the logical address-physical address mapping table MT(n+3) (hereinafter also referred to as the second logical address-physical address mapping table) for another write command (hereinafter also referred to as the second write command), the memory control circuit unit 404 (or memory management circuit 502) will determine the logical address-physical address mapping table MT (n+ 3) It has been loaded into the mapping table zone MTZ in the buffer memory 508 and temporarily stored in the cache unit 810(2-2) of the second zone Z2 (hereinafter also referred to as the third cache unit). As shown in Figure 10C, the memory control circuit unit 404 (or the memory management circuit 502) will write data to the physical programming unit mapped to the logical address in the rewritable non-volatile memory module 406, and update the logical address - The physical address mapping table MT(n+3), and marks the cache unit 810(2-2) as updated.

At this point, if an instruction is received from the host system to write data (hereinafter also referred to as the third data) into the logical address-physical address mapping table MT (x) (hereinafter also referred to as the third logical address-physical address mapping table ) of another write command (hereinafter also referred to as the third write command), the memory control circuit unit 404 (or memory management circuit 502) judges that the logical address-physical address mapping table MT(x) has not been loaded into the mapping table zone MTZ in the buffer memory 508. Therefore, the memory control circuit unit 404 (or the memory management circuit 502) will load the logical address-physical address mapping table MT(x) from the rewritable non-volatile memory module 406 into the mapping table zone MTZ, and use the first The cache unit 810(2-1) in the second zone Z2 pointed to by a pointer P1 temporarily stores the logical address-physical address mapping table MT(x). As shown in FIG. 10D, the logical address-physical address mapping table MT(x) is temporarily stored in the cache unit 810(2-1) (hereinafter also referred to as the fourth cache unit) in the second zone Z2, and the memory control circuit The unit 404 (or the memory management circuit 502 ) writes data into the rewritable non-volatile memory module 406 . The memory control circuit unit 404 (or the memory management circuit 502 ) will also update the logical address-physical address mapping table MT(x), and mark the cache unit 810(2-1) as an updated state.

Furthermore, the memory control circuit unit 404 (or the memory management circuit 502 ) selects the last cache unit of the cache unit 810 ( 2 - 1 ) in the second zone Z2 that is not in the updated state to set the first index P1 . In this exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) sequentially determines that the next cache unit 810 ( 2 - 2 ) of the cache unit 810 ( 2 - 1 ) has been marked as updated. Therefore, the memory control circuit unit 404 (or the memory management circuit 502 ) will sequentially search for cache units that are not in the updated state. Next, the memory control circuit unit 404 (or the memory management circuit 502) will determine that the next cache unit 810(2-3) of the cache unit 810(2-2) is not in the updated state, and set the first pointer P1 to point to the cache Unit 810(2-3).

In this exemplary embodiment, after the restore operation on the first zone Z1 is completed, that is, the memory control circuit unit 404 (or the memory management circuit 502 ) has saved all cache units 810(1-0)˜ Write the logical address-physical address mapping table in 810(1-n) into the rewritable non-volatile memory module, and the memory control circuit unit 404 (or memory management circuit 502) will write all The cache units 810(1-0)-810(1-n) are marked as not updated. In this way, when all the cache units 810(2-0)˜810(2-n) in the second zone Z2 are marked as updated, the memory control circuit unit 404 (or the memory management circuit 502) will start back to Store operation, so as to store back the logical address-physical address mapping tables temporarily stored in all cache units 810(2-0)-810(2-n) of the second zone Z2 to the rewritable non-volatile memory module 406 At the same time, the update area is reset to the first area Z1, so as to continuously receive the data of the write command from the host system to perform the write operation. In addition, in another exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502 ) may further divide the buffer memory 508 into another area with multiple consecutive cache units to temporarily store logic The address-physical address mapping table is not limited in the present invention.

11A and 11B are flowcharts of a cache memory management method according to an exemplary embodiment.

Referring to FIG. 11A , in step S1101 , the memory control circuit unit 404 (or the memory management circuit 502 ) divides a mapping table area in the buffer memory 508 .

In step S1103 , the memory control circuit unit 404 (or the memory management circuit 502 ) divides the mapping table area into a first area and a second area respectively having a plurality of consecutive cache units.

In step S1105, the memory control circuit unit 404 (or the memory management circuit 502) loads a plurality of logical address-physical address mapping tables from the rewritable non-volatile memory module into the first area and the second area. As mentioned above, each loaded logical address-physical address mapping table is temporarily stored in one of the cache units in the first area or in one of the cache units in the second area.

In step S1107, the memory control circuit unit 404 (or the memory management circuit 502) sets the update area to the first area.

In step S1109, the memory control circuit unit 404 (or the memory management circuit 502) updates one of the logical address-physical address mapping tables of the plurality of logical address-physical address mapping tables, and maps one of the logical address-physical address The table is temporarily stored in one of the cache units in the first area, and the one of the cache units in the first area is marked as updated. Specifically, the memory control circuit unit 404 (or the memory management circuit 502) will update the logical address-physical address mapping table according to the write command received from the host system 11, and the relevant operation methods have been described in the aforementioned exemplary embodiments , which will not be repeated here.

In step S1111, if all cache units in the first area are marked as updated, the memory control circuit unit 404 (or memory management circuit 502) temporarily stores the logical address-physical address in all cache units in the first area The address mapping table is stored back into the rewritable non-volatile memory module. However, the memory control circuit unit 404 (or the memory management circuit 502 ) will also start the store back operation at other time points, which have been illustrated in the foregoing content, and will not be repeated here.

If a write command is received from the host system 11 during the process of restoring the logical address-physical address mapping tables temporarily stored in all the cache units in the first area to the rewritable non-volatile memory module, it will additionally execute the 11B process.

Please refer to FIG. 11B, in step S1113, the memory control circuit unit 404 (or the memory management circuit 502) receives from the host system a write command indicating to write data to a logical address belonging to a logical address-physical address mapping table .

In step S1115, the memory control circuit unit 404 (or the memory management circuit 502) changes the update area to the second area.

In step S1117, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the logical address-physical address mapping table to which the logical address belongs has been temporarily stored in the first area or the second area.

In step S1119, if the logical address-physical address mapping table to which the logical address belongs has been temporarily stored in the cache unit of the first area (hereinafter also referred to as the first cache unit), the memory control circuit unit 404 (or memory management circuit 502) Write data to the rewritable non-volatile memory module, and copy the logical address-physical address mapping table in the first cache unit in the first area to the cache unit in the second area (also refer to below for the second cache unit).

In step S1121, the memory control circuit unit 404 (or the memory management circuit 502) updates the logical address-physical address mapping table temporarily stored in the second cache unit in the second area, and marks the second cache unit as an updated state .

In step S1123, if the logical address-physical address mapping table to which the logical address belongs has been temporarily stored in the cache unit of the second area (hereinafter also referred to as the third cache unit), the memory control circuit unit 404 (or memory management circuit 502) Write data into the rewritable non-volatile memory module, update the logical address-physical address mapping table temporarily stored in the third cache unit in the second area, and mark the third cache unit as an updated state .

In step S1125, if the logical address-physical address mapping table to which the logical address belongs has not been temporarily stored in the first area or the second area, the memory control circuit unit 404 (or the memory management circuit 502 ) starts from the rewritable non-volatile The memory module loads the logical address-physical address mapping table to which the logical address belongs and temporarily stores it in the cache unit in the second area (hereinafter also referred to as the fourth cache unit).

In step S1127, the memory control circuit unit 404 (or the memory management circuit 502) writes data into the rewritable non-volatile memory module, and updates the logical address-physical address temporarily stored in the fourth cache unit in the second area. address mapping table, and mark the fourth cache unit as updated.

In step S1129, if all cache units in the second area are marked as updated, the memory control circuit unit 404 (or memory management circuit 502) temporarily stores the logical address-physical address in all cache units in the second area The address mapping table is stored back into the rewritable non-volatile memory module. However, the memory control circuit unit 404 (or the memory management circuit 502 ) will also start the store back operation at other time points, which have been illustrated in the foregoing content, and will not be repeated here.

To sum up, the buffer memory management method, memory control circuit unit and memory storage device provided by the present invention are to divide a specific area with continuous buffer units in the buffer memory, and set the update area as a specific area, so as to The logical address-physical address mapping table to be updated is temporarily stored in the update area. In this way, when the updated logical address-physical address mapping table in the buffer memory is to be stored back to the rewritable non-volatile memory module, the data in the update area can be directly stored according to the size of the physical programming unit. The updated logical address-physical address mapping table is written into the physical programming unit without additional copying and collecting operations. And by setting the specific area to a specific size, the problem of overloading the system due to the large amount of data to be processed can be avoided during the restore operation, thereby effectively improving the processing speed of the restore operation. In addition, by changing the way of updating the area, during the period when the updated logical address-physical address mapping table in the buffer memory is stored back to the rewritable non-volatile memory module, the write command can be continuously received from the host system data and perform write operations to avoid write failures due to long waiting times and improve system stability.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (18)

1. a kind of buffer storage supervisory method, the buffer storage for memory storage apparatus, which is characterized in that described Memory storage apparatus has reproducible nonvolatile memorizer module, and the buffer storage supervisory method includes:

First area and second area are marked off in said buffer memory, wherein the first area and the second area Respectively there are continuous multiple cache units, and in those cache units in the first area and the second area At least part cache unit kept in multiple logical address-physical address mapping tables；

The first area is set as update area, copy-back operation is executed to incite somebody to action to those cache units of the first area Those logical address-physical address mapping tables for being stored in the first area restore to the duplicative non-volatile memories In device module；

The first write instruction is received from host system, wherein first write instruction instruction writes first data into first and patrols Volume address, and the first logical address-physical address mapping table belonging to first logical address has been temporarily stored in described the In the first cache unit among the cache unit in one region；

The update area is changed to the second area, first data are written and are deposited to the duplicative is non-volatile Memory modules, and the first logical address-physical address mapping table in the first area is copied into secondth area In the second cache unit among cache unit in domain；And

The the first logical address-physical address updated in temporary second cache unit in the second region reflects Firing table.

2. buffer storage supervisory method according to claim 1, which is characterized in that update is temporarily stored in the second area In second cache unit in the first logical address-physical address mapping table the step of, further includes:

Second cache unit is denoted as more new state, wherein the update area be configured to temporarily store it is multiple be updated patrol Collect address-physical address mapping table.

3. buffer storage supervisory method according to claim 2, which is characterized in that further include:

When all cache units of the second area are all the more new state, by all cachings of the second area Those logical address-physical address mapping tables in unit restore in the reproducible nonvolatile memorizer module, weight First area described in new settings is the update area.

4. buffer storage supervisory method according to claim 2, which is characterized in that further include:

According to the sequence of the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit；And

In second cache unit copied to the first logical address-physical address mapping table in the second area Later, it sets first index and is directed toward another cache unit among the cache unit of the second area, wherein described Another cache unit is the cache unit that the latter of second cache unit is not the more new state.

5. buffer storage supervisory method according to claim 2, which is characterized in that further include:

The second write instruction is received from the host system, wherein the second data are written to for second write instruction instruction Two logical addresses, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in institute It states in the third cache unit among the cache unit of second area；And

The update area is changed to the second area, second data are written and are deposited to the duplicative is non-volatile Memory modules, and update the second logical address-object in the temporary third cache unit in the second region Manage address mapping table.

6. buffer storage supervisory method according to claim 2, which is characterized in that further include:

Third write instruction is received from the host system, wherein third data are written to for third write instruction instruction Three logical addresses, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into and reflects Firing table area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into described first Region and the second area；

The update area is changed to the second area, institute is loaded into from the reproducible nonvolatile memorizer module State third logical address-physical address mapping table, and third logical address-physical address mapping table be temporarily stored in it is described In the 4th cache unit among the cache unit of second area；And

The third data are written to the reproducible nonvolatile memorizer module, and updates and is temporarily stored in the second area In the 4th cache unit in the third logical address-physical address mapping table.

7. a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, which is characterized in that institute Stating memorizer control circuit unit includes:

Host interface is electrically connected to host system；

Memory interface is electrically connected to the reproducible nonvolatile memorizer module；

Buffer storage is electrically connected to the host interface and the memory interface；And

Memory management circuitry is electrically connected to the host interface, the memory interface and the buffer storage, and To mark off first area and second area in said buffer memory, wherein the first area and the second area Respectively there are continuous multiple cache units, and in those cache units in the first area and the second area At least part cache unit kept in multiple logical address-physical address mapping tables,

Wherein, the memory management circuitry is also to be set as update area for the first area, to the first area Those cache units execute copy-back operation so that those logical address-physical address mapping tables of the first area will be stored in It restores in the reproducible nonvolatile memorizer module,

Wherein, the memory management circuitry is also to receive the first write instruction, first write-in from the host system Instruction instruction writes first data into the first logical address, and the first logical address-belonging to first logical address Physical address mapping table has been temporarily stored in the first cache unit among the cache unit of the first area,

Wherein, the memory management circuitry is also being changed to the second area for the update area, is written described the One data are to the reproducible nonvolatile memorizer module, and by first logical address-in the first area Physical address mapping table copies in the second cache unit among the cache unit in the second area,

Wherein, the memory management circuitry is also to update in temporary second cache unit in the second region The first logical address-physical address mapping table.

8. memorizer control circuit unit according to claim 7, which is characterized in that the memory management circuitry is also used Second cache unit is denoted as more new state, wherein the update area is configured to temporarily store multiple logics being updated Address-physical address mapping table.

9. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also used When with all cache units in the second area being all the more new state, by all caching lists of the second area Those logical address-physical address mapping tables in member restore in the reproducible nonvolatile memorizer module, again The first area is set as the update area.

10. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To the sequence according to the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit,

Wherein, the first logical address-physical address mapping table in the first area is being copied into secondth area After in second cache unit in domain, the memory management circuitry is also to set described in the first index direction Another cache unit among the cache unit of second area, wherein another described cache unit is that second caching is single The latter of member is not the cache unit of the more new state.

11. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive the second write instruction from the host system, the second data, which are written to second, for the second write instruction instruction is patrolled Volume address, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in described the In third cache unit among the cache unit in two regions,

Wherein, the memory management circuitry is also being changed to the second area for the update area, is written described the Two data are to the reproducible nonvolatile memorizer module, and it is slow to update the temporary third in the second region The second logical address-physical address mapping table in memory cell.

12. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive third write instruction from the host system, third data, which are written to third, for the third write instruction instruction is patrolled Address is collected, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into mapping table Area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into the first area With the second area,

Wherein, the memory management circuitry is answered also the update area is changed to the second area from described It writes and is loaded into the third logical address-physical address mapping table in formula non-volatile memory module, and the third logic Address-physical address mapping table is temporarily stored in the 4th cache unit among the cache unit of the second area,

Wherein, the memory management circuitry is also to be written the third data to the type nonvolatile Module, and update the third logical address-in temporary the 4th cache unit in the second region physically Location mapping table.

13. a kind of memory storage apparatus characterized by comprising

Connecting interface unit, is electrically connected to host system；

Reproducible nonvolatile memorizer module；And

Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile Module, and including buffer storage, and to mark off first area and second area in said buffer memory, Described in first area and the second area respectively there is continuous multiple cache units, and the first area and institute It states at least part cache unit in those cache units in second area and has kept in multiple logical address-physical address and reflect Firing table,

Wherein, the memorizer control circuit unit is also to be set as update area for the first area, to described first Those cache units in region execute copy-back operation to reflect those logical address-physical address for being stored in the first area Firing table restores in the reproducible nonvolatile memorizer module,

Wherein, the memorizer control circuit unit also to from the host system receive the first write instruction, described first Write instruction instruction writes first data into the first logical address, and belonging to first logical address first logically Location-physical address mapping table has been temporarily stored in the first cache unit among the cache unit of the first area,

Wherein, institute is written also the update area is changed to the second area in the memorizer control circuit unit The first data are stated to the reproducible nonvolatile memorizer module, and logically by described first in the first area Location-physical address mapping table copies in the second cache unit among the cache unit in the second area,

Wherein, the memorizer control circuit unit is also single to update temporary second caching in the second region The first logical address-physical address mapping table in member.

14. memory storage apparatus according to claim 13, which is characterized in that memorizer control circuit unit also to Second cache unit is denoted as more new state, wherein the update area is configured to temporarily store multiple be updated logically Location-physical address mapping table.

15. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also When to all cache units in the second area being all the more new state, by all cachings of the second area Those logical address-physical address mapping tables in unit restore in the reproducible nonvolatile memorizer module, weight First area described in new settings is the update area.

16. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To the sequence according to the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit,

Wherein, the first logical address-physical address mapping table in the first area is being copied into secondth area After in second cache unit in domain, the memorizer control circuit unit is also directed toward to set first index Another cache unit among the cache unit of the second area, wherein another described cache unit is described second slow The latter of memory cell is not the cache unit of the more new state.

17. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To receive the second write instruction from the host system, the second data, which are written to second, for the second write instruction instruction is patrolled Volume address, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in described the In third cache unit among the cache unit in two regions,

Wherein, institute is written also the update area is changed to the second area in the memorizer control circuit unit The second data are stated to the reproducible nonvolatile memorizer module, and update temporary described the in the second region The second logical address-physical address mapping table in three cache units.

18. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To receive third write instruction from the host system, third data, which are written to third, for the third write instruction instruction is patrolled Address is collected, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into mapping table Area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into the first area With the second area,

Wherein, the memorizer control circuit unit is also to be changed to the second area for the update area, from described Third logical address-the physical address mapping table, and the third are loaded into reproducible nonvolatile memorizer module Logical address-physical address mapping table is temporarily stored in the 4th cache unit among the cache unit of the second area,

Wherein, the memorizer control circuit unit is also deposited the third data are written to the duplicative is non-volatile Memory modules, and update the third logical address-object in temporary the 4th cache unit in the second region Manage address mapping table.