CN106711203B

CN106711203B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN106711203B
Application number: CN201510775826.XA
Authority: CN
Inventors: 张宇瑞; 林正基
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2015-11-12
Filing date: 2015-11-12
Publication date: 2020-03-27
Anticipated expiration: 2035-11-12
Also published as: CN106711203A

Abstract

The present invention provides a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a substrate, a well region having a first conductivity type and located in the substrate, a first doped region having a second conductivity type and having a plurality of branches arranged in the well region, a second doped region having the first conductivity type and having a plurality of branches, and a third doped region having the first conductivity type and arranged in the well region. The second conductivity type is opposite to the first conductivity type. A portion of the first doped region overlaps a portion of the third doped region. The branches of the second doped region are arranged in the third doped region, and a portion of the third doped region is arranged between the first doped region and the second doped region.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a zener diode (zener diode) with a doped region (impurity region) branch.

Background

Generally, when the zener diode is applied to a circuit, it is operated by reverse bias (reverse bias). When the reverse bias voltage applied to the zener diode exceeds a certain value, the current flowing through the diode will be rapidly increased due to electron tunneling effect. This reverse bias is referred to as the Zener breakdown voltage (Zener breakdown voltage). In a zener diode, forward (forward) current is similar to a conventional diode.

The basic architecture of a zener diode includes a p-n junction (p-njunction). The zener breakdown voltage can be tuned by selecting appropriate doping materials and concentrations. Conventional zener diodes include a rectangular doped region. Fig. 1A shows a conventional zener diode 100 with an n-type base. FIG. 1B is a cross-sectional view along line AA' of FIG. 1A. The Zener diode 100 is formed in an N-type Well region (N-Well or NW)102 of a semiconductor substrate 104 and includes a heavily p-doped region (p-Well or NW)⁺)106, at least one heavily n-doped region (n)⁺)108, and at least one n-type base region (NBASE) 110. The zener diode 100 has an anode 112 coupled to the p-type heavily doped region 106 and at least one cathode 114 coupled to the n-type heavily doped region 108.

Fig. 2A shows a conventional zener diode 200 for a p-type base. Fig. 2B is a cross-sectional view along line AA' shown in fig. 2A. The zener diode 200 is formed in a P-type Well region (P-Well or PW)202 of a semiconductor substrate 204 and includes an n-type heavily doped region 206, at least one P-type heavily doped region 208, and at least one P-type base region (PBASE) 210. The zener diode 200 has an anode 212 coupled to the n-type heavily doped region 206 and at least one cathode 214 coupled to the p-type heavily doped region 208.

As shown in fig. 1A, 1B, 2A and 2B, the conventional zener diode has doped regions, such as rectangular p-type heavily doped region 106, n-type heavily doped region 108, n-type heavily doped region 206 and p-type heavily doped region 208. However, in order to achieve higher performance and avoid circuit failure due to the slow switching speed (switching speed) characteristic of the conventional zener diode, the switching speed of the zener diode needs to be increased.

Disclosure of Invention

According to a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a well region of a first conductivity type disposed in the substrate, a first doped region of a second conductivity type disposed in the well region and having a plurality of branches, a second doped region of the first conductivity type disposed in the well region and having a plurality of branches, and a third doped region of the first conductivity type disposed in the well region. The second conductivity type is opposite to the first conductivity type. A portion of the first doped region overlaps a portion of the third doped region. The branch of the second doped region is arranged in the third doped region, and a part of the third doped region is arranged between the first doped region and the second doped region.

According to a second aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, a well region of a first conductivity type disposed in the substrate, a first doped region of a second conductivity type, a second doped region of the first conductivity type, and a third doped region of the first conductivity type disposed in the well region. The first doped region has a first branch extending in a first direction and a plurality of second branches extending in a second direction and connected to the first branch. The second doped region has a third branch substantially extending in the first direction and a plurality of fourth branches substantially extending in the second direction and connected to the third branch. The second conductivity type is opposite to the first conductivity type. A portion of the first doped region overlaps a portion of the third doped region, and a portion of the third doped region is disposed between the first doped region and the second doped region.

According to a third aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes forming a well region of a first conductivity type in a substrate, forming a third doped region of the first conductivity type in the well region, forming a first doped region of a second conductivity type having a plurality of branches in the well region, and forming a second doped region of the first conductivity type having a plurality of branches in the third doped region. The second conductivity type is opposite to the first conductivity type. A portion of the first doped region is formed to overlap a portion of the third doped region. A portion of the third doped region is disposed between the first doped region and the second doped region.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings.

Drawings

The drawings herein attached, which depict exemplary embodiments of the invention, are described as follows:

fig. 1A shows a plan view of a conventional zener diode.

Fig. 1B shows a cross-sectional view along line AA' in fig. 1A.

Fig. 2A shows a plan view of a conventional zener diode.

Fig. 2B shows a cross-sectional view along line AA' in fig. 2A.

Fig. 3A illustrates a plan view of an exemplary semiconductor device in accordance with some embodiments of the invention.

Fig. 3B shows a cross-sectional view along line AA' in fig. 3A.

Fig. 3C illustrates a plan view of an exemplary semiconductor device in accordance with some embodiments of the invention.

Fig. 4A shows a current-voltage curve of a measurement result of a conventional zener diode.

Fig. 4B shows a current-voltage curve of the measurement results of an exemplary semiconductor device according to some embodiments of the present invention.

Fig. 5A shows a current-voltage curve of the measurement result of the conventional zener diode.

Fig. 5B illustrates a current-voltage curve of measurements made by an exemplary semiconductor device in accordance with some embodiments of the present invention.

Figures 6A-6C illustrate plan views of exemplary zener diodes according to some embodiments of the present invention.

Fig. 7 illustrates a cross-sectional view of an exemplary semiconductor device in accordance with some embodiments of the present invention.

Fig. 8 is a flow chart illustrating an exemplary method of fabricating a semiconductor device according to some embodiments of the present invention.

[ notation ] to show

100. 200, 301, 600, 610, 620: zener diode

102. 202, 302, 702: well region

104. 204, 304, 704: semiconductor substrate

106. 208: p-type heavily doped region

108. 206: n-type heavily doped region

110. 210, 310, 606, 616, 626, 710: base region

112. 214: anode

114. 212, and (3): cathode electrode

300. 700: semiconductor device with a plurality of semiconductor chips

306. 602, 612, 622, 706: first doped region

306a, 602 a: first branch

306b, 602 b: second branch

308. 614, 624, 708: second doped region

308a, 602 c: third branch

308b, 604 a: the fourth branch

312. 712: a first electrode

314. 714: second electrode

402. 404, 502, 504: curve line

402a, 404a, 502a, 504 a: zener breakdown region

604 b: the fifth branch

604 c: the sixth branch

612a, 612b, 614a, 614b, 624a, 624 b: branch of

716: dielectric layer

718: field oxide

800: method of producing a composite material

802. 804, 806, 808, 810, 812, 814: step (ii) of

A-A': line segment

Ron: resistance (RC)

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

Fig. 3A illustrates a plan view of a semiconductor device 300 including a zener diode 301 according to some embodiments of the present invention. Fig. 3B shows a cross-sectional view along line AA' in fig. 3A. Referring to fig. 3A and 3B, the zener diode 301 is formed in the well 302 of the first conductivity type, and the well 302 is formed by doping the semiconductor substrate 304 with a dopant of the first conductivity type. The zener diode 301 includes a first doped region 306 doped with a second conductive type dopant, at least one second doped region 308 doped with a first conductive type dopant, and at least one base region 310 (third doped region) doped with a first conductive type dopant. The first conductivity type is opposite to the second conductivity type. For example, the semiconductor substrate 304 may be a p-type silicon or n-type silicon substrate. In some embodiments, second doped region 308 is disposed in base region 310 to a shallower depth than base region 310. The first doped region is disposed in well region 302 and has a shallower depth than base region 310. A portion of first doped region 306 overlaps base region 310. The zener diode 301 has a first electrode 312 coupled to the first doped region 306 and at least one second electrode 314 coupled to the second doped region 308. In an exemplary embodiment of the invention, fig. 3B illustrates two second doped regions 308 embedded in two base regions 310, each base region 310 partially overlapping the first doped region 306.

Fig. 3C shows a portion of zener diode 301, and base region 310 is not shown for clarity. Referring to fig. 3C, the first doped region 306 includes a first branch 306a extending in a first direction, such as an x-axis direction, and a second branch 306b (four second branches 306b are illustrated) extending from the first branch 306a in a second direction different from the first direction, such as a y-axis direction. The second doped region 308 includes a third branch 308a extending in a third direction, e.g., substantially the x-axis direction, and a fourth branch 308b (three fourth branches 308b are illustrated) extending from the third branch 308a in a fourth direction different from the third direction, e.g., substantially the y-axis direction. The second branch 306b of the first doped region 306 and the fourth branch 308b of the second doped region 308 are disposed alternately (interlace with reach other). The first doped region 306 and the second doped region 308 are separated by a base region 310. Although a particular number of branches are depicted in FIG. 3C, the number of branches is not so limited, and may be more or less than the number depicted herein. In the embodiment shown here, the x-axis direction and the y-axis direction are orthogonal (orthogonal).

With reference to fig. 3C, the first doped region 306 has a comb shape or a fork shape, and has a second branch 306b pointing to a third branch 308a of the second doped region 308 along the y-axis direction. The second doped region 308 also has a comb or fork shape with a fourth branch 308b pointing along the y-axis direction towards the first branch 306a of the first doped region 306. The free end (free end) of each second branch 306b of the first doped region 306 is disposed adjacent to the third branch 308a of the second doped region 308. The free end of each fourth branch 308b of the second doped region 308 is disposed adjacent to the first branch 306a of the first doped region 306. As shown in fig. 3C, at least one second branch 306b is disposed between a pair of fourth branches 308b, and at least one fourth branch 308b is disposed between a pair of second branches 306 b. Compared to the conventional zener diode having the same area, the doped region layout shown in fig. 3A and 3C increases junction area (junction area), for example, the interface between the first doped region 306 and the base region 310 increases by about 90%, which increases the current in zener breakdown.

In some embodiments, the firstOne conductivity type is n-type and the second conductivity type is p-type, or vice versa. For example, in an n-type base zener diode, the well region 302 may be n-type; the first doped region 306 may have a doping concentration (doping concentration) of between 10 per cubic centimeter¹⁸To 10²⁰An atomic p-type heavily doped region; the second doped region 308 may be doped to a concentration of between 10 per cubic centimeter¹⁸To 10²⁰An atomic n-type heavily doped region; base region 310 may be doped to a concentration of between 10 per cubic centimeter¹⁶To 10¹⁹An atomic n-type region; and the doping concentration of second doped region 308 is made high compared to the doping concentration of base region 310. The doping concentration of base region 310 depends on the zener breakdown voltage required. Specifically, the doping concentrations of the base region 310 (third doped region) and the first doped region 306 are parameters for adjusting the zener breakdown voltage. The doping concentration of the second doped region 308 is greater than the doping concentration of the well region 302. In a p-type base zener diode, the well region 302 may be p-type; the first doped region 306 may have a doping concentration (doping concentration) of between 10 per cubic centimeter¹⁸To 10²⁰An atomic n-type heavily doped region; the second doped region 308 may be doped to a concentration of between 10 per cubic centimeter¹⁸To 10²⁰An atomic p-type heavily doped region; base region 310 may be doped to a concentration of between 10 per cubic centimeter¹⁶To 10¹⁹A single atom p-type region. In some embodiments, the n-type dopant may be phosphorus or arsenic and the p-type dopant may be boron.

Fig. 4A and 4B show exemplary current-voltage (I-V) characteristics measured on an actual device. Where curves 402 and 404 represent a conventional zener diode and an n-type base zener diode according to some embodiments of the present invention, respectively. In fig. 4A and 4B, the abscissa represents voltage and the ordinate represents current. After zener breakdown in reverse bias, current-

voltage curves

402 and 404 each include

zener breakdown regions

402a and 404a, respectively. The

zener breakdown regions

402a and 404a of the

curves

402 and 404 have a slope that is inversely proportional to the resistance Ron of the diode. As shown in fig. 4A and 4B, the resistance Ron of the conventional zener diode is 18.7 ohms (Ω), while the resistance of the zener diode according to some embodiments of the present invention is 15.6 ohms. The smaller resistance, which represents the zener diode of some embodiments of the present invention, has a faster switching speed than a conventional zener diode.

Fig. 5A and 5B show exemplary current-voltage characteristics measured on an actual device. Where curves 502 and 504 represent a conventional zener diode and a p-type base zener diode according to some embodiments of the present invention, respectively. In fig. 5A and 5B, the abscissa represents voltage and the ordinate represents current. After zener breakdown under reverse bias, the current-

voltage curves

502 and 504 each include a

zener breakdown region

502a and 504 a. While the slope of the zener region 504a is still maintained, the slope of the curve 502a cannot be obtained in the zener region 502a because the zener region 502a can only be approximated by a quadratic equation (quadratic equation), which means that the switching speed is slower. In fig. 5B, the resistance Ron of the zener diode is 23.1 ohms.

Although the first branch 306a, the second branch 306b, the third branch 308a, and the fourth branch 308b are illustrated as being rectangular in fig. 3C, the present invention is not limited thereto. The shape of these branches may be circular, triangular, polygonal, etc. For example, fig. 6A illustrates a portion of the zener diode 600 including a first branch 602a extending in the x-axis direction, a second branch 602b extending from the first branch 602a in the y-axis direction, and a third branch 602c extending from the second branch 602b in the x-axis direction. The first branch 602a, the second branch 602b, and the third branch 602c are all part of the first doped region 602. The zener diode 600 further includes a fourth branch 604a extending in the x-axis direction, a fifth branch 604b extending from the fourth branch 604a in the y-axis direction, and a sixth branch 604c extending from the fifth branch 604b in the x-axis direction. The fourth branch 604a, the fifth branch 604b, and the sixth branch 604c are all part of the second doped region. The first branch 602a, the second branch 602b, the third branch 602c of the first doped region 602, and the fourth branch 604a, the fifth branch 604b, the sixth branch 604c of the second doped region are separated by a base region 606 (third doped region). The first branch 602a, the second branch 602b, the third branch 602c of the first doped region 602 and the fourth branch 604a, the fifth branch 604b, and the sixth branch 604c of the second doped region alternate with each other to increase the current between the first doped region and the second doped region.

Figure 6B illustrates a portion of a zener diode 610 according to some embodiments of the present invention. The zener diode 610 includes a first doped region 612 having

branches

612a and 612b, and a second doped region 614 having

branches

614a and 614 b. Branch 614b has a rounded trailing end portion (end portion). The

branches

612a and 612b of the first doped region 612 and the

branches

614a and 614b of the second doped region 614 are separated by a base region 616 (third doped region).

Figure 6C illustrates a portion of a zener diode 620 in accordance with some embodiments of the present invention. Zener diode 620 includes a first doped region 622 and a second doped region 624 having

branches

624a and 624 b. Branch 624b has an arrow-shaped trailing end portion. The first doped region 622 and the

branches

624a and 624b of the second doped region 624 are separated by a base region 626 (third doped region).

The respective doping concentration ranges of the first doping region, the second doping region and the third doping region in the

zener diodes

600, 610 and 620 are respectively the same as those of the first doping region, the second doping region and the third doping region of the zener diode 301, and the doping concentration of the second doping region is higher than that of the third doping region.

Fig. 7 depicts an exemplary semiconductor device 700 having a zener diode 701 according to some embodiments of the present invention. The zener diode 701 is formed on the first conductive type well region 702 having the first conductive type dopant in the semiconductor substrate 704, and includes a first doped region 706 having the second conductive type dopant, at least one second doped region 708 having the first conductive type dopant, and at least one base region 710 (third doped region) having the first conductive type dopant. The first conductivity type is opposite to the second conductivity type. The second doped region 708 is disposed in the base region 710 and has a shallower depth than the base region 710. The first doped region is disposed in the well 702 and has a shallower depth than the base region 710. A portion of the first doped region 706 overlaps the base region 710. The zener diode 701 has a first electrode 712 coupled to the first doped region 706 through the dielectric layer 716, and at least a second electrode 714 coupled to the second doped region 708 through the dielectric layer 716. The dielectric layer 716 may be an oxide, a nitride, or a combination thereof. The semiconductor device 700 may further include a field oxide (field oxide)718 disposed around the base region 710. In some embodiments, the field oxide 718 may be replaced by a shallow trench isolation (shallow trench isolation) or other suitable dielectric structure.

Fig. 8 illustrates an exemplary method 800 of forming a semiconductor device, such as semiconductor device 300 (fig. 3A-3C) and semiconductor device 700 (fig. 7), including zener diodes in various embodiments of the present invention. Referring to fig. 3A-3C, 7 and 8, in step 802, a well region of a first conductivity type, such as the well region 302 or the well region 702, is formed in the semiconductor substrate. The well region may be formed by ion implantation (ion implantation). In step 804, an isolation region, such as a field oxide 718, is formed in the substrate. At step 806, a base region (third doped region) of the first conductivity type, such as base region 310 or base region 710, is formed in the well region adjacent to the isolation region. In step 808, a first doped region of the second conductivity type, such as the first doped region 306 or the first doped region 706, is formed in the well region and has a plurality of branches. The branches of the first doped region are formed to partially overlap the base region. In step 810, a second doped region of the first conductivity type, such as the second doped region 308 or the second doped region 708, having a plurality of branches, is formed in the base region. The branches of the second doping region are formed to be separated from and alternate with the branches of the first doping region as shown in fig. 3C, 6A, 6B and 6C. At least one branch of the first doped region is formed to be interposed between branches of the two second doped regions, and at least one branch of the second doped region is formed to be interposed between branches of the two first doped regions. The base region, the first doped region and the second doped region may be formed by ion implantation.

Referring to fig. 7 and 8, in some embodiments, the method 800 further includes

steps

812 and 814. In step 812, a dielectric layer, such as dielectric layer 716, is formed over the substrate. In step 814, electrodes, such as electrode 712 and electrode 714, are formed, coupling the first doped regions and the second doped regions through vias (vias) in the dielectric layer.

In some embodiments, one or more of the steps in FIG. 8 may be omitted or modified in order.

The zener diode of the present invention can be used in a voltage regulator (voltage regulator), a voltage shifter (voltage shifter) or a waveform limiter (waveform limiter), a transient voltage suppressor (transient voltage suppressor), or any other circuit using a zener diode.

While the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto. Various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A semiconductor device, comprising:

a substrate;

a well region of a first conductivity type disposed in the substrate;

a first doped region of a second conductivity type opposite to the first conductivity type, the first doped region having a plurality of branches disposed in the well region;

a second doped region of the first conductivity type, the second doped region having a plurality of branches; and

a third doped region of the first conductivity type disposed in the well region, a portion of the first doped region overlapping a portion of the third doped region, the branches of the second doped region disposed in the third doped region, and another portion of the third doped region disposed between the first doped region and the second doped region;

wherein the first doped region is located in an opposite inner portion of the semiconductor device, and the second doped region is located in an opposite outer portion of the semiconductor device; the branches of the first doped region comprise a first branch extending in a first direction and a plurality of second branches extending in a second direction different from the first direction; the branches of the first doped region further include a plurality of third branches extending from the second branches in the first direction.

2. The semiconductor device as defined in claim 1, wherein at least a portion of the branches of the first doped region and at least a portion of the branches of the second doped region alternate with each other.

3. The semiconductor device as claimed in claim 1, wherein the branches of the second doped region include a fourth branch extending in a third direction different from the second direction, the free ends of the second branch being disposed toward the fourth branch.

4. The semiconductor device of claim 3, wherein the branches of the second doped region further comprise fifth branches extending from the fourth branches in a fourth direction, free ends of the fifth branches being disposed toward the first branch.

5. The semiconductor device as claimed in claim 4, wherein at least one of the second branches is disposed between two of the fifth branches, and at least one of the fifth branches is disposed between two of the second branches.

6. The semiconductor device of claim 4, wherein the branches of the second doped region further comprise sixth branches extending from the fifth branches in the third direction.

7. The semiconductor device as defined in claim 3, wherein the free ends of each of the second branches are circular or polygonal.

8. The semiconductor element according to claim 1, further comprising:

a dielectric layer disposed on the substrate;

a first electrode coupled to the first doped region through the dielectric layer; and

a second electrode coupled to the second doped region through the dielectric layer.

9. The semiconductor device as claimed in claim 1, further comprising an insulating layer disposed around the third doped region.

10. The semiconductor device as claimed in claim 1, wherein the second doped region has a doping concentration higher than that of the third doped region.

11. A semiconductor device, comprising:

a substrate;

a well region of a first conductivity type disposed in the substrate;

a first doped region of a second conductivity type, the first doped region having a first branch extending in a first direction and a plurality of second branches extending in a second direction and connected to the first branch, the first doped region further having a plurality of third branches extending from the second branches in the first direction; the second conductivity type is opposite to the first conductivity type;

a second doped region of the first conductivity type, the second doped region having a fourth branch extending in the first direction and a plurality of fifth branches extending in the second direction and connected to the fourth branch; and

a third doped region of the first conductivity type disposed in the well region, a portion of the first doped region overlapping a portion of the third doped region, the second doped region disposed in the third doped region, and another portion of the third doped region disposed between the first doped region and the second doped region;

the first doped region is located in the opposite inner portion of the semiconductor element, and the second doped region is located in the opposite outer portion of the semiconductor element.

12. The semiconductor device as defined in claim 11, wherein at least a portion of the second branches of the first doped region and at least a portion of the fifth branches of the second doped region alternate with each other.

13. The semiconductor device as claimed in claim 11, wherein the free ends of the second branches are disposed toward the fourth branch.

14. The semiconductor device as claimed in claim 11, wherein free ends of the fifth branches are disposed toward the first branch.

15. The semiconductor device as claimed in claim 11, wherein at least one of the second branches is disposed between two of the fifth branches, and at least one of the fifth branches is disposed between two of the second branches.

16. A method for manufacturing a semiconductor device, comprising:

forming a well region of a first conductivity type in a substrate;

forming a third doped region of the first conductivity type in the well region;

forming a first doped region of a second conductivity type in the well region, the first doped region having a plurality of branches, the second conductivity type being opposite to the first conductivity type, a portion of the first doped region being formed to overlap a portion of the third doped region; and

forming the second doped region of the first conductivity type in the third doped region, the second doped region having a plurality of branches, another portion of the third doped region being disposed between the first doped region and the second doped region;

wherein the first doped region is located in an opposite inner portion of the semiconductor device, the second doped region is located in an opposite outer portion of the semiconductor device, and the branches of the first doped region include a first branch extending in a first direction and a plurality of second branches extending in a second direction different from the first direction; the branches of the first doped region further include a plurality of third branches extending from the second branches in the first direction.