CN106656782B - Data packet forwarding processing system and method - Google Patents
Data packet forwarding processing system and method Download PDFInfo
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- CN106656782B CN106656782B CN201610858494.6A CN201610858494A CN106656782B CN 106656782 B CN106656782 B CN 106656782B CN 201610858494 A CN201610858494 A CN 201610858494A CN 106656782 B CN106656782 B CN 106656782B
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- H—ELECTRICITY
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- H04L45/00—Routing or path finding of packets in data switching networks
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Abstract
The invention provides a data packet forwarding processing system, which comprises a sending side unit and a receiving side unit, wherein the input end of the sending side unit and the output end of the receiving side unit are respectively connected with a plurality of switching chips, and the output end of the sending side unit and the input end of the receiving side unit are respectively connected with a line side interface; the data packets input by the line side interface are subjected to information identification by the receiving side unit and then are respectively sent to the corresponding exchange chips. The invention also provides a data packet forwarding processing method. The invention effectively solves the problem that a large-capacity interface and a small-capacity interface of the communication equipment are incompatible, and simultaneously solves the problem of data packet forwarding processing between the large-capacity interface and the small-capacity interface. The system and the method of the system not only have simple realization and low use cost, but also are more convenient and faster, have high forwarding speed and effectively improve the transmission speed.
Description
Technical Field
The present invention relates to network communications, and in particular, to a system and method for forwarding and processing data packets.
Background
With the development of network technology, the wide application of 40G and 100G high-speed interface technologies will bring great opportunities for network equipment upgrading. Interface upgrades by chip and device manufacturers also introduce some interface problems. When the 40G and 100G interfaces are applied, the problem that the interface of the originally used internal exchange chip does not support or the interface of the new exchange chip does not support well becomes a problem that the equipment manufacturer is compatible with the external high-speed interface of the original network equipment. The device price is mainly reflected in the single port price. Therefore, reducing the processing cost of the single-port service is also a main means for improving the product competitiveness of each manufacturer.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the problems in the prior art, the invention provides a data packet forwarding processing system which effectively solves the problem of compatibility between a high-speed interface and a switching chip.
The technical scheme is as follows: the invention provides a data packet forwarding processing system, which comprises a sending side unit and a receiving side unit, wherein the input end of the sending side unit and the output end of the receiving side unit are respectively connected with a plurality of switching chips, and the output end of the sending side unit and the input end of the receiving side unit are respectively connected with a line side interface; the data packets input by the line side interface are subjected to information identification by the receiving side unit and then are respectively sent to the corresponding exchange chips.
Further, the sending side unit and the receiving side unit are integrated in the FPGA chip, and the input and the output of the sending side unit and the receiving side unit are realized through a port of the FPGA chip. Such use is less costly.
Further, the sending side unit comprises a switching receiving unit, a packet cache convergence module, a sending cache control module and an interface sending module; the exchange receiving module receives a data packet input by the exchange chip and sends the data packet to the packet cache convergence module; the packet cache convergence module converges and caches the received data packets; the packet cache convergence module sends the cached data packet to the sending cache control module, the sending cache control module temporarily stores the data packet meeting the line speed, and sends the temporarily stored sending data packet to the interface sending module, and the data packet is sent to the line side interface through the interface sending module.
Further, the receiving side unit comprises an interface receiving module, a cache module, a packet identification module, a packet information module, a table look-up module, a packet cache processing module and an exchange sending module; the interface receiving module is used for receiving a data packet sent by a line side interface and sending the received data packet to the cache module; the cache module is used for caching the data packet, and when the data packet is cached in the cache module, the cache module outputs the data packet to the packet identification module and the packet information module; the packet identification module acquires quintuple information of a data packet and sends the acquired quintuple information to the table look-up module, the table look-up module comprises an external memory, the external memory is used for storing and setting corresponding table items between a data packet receiving port and the data packet, the table look-up module acquires a table look-up address through a configured quintuple processing method and inquires the table items in the external memory QDR according to the acquired table look-up address; extracting corresponding configuration information and data packet forwarding information from the table entry; and sending to a packet information module; the packet information module judges whether the data packet has corresponding configuration information, if so, the configuration information of the obtained data packet and the forwarding information of the data packet are carried and then the data packet is sent to the packet cache processing module in a turn-around mode, and if the data packet does not have corresponding configuration information, the data packet is directly discarded or the forwarding purpose is randomly selected; the packet caching processing module caches data packets of all forwarding purposes and then sends the data packets to the sending switching module; and the exchange sending module encapsulates the data packet forwarding information and the data packet and then sends the encapsulated data packet forwarding information and the encapsulated data packet to the exchange chip.
Further, the external memory is a quadruple rate static memory (hereinafter abbreviated as QDR).
The invention also provides a data packet forwarding processing method based on the data packet forwarding processing system, which comprises the following steps: establishing a database of corresponding table entries between a data packet receiving port and a data packet in a table look-up module; when the exchange chip sends data to the line side interface, the exchange receiving module receives a data packet sent by the exchange chip and sends the data packet to the packet cache convergence module; the packet cache convergence module converges and caches the received data packets; the packet cache convergence module sends the cached data packet to the sending cache control module, the sending cache control module temporarily stores the data packet meeting the line speed and sends the temporarily stored sending data packet to the interface sending module, and the data packet is sent to the line side interface through the interface sending module; when the line side interface needs to start data to the exchange chip, the interface receiving module receives a data packet sent by the line side interface and sends the received data packet to the cache module; the cache module caches the data packet, and when the data packet is cached in the cache module, the cache module outputs the data packet to the packet identification module and the packet information module; the packet identification module acquires quintuple information of a data packet and sends the acquired quintuple information to the table look-up module, the table look-up module acquires a table look-up address through a configured quintuple processing method and establishes a database of corresponding table entries between a data packet receiving port and the data packet in the table look-up module for query; extracting corresponding configuration information and data packet forwarding information from the table entry; and sending to a packet information module; the packet information module judges whether the data packet has corresponding configuration information, if the data packet has the configuration information, the obtained configuration information and the data packet forwarding information of the data packet are carried and then the data packet is sent to the packet cache processing module in a turn-around mode, and if the data packet does not have the corresponding configuration information or does not obtain a corresponding quintuple, the data packet is directly discarded or the forwarding purpose is randomly selected; the packet caching processing module caches each interface data packet and then sends the interface data packet to the sending exchange module; and the exchange sending module packages the packet information and the data packet and sends the package information and the data packet to the exchange chip.
Has the advantages that: compared with the prior art, the invention connects the large-capacity interface and the small-capacity interface through the FPGA chip and performs convergence or splitting processing on the received data packet, thereby effectively solving the problem that the large-capacity interface and the small-capacity interface of the communication equipment are incompatible and simultaneously solving the problem of data packet forwarding processing between the large-capacity interface and the small-capacity interface. The system and the method of the system not only have simple realization and low use cost, but also are more convenient and faster, have high forwarding speed and effectively improve the transmission speed.
Drawings
FIG. 1 is a schematic diagram of the present invention;
FIG. 2 is a schematic structural view of the present invention;
fig. 3 is a flow chart of the receiving side unit forwarding data packets in the present invention.
Detailed Description
The invention is further explained below with reference to the drawings.
As shown in fig. 1, the system for forwarding a data packet according to the present invention implements a function of forwarding a data packet based on an FPGA chip, wherein the FPGA chip is connected to a line side interface, a QDR database, and a switch chip. After the data packet is input and the table entries in the external QDR are inquired, the related information is packaged into the data packet and then is distributed to each system side interface. Forwarding to a switching chip through a system side interface; the transmitted data packet is received and cached by the system side interface, and the data packet is converged to the interface to be transmitted and cached and then is transmitted out through the interface.
As shown in fig. 2, a data packet forwarding processing system provided by the present invention mainly includes a sending side unit and a receiving side unit, an input end of the sending side unit and an output end of the receiving side unit are respectively connected to a plurality of switch chips, and an output end of the sending side unit and an input end of the receiving side unit are respectively connected to a line side interface; the data packets input by the line side interface are subjected to information identification by the receiving side unit and then are respectively sent to the corresponding exchange chips.
The sending side unit comprises a switching receiving unit, a packet cache convergence module, a sending cache control module and an interface sending module; the exchange receiving module receives a data packet input by the exchange chip and sends the data packet to the packet cache convergence module; the packet cache convergence module converges and caches the received data packets; the packet cache convergence module sends the cached data packet to the sending cache control module, the sending cache control module temporarily stores the data packet meeting the line speed, the temporarily stored sending data packet is sent to the interface sending module, and the data packet is sent to the line side interface through the interface sending module. The packet cache convergence module may adopt a 10G interface, or may adopt an internal interface with a large bandwidth, such as 100G interlaken.
The receiving side unit comprises an interface receiving module, a cache module, a packet identification module, a packet information module, a table look-up module, a packet cache processing module and an exchange sending module; the interface receiving module is used for receiving the data packet sent by the line side interface and sending the received data packet to the cache module; the buffer module is used for buffering the data packet. As shown in fig. 3, when a data packet is cached in the cache module, the cache module outputs the data packet to the packet identification module and the packet information module; the packet identification module acquires quintuple information of a data packet, wherein the quintuple information generally refers to a source IP address, a source port number, a destination IP address, a destination port number and a transport layer protocol, and sends the acquired quintuple information to the table look-up module; if no quintuple information exists, judging whether the mode is a discarding mode, if the mode is the discarding mode, directly discarding, if the mode is not the discarding mode, randomly configuring port information, and sending the configured port information to a packet information module. The table look-up module comprises an external memory, and the external memory is used for storing and setting corresponding table entries between the data packet receiving port and the data packet. The table look-up module obtains a table look-up address through a configured quintuple processing method and queries the table entry in the external memory QDR according to the obtained table look-up address; extracting corresponding configuration information and data packet forwarding information from the table entry, wherein 16-bit data corresponding to each address in the table entry is provided, the first bit to the fifteenth bit represent transmitted port information, and if the corresponding bit is 1, transmitting the data packet to the corresponding port; the 16 th bit is configuration information, if the 16 th bit is 1, the configuration is performed, a corresponding sending port exists, and if the 16 th bit is 0, the configuration is not performed; sending the inquired data to a packet information module; the packet information module judges whether the data packet has corresponding configuration information, if the data packet has the configuration information, the obtained configuration information and the data packet forwarding information of the data packet are carried and then the data packet is sent to the packet cache processing module in a turn-around mode, and if the data packet does not have the corresponding configuration information or does not obtain a corresponding quintuple, the data packet is directly discarded or the forwarding purpose is randomly selected; the packet caching processing module caches each interface data packet and then sends the interface data packet to the sending exchange module; and the exchange sending module packages the packet information and the data packet and sends the package information and the data packet to the exchange chip.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A packet forwarding processing system, characterized by: the circuit comprises a sending side unit and a receiving side unit, wherein the input end of the sending side unit and the output end of the receiving side unit are respectively connected with a plurality of switching chips, and the output end of the sending side unit and the input end of the receiving side unit are respectively connected with a line side interface; the data packets input by the line side interface are subjected to information identification by the receiving side unit and then are respectively sent to the corresponding exchange chips;
the transmitting side unit and the receiving side unit are integrated in an FPGA chip, and the input and the output of the transmitting side unit and the receiving side unit are realized through a port of the FPGA chip;
the receiving side unit comprises an interface receiving module, a cache module, a packet identification module, a packet information module, a table look-up module, a packet cache processing module and an exchange sending module; the interface receiving module is used for receiving a data packet sent by a line side interface and sending the received data packet to the cache module; the cache module is used for caching the data packet, and when the data packet is cached in the cache module, the cache module outputs the data packet to the packet identification module and the packet information module; the packet identification module acquires quintuple information of a data packet and sends the acquired quintuple information to the table look-up module, the table look-up module comprises an external memory, the external memory is used for storing and setting corresponding table items between a data packet receiving port and the data packet, the table look-up module acquires a table look-up address through a configured quintuple processing method and inquires the table items in the external memory QDR according to the acquired table look-up address; extracting corresponding configuration information and data packet forwarding information from the table entry; and sending to a packet information module; the packet information module judges whether the data packet has corresponding configuration information, if so, the configuration information of the obtained data packet and the forwarding information of the data packet are carried and then the data packet is sent to the packet cache processing module in a turn-around mode, and if the data packet does not have corresponding configuration information, the data packet is directly discarded or the forwarding purpose is randomly selected; the packet caching processing module caches data packets of all forwarding purposes and then sends the data packets to the switching sending module; and the exchange sending module encapsulates the data packet forwarding information and the data packet and then sends the encapsulated data packet forwarding information and the encapsulated data packet to the exchange chip.
2. The packet forwarding processing system of claim 1, wherein: the sending side unit comprises a switching receiving unit, a packet cache convergence module, a sending cache control module and an interface sending module; the exchange receiving module receives a data packet input by the exchange chip and sends the data packet to the packet cache convergence module; the packet cache convergence module converges and caches the received data packets; the packet cache convergence module sends the cached data packet to the sending cache control module, the sending cache control module temporarily stores the data packet meeting the line speed, and sends the temporarily stored sending data packet to the interface sending module, and the data packet is sent to the line side interface through the interface sending module.
3. The packet forwarding processing system of claim 1, wherein: the external memory is a quadruple rate static memory.
4. A packet forwarding processing method based on the packet forwarding processing system of claim 1, characterized in that: the method comprises the following steps: establishing a database of corresponding table entries between a data packet receiving port and a data packet in a table look-up module; when the exchange chip sends data to the line side interface, the exchange receiving module receives a data packet sent by the exchange chip and sends the data packet to the packet cache convergence module; the packet cache convergence module converges and caches the received data packets; the packet cache convergence module sends the cached data packet to the sending cache control module, the sending cache control module temporarily stores the data packet meeting the line speed and sends the temporarily stored sending data packet to the interface sending module, and the data packet is sent to the line side interface through the interface sending module; when the line side interface needs to start data to the exchange chip, the interface receiving module receives a data packet sent by the line side interface and sends the received data packet to the cache module; the cache module caches the data packet, and when the data packet is cached in the cache module, the cache module outputs the data packet to the packet identification module and the packet information module; the packet identification module acquires quintuple information of a data packet and sends the acquired quintuple information to the table look-up module, the table look-up module acquires a table look-up address through a configured quintuple processing method and establishes a database of corresponding table entries between a data packet receiving port and the data packet in the table look-up module for query; extracting corresponding configuration information and data packet forwarding information from the table entry; and sending to a packet information module; the packet information module judges whether the data packet has corresponding configuration information, if the data packet has the configuration information, the obtained configuration information and the data packet forwarding information of the data packet are carried and then the data packet is sent to the packet cache processing module in a turn-around mode, and if the data packet does not have the corresponding configuration information or does not obtain a corresponding quintuple, the data packet is directly discarded or the forwarding purpose is randomly selected; the packet caching processing module caches each interface data packet and then sends the interface data packet to the exchange sending module; and the exchange sending module packages the packet information and the data packet and sends the package information and the data packet to the exchange chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1917479A (en) * | 2006-09-20 | 2007-02-21 | 华为技术有限公司 | Methods of data concourse, analysis, data retransmission, and data interchange |
| CN102457426A (en) * | 2010-10-25 | 2012-05-16 | 深圳中兴力维技术有限公司 | Convergent type Ethernet over plesiochronous digital hierarchy (EoPDH) network bridge equipment and data transmission method thereof |
| CN203984453U (en) * | 2014-07-15 | 2014-12-03 | 北京蛙视通信技术股份有限公司 | Industrial Ethernet switch |
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| US7440467B2 (en) * | 2004-05-05 | 2008-10-21 | Gigamon Systems Llc | Asymmetric packet switch and a method of use |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1917479A (en) * | 2006-09-20 | 2007-02-21 | 华为技术有限公司 | Methods of data concourse, analysis, data retransmission, and data interchange |
| CN102457426A (en) * | 2010-10-25 | 2012-05-16 | 深圳中兴力维技术有限公司 | Convergent type Ethernet over plesiochronous digital hierarchy (EoPDH) network bridge equipment and data transmission method thereof |
| CN203984453U (en) * | 2014-07-15 | 2014-12-03 | 北京蛙视通信技术股份有限公司 | Industrial Ethernet switch |
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