CN106611708B - A kind of semiconductor device and its preparation method, electronic device - Google Patents

Abstract

The invention relates to a semiconductor device, a preparation method thereof, and an electronic device. The method includes step S1: providing a semiconductor substrate, on which a pad oxide layer and a floating gate material layer are sequentially formed; step S2: performing LDD ion implantation, so as to expect in the semiconductor substrate Forming an LDD ion implantation region in the region where the source and drain are formed; step S3: forming an isolation material layer, a control gate material layer, and a mask layer on the floating gate material layer, and patterning the mask layer, the control gate material layer Layer, the isolation material layer and the floating gate material layer, so as to form a plurality of gate stacks spaced apart from each other on both sides of the LDD ion implantation region; step S4: perform on both sides of the gate stack Source and drain implantation to form source and drain surrounding the LDD ion implantation region. The method of the invention can improve the performance of the semiconductor device, and at the same time, the method can also ensure that the surface of the active region is clean and rough.

Description

A kind of semiconductor device and its preparation method, electronic device

technical field

The present invention relates to a semiconductor device, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device.

Background technique

With the rapid development of portable electronic devices (such as mobile phones, digital cameras, MP3 players, and PDAs, etc.), the requirements for data storage are getting higher and higher. Non-volatile flash memory has become the most important storage component in these devices due to its ability to save data even when power is off. Among them, because flash memory (flash memory) can achieve high chip storage density, and does not introduce new materials , The manufacturing process is compatible, therefore, it can be more easily and reliably integrated into own digital and analog circuits.

Non-Volatile Semiconductor Memory (Non-Volatile Semiconductor Memory) has become a popular field of memory family because of its characteristic of retaining information when power is turned off. Among them, the ETOX (Electron Tunneling Oxided device) structure is mainly composed of a substrate, a tunnel oxide layer, a polycrystalline floating gate (FG), an inter-gate insulating layer and a polycrystalline control gate (CG). ETOX memory is "written" or "erased" by injecting or pulling electrons into the floating gate. Due to the change of electrons in the floating gate, the threshold voltage of the memory cell will also change accordingly. When electrons are injected into the floating gate, the threshold voltage rises, which is defined as "1"; when electrons are pulled out of the floating gate, it is defined as "0".

As the size of semiconductor devices continues to decrease, the length of the floating gate and the width of the active region decrease, and their size becomes more important for ETOX. Among them, LDD ion implantation in the active area and source-drain implantation are more critical. Currently, LDD ion implantation is usually The LDD ion implantation is performed on both sides of the stack after forming the stack of the floating gate, isolation layer and control gate, but since the aspect ratio of the stack is 10:1, during the ion implantation process, if If the ion implantation is deep, it will affect the effective length of the unit device, which may cause source-drain breakthrough, and the control gate will not work normally; if the ion implantation is shallow, it will cause damage during contact hole etching and cause device function failure.

If LDD ion implantation is not performed, the ion concentration of the source and drain will be low, and parasitic capacitance will be generated between the drain terminal and the substrate. In order to make the device work normally, it is necessary to provide a larger voltage to the drain terminal, or the current becomes smaller, which cannot meet the requirements of the device. need.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

In order to solve the problems existing in the prior art, a method for preparing a semiconductor device is provided, including:

Step S1: providing a semiconductor substrate on which a pad oxide layer and a floating gate material layer are sequentially formed;

Step S2: performing LDD ion implantation to form an LDD ion implantation region in the semiconductor substrate where source and drain are expected to be formed;

Step S3: forming an isolation material layer, a control gate material layer, and a mask layer on the floating gate material layer, and patterning the mask layer, the control gate material layer, the isolation material layer, and the floating gate a material layer to form a plurality of gate stacks spaced apart from each other on both sides of the LDD ion implantation region;

Step S4: performing source-drain implantation on both sides of the gate stack to form source-drain surrounding the LDD ion implantation region.

Optionally, the step S3 includes:

Step S31: forming a shallow trench isolation structure in the floating gate material layer and the semiconductor substrate in a direction perpendicular to the extending direction of the LDD ion implantation region;

Step S32: Etching back the isolation material layer in the shallow trench isolation structure to expose part of the floating gate material layer;

Step S33: forming the isolation material layer, the control gate material layer and the mask layer on the floating gate material layer.

Optionally, the step S31 includes:

Step S311: forming a second mask layer on the floating gate material layer, and patterning the floating gate material layer, the semiconductor substrate, and the second mask layer, so that the ion implantation area of the LDD A shallow groove is formed in a direction perpendicular to the extending direction;

Step S32: filling the shallow trench with an isolation material to form the shallow trench isolation structure;

Step S33: removing the second mask layer.

Optionally, in the step S4, the aspect ratio of the gate stack in the source-drain implantation is 5:1.

Optionally, the energy of the LDD ion implantation is 15-30Kev.

Optionally, the dose of the LDD ion implantation is 3×10 ¹⁴ -5×10 ¹⁴ .

Optionally, before performing the source-drain implantation in the step S4, the step of forming a spacer on the sidewall of the gate stack is further included.

The present invention also provides a semiconductor device prepared based on the above method.

The present invention also provides an electronic device, including the above-mentioned semiconductor device.

In order to solve the problems in the prior art, the present invention provides a method for preparing a semiconductor device. In the method, after forming the floating gate layer, LDD ion implantation is performed, and the thickness of the floating gate layer is relatively small. Ensuring that the LDD ions enter the active area, the LDD ions entering the active area can help determine the concentration of source and drain ions to improve the performance of semiconductor devices, and at the same time, the method can also ensure that the surface of the active area is clean and rough.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. Embodiments of the present invention and their descriptions are shown in the drawings to explain the device and principle of the present invention. In the attached picture,

1a-1i are schematic diagrams of the fabrication process of the semiconductor device described in one embodiment of the present invention;

FIG. 2 is a flow chart of the manufacturing process of the semiconductor device described in one embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present invention, detailed steps and detailed structures will be provided in the following description, so as to illustrate the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

Embodiment one

A specific embodiment of the present invention will be described below in conjunction with the accompanying drawings, wherein, Figures 1a-1i are schematic diagrams of the manufacturing process of the semiconductor device described in one embodiment of the present invention; Figure 2 is a schematic diagram of the semiconductor device described in one embodiment of the present invention Flow chart of the preparation process.

First, step 101 is performed to provide a semiconductor substrate 101 on which a pad oxide layer is formed.

First, referring to FIG. 1a, FIG. 1a is a cross-sectional view of the semiconductor device along the Y-axis direction. Among them, Figures 1a-1b are cross-sectional views of the semiconductor device along the Y-axis direction; Figures 1c-1g are cross-sectional views of the semiconductor device along the X-axis direction; Figures 1h-1i are cross-sectional views of the semiconductor device along the X-axis direction Sectional view. Wherein the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), Silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

In addition, an active region may be defined on the semiconductor substrate 101 . Other active devices may also be included on the active area, which are not marked in the shown figures for convenience.

A pad oxide layer 102 is formed on the semiconductor substrate 101 , wherein the pad oxide layer 102 may be a dielectric material commonly used in the field, for example, an oxide may be selected.

The formation method of the pad oxide layer 102 may be a high temperature oxidation or deposition method, and is not limited to a certain method, and may be selected according to needs.

In the present invention, the _SiO2 layer is selected as the pad oxide layer 102, and the thickness of the pad oxide layer 102 can be 1-20nm, but it is not limited to this thickness, and those skilled in the art can adjust it as required, for better results.

In this step, as a specific implementation manner, the deposition method of the SiO ₂ layer may be thermal oxidation, atomic layer deposition, chemical vapor deposition, electron beam evaporation or magnetron sputtering.

Executing step 102, forming a floating gate material layer 103 and a first mask layer on the pad oxide layer 102, and performing LDD ion implantation, so as to form an LDD in a region where source and drain are expected to be formed in the semiconductor substrate ion implantation area.

Specifically, as shown in Figure 1a, the floating gate material layer is selected from semiconductor materials, such as silicon, polysilicon or Ge, etc., and is not limited to a certain material, and the deposition method of the floating gate material layer can be selected from molecular beam epitaxy. (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG).

In this embodiment, a floating gate material layer of polysilicon is formed, and the polysilicon is formed by an epitaxial method. Specifically, silicon is used as an example for further illustration in a specific embodiment, and the reaction gas may include hydrogen (H ₂ ) carried four At least one of silicon chloride (SiCl ₄ ) or trichlorosilane (SiHCl ₃ ), silane (SiH ₄ ) and dichlorosilane (SiH ₂ Cl ₂ ) etc. enters the reaction chamber where the silicon substrate is placed. The reaction chamber carries out a high-temperature chemical reaction to reduce or thermally decompose the silicon-containing reaction gas, and the resulting silicon atoms grow epitaxially on the surface of the pad oxide layer.

In this step, a first mask layer is formed on the floating gate material layer 103 , where the first mask layer can be a commonly used mask, for example, a photoresist layer can be used.

Patterning the first mask layer to form an opening, and then performing LDD ion implantation using the first mask layer as a mask to form an LDD ion implantation region along the X-axis direction on the semiconductor substrate.

Wherein, in this step, the floating gate material layer has a small thickness to ensure that the LDD ions enter the active region, and the LDD ions entering the active region can help determine the concentration of source and drain ions.

Wherein, the thickness of the floating gate material layer is not limited to a certain value range, and the aspect ratio of the gate stack formed by forming the floating gate, isolation layer, control gate and mask layer is 5:1, that is, Can.

Wherein, the energy of the LDD ion implantation is 15-30Kev. The dose of the LDD ion implantation is 3×10 ¹⁴ -5×10 ¹⁴ .

The LDD ion implantation is performed after depositing the floating gate material layer, and the pad oxide layer 102 and the floating gate material layer are used as protection to keep the surface of the active region rough and prevent electrons from source-drain punch-through .

Executing step 103, forming a second mask layer on the floating gate material layer, patterning the floating gate material layer, the semiconductor substrate and the second mask layer, so as to perform ion implantation with the LDD Shallow trenches are formed in a direction perpendicular to the direction in which the region extends.

Specifically, as shown in FIG. 1c, in this step, the mask layer may be a hard mask layer, such as SiN, to protect the floating gate layer from damage during the shallow trench formation process.

Next, a dry etching process is performed to sequentially etch the hard mask layer 104 , the floating gate material layer, the pad oxide layer and the semiconductor substrate 101 to form shallow trenches. Specifically, a patterned photoresist layer can be formed on the hard mask layer, and the hard mask layer is dry-etched using the photoresist layer as a mask to transfer the pattern to the hard mask layer, and The floating gate material layer, the pad oxide layer and the semiconductor substrate 101 are etched using the photoresist layer and the hard mask layer as masks to form trenches.

Step 104 is executed to fill the trench with shallow trench isolation material to form a shallow trench isolation structure.

Specifically, as shown in FIG. 1d, a shallow trench isolation material 105 can be formed on the hard mask layer and in the trench, and the shallow trench isolation material can be silicon oxide, silicon oxynitride and/or other existing Low dielectric constant material; perform a chemical mechanical polishing process and stop on the hard mask layer to form shallow trench isolation structures.

Finally, the hard mask layer is removed. The method for removing the remaining hard mask layer may be a wet etching process, and since the etchant for removing the hard mask layer is well known in the art, it will not be described in detail.

Step 105 is executed, etching back the isolation material layer in the isolation structure to expose part of the floating gate material layer.

Specifically, as shown in FIG. 1e, in this step, part of the oxide in the shallow trench isolation structure is removed by blanket dry etching (Blank etch) to form a groove to expose the floating gate material layer. Part of the sidewall, this step is called the step of opening the memory cell (cell open, COPEN), that is, by removing part of the shallow trench isolation oxide between the floating gates, to expose part of the floating gate material layer structure , so as to form a stable contact with the floating gate structure after depositing the polysilicon layer, so as to avoid the problem of contact instability caused by the reduction of the device size.

Execute step 106, forming an isolation material layer, a control gate material layer, and a mask layer on the floating gate material layer, and patterning the floating gate material layer, the isolation material layer, the control gate material layer, and the The mask layer is used to form several grid stacks spaced apart from each other on both sides of the LDD ion implantation region.

Specifically, as shown in Figures 1f-1g, in this step, an isolation material layer, a control gate material layer, and a mask layer are formed on the floating gate material layer, and the floating gate material layer, the isolation material layer, and the isolation layer are patterned. material layer, the control gate material layer and a mask layer to form a gate stack.

Wherein, an isolation material layer is formed on the floating gate material layer, and the isolation material layer can be an insulating material commonly used in the field, such as ONO (oxide-nitride-oxide structural insulation isolation layer), but not limited to the materials described.

Then, a control gate material layer is formed above the isolation material layer, wherein the control gate material layer can be selected from the same material as the floating gate material layer, or a different material, for example, a metal gate can be used as a control grid.

Wherein, the mask layer can be a hard mask layer, for example, a SiN or metal hard mask layer can be selected, and is not limited to a certain one.

patterning the floating gate material layer, the isolation material layer, the control gate material layer and the mask layer to form the floating gate 102, the isolation layer 106, the control gate 107 and the mask layer 108 , to form the gate stack.

Specifically, the patterning method includes but is not limited to the following methods: forming an organic distribution layer (Organic distribution layer, ODL) on the mask layer 108, a silicon-containing bottom anti-reflective coating (Si-BARC), and A patterned photoresist layer is deposited on the silicon-containing bottom anti-reflective coating (Si-BARC), or only a patterned photoresist layer is formed on the control gate material layer, and the photoresist layer The pattern defines the pattern of the gate structure to be formed, and then the photoresist layer is used as a mask layer or the stack formed by etching the organic distribution layer, bottom anti-reflection coating, and photoresist layer is A mask is used to etch the floating gate material layer, the isolation material layer, the control gate material layer and the mask layer 108 .

Then remove the organic distribution layer (Organic distribution layer, ODL), silicon-containing bottom anti-reflection coating (Si-BARC), and photoresist layer.

In this step, dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching are selected.

Step 107 is executed to sequentially form a spacer layer 109 on the semiconductor substrate and the gate stack.

Specifically, as shown in FIG. 1h, in this step, a spacer material layer is deposited, and the spacer material layer is selected from oxide or nitride, or a combination of both.

The spacer material layer is etched to form the spacer 109 on the sidewall of the gate stack.

Wherein, in this step, dry etching or wet etching is selected, and in the present invention, CF etchant is preferred for etching, and the CF etchant is one of CF ₄ , CHF ₃ , C ₄ F ₈ and C ₅ F ₈ one or more species. In this embodiment, the dry etching can choose CF ₄ , CHF ₃ , plus one of N ₂ and CO ₂ as the etching atmosphere, wherein the gas flow rate is 10-200 sccm for CF ₄ and 10-200 sccm for CHF ₃ , N ₂ or CO ₂ or O ₂ 10-400sccm, the etching pressure is 30-150mTorr, and the etching time is 5-120s.

After the spacer is formed, source-drain implantation is performed on both sides of the gate stack to form source-drain surrounding the LDD ion implantation region, as shown in FIG. 1i.

So far, the introduction of the manufacturing process of the semiconductor device according to the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which will not be repeated here. Moreover, in addition to the above steps, the preparation method of this embodiment can also include other steps in the above steps or between different steps, and these steps can be realized by various processes in the prior art, here No longer.

In order to solve the problems in the prior art, the present invention provides a method for preparing a semiconductor device. In the method, after forming the floating gate layer, LDD ion implantation is performed, and the thickness of the floating gate layer is relatively small. Ensuring that the LDD ions enter the active area, the LDD ions entering the active area can help determine the concentration of source and drain ions to improve the performance of semiconductor devices, and at the same time, the method can also ensure that the surface of the active area is clean and rough.

Wherein, FIG. 2 is a process flow diagram of a semiconductor device in a specific embodiment of the present invention, specifically comprising the following steps:

Step S1: providing a semiconductor substrate on which a pad oxide layer and a floating gate material layer are sequentially formed;

Step S2: performing LDD ion implantation to form an LDD ion implantation region in the semiconductor substrate where source and drain are expected to be formed;

Step S3: forming an isolation material layer, a control gate material layer, and a mask layer on the floating gate material layer, and patterning the mask layer, the control gate material layer, the isolation material layer, and the floating gate a material layer to form a plurality of gate stacks spaced apart from each other on both sides of the LDD ion implantation region;

Step S4: performing source-drain implantation on both sides of the gate stack to form source-drain surrounding the LDD ion implantation region.

Embodiment two

The present invention also provides a semiconductor device, the semiconductor device includes a semiconductor substrate, the semiconductor substrate 101 can be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), on-insulator Stacked silicon (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

In addition, an active region may be defined on the semiconductor substrate 101 . Other active devices may also be included on the active area, which are not marked in the shown figures for convenience.

A pad oxide layer 102 is formed on the semiconductor substrate 101 , wherein the pad oxide layer 102 may be a dielectric material commonly used in the field, for example, an oxide may be selected.

When oxide is selected as the pad oxide layer 102 , the formation method of the pad oxide layer 102 can be high temperature oxidation or deposition, and is not limited to a certain method, and can be selected according to needs.

In the present invention, the _SiO2 layer is selected as the pad oxide layer 102, and the thickness of the pad oxide layer 102 can be 1-20nm, but it is not limited to this thickness, and those skilled in the art can adjust it as required, for better results.

A floating gate 103 , an isolation layer 106 , a control gate 107 and a mask layer 108 are sequentially formed on the pad oxide layer 102 to form the gate stack.

Wherein the floating gate layer is selected from a semiconductor material, such as silicon, polysilicon or Ge, etc., and is not limited to a certain material, and the deposition method of the floating gate layer can be selected from molecular beam epitaxy (MBE), metal organic chemical vapor deposition ( MOCVD), low pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxial growth (SEG).

The control gate can be made of the same material as that of the floating gate, or a different material can be used, for example, a metal gate can be formed as the control gate.

Wherein, the mask layer can be a hard mask layer, for example, a SiN or metal hard mask layer can be selected, and is not limited to a certain one.

A spacer 109 is formed on the sidewall of the gate stack

LDD ion implantation regions are formed on both sides of the gate stack, and source drains surrounding the LDD ion implantation regions are also formed on both sides of the gate stack.

Wherein, the energy of the LDD ion implantation in the LDD ion implantation region is 15-30Kev, and the dose of the LDD ion implantation is 3×10 ¹⁴ -5×10 ¹⁴ .

In the present application, since the spacer includes oxide and nitride deposited sequentially, and a stop layer is formed on the outside of the spacer as a protective layer, it avoids damage to the contact hole opening during etching. The spacer causes damage, and the cycle performance of the semiconductor device prepared by the method is greatly improved, the threshold voltage stability is higher, and the yield and performance of the NOR flash memory are further improved.

Embodiment three

The present invention also provides an electronic device, including the semiconductor device described in the second embodiment. Wherein, the semiconductor device is the semiconductor device described in the second embodiment, or the semiconductor device obtained according to the preparation method described in the first embodiment.

The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (9)

1. a kind of preparation method of semiconductor devices, comprising:

Step S1: semiconductor substrate is provided, is sequentially formed with pad oxide layer and floating gate material on the semiconductor substrate Layer；

Step S2: executing LDD ion implanting, with formed in the expected region for forming source and drain in the semiconductor substrate LDD from Sub- injection zone；

Step S3: spacer material layer, control gate material layer and mask layer are formed on the floating gate material layer, is covered described in patterning Film layer, the control gate material layer, the spacer material layer and the floating gate material layer, in the LDD ion implanted regions Two sides form several gate stacks being spaced apart from each other；

Step S4: source and drain injection is executed in the two sides of the gate stack, is surrounded with being formed as the LDD ion implanted regions Source and drain.

2. the method according to claim 1, wherein the step S3 includes:

Step S31: in the floating gate material layer and the semiconductor substrate with the LDD ion implanted regions extending direction phase Vertical side is upwardly formed fleet plough groove isolation structure；

Step S32: the spacer material layer in fleet plough groove isolation structure described in etch-back, with floating gate material layer described in exposed portion；

Step S33: the spacer material layer, the control gate material layer and the exposure mask are formed on the floating gate material layer Layer.

3. according to the method described in claim 2, it is characterized in that, the step S31 includes:

Step S311: forming the second mask layer on the floating gate material layer, patterns the floating gate material layer, the semiconductor Substrate and second mask layer, to be upwardly formed shallow ridges in the side perpendicular with the LDD ion implanted regions extending direction Slot；

Step S32: filling isolated material in the shallow trench, to form the fleet plough groove isolation structure；

Step S33: removal second mask layer.

4. the method according to claim 1, wherein in the step S4, described in source and drain injection The depth-width ratio of gate stack is 5:1.

5. the method according to claim 1, wherein the energy of the LDD ion implanting is 15-30Kev.

6. the method according to claim 1, wherein the dosage of the LDD ion implanting is 3 × 10¹⁴-5× 10¹⁴cm^-2。

7. the method according to claim 1, wherein injecting it in the execution source and drain in the step S4 Before, it may further include the step of clearance wall is formed on the side wall of the gate stack.

8. a kind of semiconductor devices being prepared based on method described in one of claim 1 to 7.

9. a kind of electronic device, including semiconductor devices according to any one of claims 8.