CN106610814B - Shared switch capacitor true random number generator and method for generating true random number - Google Patents
Shared switch capacitor true random number generator and method for generating true random number Download PDFInfo
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Abstract
The invention provides a shared switch capacitor true random number generator, which comprises a first true random number generating unit and a second true random number generating unit, wherein the first true random number generating unit and the second true random number generating unit are connected in series in an end-to-end connection mode to form a loop, the first true random number generating unit and the second true random number generating unit are provided with shared operational amplifiers, the first true random number generating unit completes random number generating operation under the control of a first clock control signal and a second clock control signal, and the second true random number generating unit alternatively completes random number generating operation under the control of the first clock control signal and the second clock control signal. The invention also provides a method of operating the shared switched capacitor random number generator. By the technical scheme of the invention, the circuit can be simplified to reduce the power consumption of the circuit and the area of the circuit.
Description
Technical Field
The present invention relates to the field of true random number generators, and more particularly, to a shared-capacitor (SC) True Random Number Generator (TRNG) and an operating method thereof.
Background
True random number generators are an important component of information security systems and are widely used in applications such as data encryption, digital signatures, and authentication. The randomness, reliability, speed, etc. of the true random number generator are important considerations.
True Random Number Generators (TRNGs) are known with various generation principles, such as: a thermal noise amplification mode, a low-frequency clock sampling high-frequency standard clock mode with noise, a chaos principle based on a discrete one-dimensional nonlinear equation and the like. These generation principles each have advantages and are generally selected according to different application requirements. Compared with other principles, the true random generator based on the chaos principle and realized by using the switched capacitor has the advantages that the circuit is easier and more accurate to realize, and the generated random number has the best randomness.
In true random number generators based on the chaos principle, a discrete one-dimensional nonlinear equation is generally used, as shown in the following equation (1-1). The discrete time iteration result generated by the equation shows the characteristic of chaos, the long-term state of the discrete time iteration result has the characteristics of being unpredictable, sensitive to an initial value and the like, and the discrete time iteration result can be used as a principle of generating a true random number and is also one of ideal principles of generating the true random number. The corresponding function is shown in fig. 1.
The switched capacitor circuit capable of implementing the equation shown in equation (1-1) requires a negative feedback circuit composed of an operational amplifier and a capacitor to perform multiplication and subtraction operations, wherein the capacitor is used to perform sampling on an input signal, and then the capacitor and the operational amplifier are used to perform addition and subtraction operations and multiplication by 2 operations, that is, random number generation operations include sampling operations and operational operations. The operational amplifier is in an idle, unused state during the sampling phase.
Fig. 2 shows a pipelined ADC-based true random number generator looped by cascading 8 pipelined ADC conversion stages. However, the true random number generator shown in fig. 2 has a disadvantage of large circuit scale and high complexity, which results in large chip occupation area and large power consumption of the true random number generator.
Therefore, in the field of true random number generation, how to reduce the power consumption of a chip and reduce the number of circuit elements in a true random number generator to reduce the chip area is an important research direction.
Disclosure of Invention
The inventors of the present invention have actively studied and proposed the present invention to solve the problems of the prior art.
According to one aspect of the present invention, a shared switched capacitor true random number generator is provided, which includes a first true random number generation unit and a second true random number generation unit, the first true random number generation unit and the second true random number generation unit are connected in series in an end-to-end manner to form a loop, the first true random number generation unit and the second true random number generation unit have a shared operational amplifier, and the first true random number generation unit and the second true random number generation unit alternately perform a random number generation operation under the control of a first clock control signal and a second clock control signal, respectively.
Preferably, the first true random number generating unit and the second true random number generating unit further share a first switch group, a reference voltage generating circuit, and a switch timing control circuit for generating a first clock control signal and a second clock control signal, the switches in the first switch group are turned on or off by the control of the first clock control signal and the second clock control signal, and each of the first true random number generating unit and the second true random number generating unit further includes: a quantization level selection circuit for generating a random number from an output from the operational amplifier and a reference voltage generated by the reference voltage generation circuit under control of the first clock control signal or the second clock control signal generated by the switching timing control circuit; a second switch group, wherein the switches in the second switch group are closed or opened under the control of the first clock control signal and the second clock control signal generated by the switch timing control circuit; and the first capacitor and the second capacitor are used for completing the sampling or random number generation operation of the true random number generation unit together with the quantization level selection circuit and the operational amplifier under the condition that the switches in the first switch group and the second switch group are opened or closed under the control of the first clock control signal and the second clock control signal.
In one embodiment, the first capacitance and the second capacitance are the same and matched, or preferably, the first capacitance and the second capacitance in the first true random number generating unit and the second true random number generating unit are the same and matched.
Further, the quantization level selection circuit includes: a detection correction circuit for determining whether or not the output of the operational amplifier exceeds a predetermined threshold value, and correcting the output of the operational amplifier if the threshold value is exceeded; a comparator having a latch function for comparing an output of the operational amplifier with a reference voltage and outputting a logic signal under control of the first clock control signal or the second clock control signal; a multiplexer for selecting one of the reference voltages generated by the output reference voltage generating circuit according to the logic signal; and a post-processor post-processing the logic signal to generate a random number.
Specifically, under control of the first clock control signal and the second clock control signal: during a first half cycle of one clock cycle, a first set of switches in the first set of switches, a first set of switches in the second set of switches of the first true random number generating unit, and a second set of switches in the second set of switches of the second true random number generating unit are closed and a second set of switches in the first set of switches, a second set of switches in the second set of switches of the first true random number generating unit, and a first set of switches in the second set of switches of the second true random number generating unit are open such that: the inverting input end of the operational amplifier is connected with one end of a first capacitor and one end of a second capacitor of the second true random number generating unit through a first switch group, the second output of the operational amplifier is connected with the input of the quantization level selection circuit of the first true random number generating unit and is connected with the other end of a second capacitor of the second true random number generating unit through a second switch group of the second true random number generating unit, the other end of the first capacitor of the second true random number generating unit is connected with the output of the quantization level selection circuit of the second true random number generating unit through a second switch group of the second true random number generating unit, one end of the first capacitor and one end of the second capacitor of the first true random number generating unit are connected with the reference voltage generated by the reference voltage generating circuit through a first switch group and the other end of the first capacitor is connected with the second output of the operational amplifier through a second switch group of the first true random number generating unit, the first true random number generating unit completes the sampling operation and the second true random number generating unit completes the random number generating operation; and in a second half cycle of one clock cycle, the second set of switches in the first set of switches, the second set of switches in the second set of switches of the first true random number generating unit and the first set of switches in the second set of switches of the second true random number generating unit are closed and the first set of switches in the first set of switches, the first set of switches in the second set of switches of the first true random number generating unit and the second set of switches in the second set of switches of the second true random number generating unit are open, such that: the non-inverting input end of the operational amplifier is connected with one end of a first capacitor and one end of a second capacitor of the first true random number generating unit through a first switch group, the first output of the operational amplifier is connected with the input of a quantization level selecting circuit of the second true random number generating unit and is connected with the other end of the first capacitor of the first true random number generating unit through a second switch group of the first true random number generating unit, the other end of the second capacitor of the first true random number generating unit is connected with the output of the quantization level selecting circuit of the first true random number generating unit through a second switch group of the first true random number generating unit, one end of a first capacitor and one end of a second capacitor of the second true random number generating unit are connected with a reference voltage generated by a reference voltage generating circuit through the first switch group and the other end of the first capacitor is connected with the first output of the operational amplifier through a second switch group of the second true random number generating unit, the second true random number generating unit thereby completes the sampling operation and the first true random number generating unit completes the random number generating operation.
Preferably, in one clock cycle, the duty ratios of the first and second clock control signals are less than 50% and the first and second clock control signals do not overlap each other to have a dead time.
According to another aspect of the invention, there is provided a method of operating a shared switched-capacitor true random number generator, wherein the switched-capacitor true random number generator comprises a first true random number generating unit and a second true random number generating unit, the method comprising: connecting a first true random number generating unit and a second true random number generating unit in series in an end-to-end connection mode to form a loop, wherein the first true random number generating unit and the second true random number generating unit are provided with a shared operational amplifier; and controlling the first true random number generating unit and the second true random number generating unit respectively by using the first clock control signal and the second clock control signal to alternately complete random number generating operation.
Preferably, the first true random number generating unit and the second true random number generating unit further share a first switch group, a reference voltage generating circuit, and a switch timing control circuit for generating a first clock control signal and a second clock control signal, the switches in the first switch group are closed or opened by the control of the first clock control signal and the second clock control signal, and in each of the first true random number generating unit and the second true random number generating unit: generating a random number from an output from the operational amplifier and a reference voltage generated by the reference voltage generating circuit under control of the first clock control signal or the second clock control signal by using a quantization level selecting circuit; closing or opening switches in the second switch group by using the first clock control signal and the second clock control signal; and under the condition that the switches in the first switch group and the second switch group are opened or closed under the control of the first clock control signal and the second clock control signal, completing the sampling or random number generation operation of the true random number generation unit by using the first capacitor and the second capacitor together with the quantization level selection circuit and the operational amplifier.
Preferably, the first capacitance and the second capacitance are the same and matched, or more preferably, the first capacitance and the second capacitance in the first true random number generating unit and the second true random number generating unit are both the same and matched.
Further, in the quantization level selection circuit: determining whether the output of the operational amplifier exceeds a predetermined threshold value by using a detection correction circuit, and correcting the output of the operational amplifier if the output of the operational amplifier exceeds the threshold value; comparing the output of the operational amplifier with a reference voltage by using a comparator with a latch function, and outputting a logic signal under the control of a first clock control signal or a second clock control signal; selecting a reference voltage generated by the output reference voltage generating circuit according to the logic signal by using a multiplexer; and post-processing the logic signal with a post-processor to generate a random number.
Specifically, under control of the first clock control signal and the second clock control signal: during a first half cycle of one clock cycle, a first set of switches in the first set of switches, a first set of switches in the second set of switches of the first true random number generating unit, and a second set of switches in the second set of switches of the second true random number generating unit are closed and a second set of switches in the first set of switches, a second set of switches in the second set of switches of the first true random number generating unit, and a first set of switches in the second set of switches of the second true random number generating unit are open such that: the inverting input end of the operational amplifier is connected with one end of a first capacitor and one end of a second capacitor of the second true random number generating unit through a first switch group, the second output of the operational amplifier is connected with the input of the quantization level selection circuit of the first true random number generating unit and is connected with the other end of a second capacitor of the second true random number generating unit through a second switch group of the second true random number generating unit, the other end of the first capacitor of the second true random number generating unit is connected with the output of the quantization level selection circuit of the second true random number generating unit through a second switch group of the second true random number generating unit, one end of the first capacitor and one end of the second capacitor of the first true random number generating unit are connected with the reference voltage generated by the reference voltage generating circuit through a first switch group and the other end of the first capacitor is connected with the second output of the operational amplifier through a second switch group of the first true random number generating unit, the first true random number generating unit completes the sampling operation and the second true random number generating unit completes the random number generating operation; and in a second half cycle of one clock cycle, the second set of switches in the first set of switches, the second set of switches in the second set of switches of the first true random number generating unit and the first set of switches in the second set of switches of the second true random number generating unit are closed and the first set of switches in the first set of switches, the first set of switches in the second set of switches of the first true random number generating unit and the second set of switches in the second set of switches of the second true random number generating unit are open, such that: the non-inverting input end of the operational amplifier is connected with one end of a first capacitor and one end of a second capacitor of the first true random number generating unit through a first switch group, the first output of the operational amplifier is connected with the input of a quantization level selecting circuit of the second true random number generating unit and is connected with the other end of the first capacitor of the first true random number generating unit through a second switch group of the first true random number generating unit, the other end of the second capacitor of the first true random number generating unit is connected with the output of the quantization level selecting circuit of the first true random number generating unit through a second switch group of the first true random number generating unit, one end of a first capacitor and one end of a second capacitor of the second true random number generating unit are connected with a reference voltage generated by a reference voltage generating circuit through the first switch group and the other end of the first capacitor is connected with the first output of the operational amplifier through a second switch group of the second true random number generating unit, the second true random number generating unit thereby completes the sampling operation and the first true random number generating unit completes the random number generating operation.
Preferably, in one clock cycle, the duty ratios of the first and second clock control signals are less than 50% and the first and second clock control signals do not overlap each other to have a dead time.
In the technical scheme of the invention, by sharing the operational amplifier, circuit elements in the true random number generator can be reduced to reduce the chip area, and by alternately controlling the true random number generating units, the reduction of power consumption can be realized.
Drawings
FIG. 1 is a schematic diagram of the principle of random number generation;
FIG. 2 is a diagram of a prior art pipelined ADC-based true random number generator;
FIG. 3 is a diagram of a shared switched capacitor true random number generator according to an embodiment of the present invention;
FIG. 4 is a timing diagram of control signals output by a switch timing control circuit according to the present invention;
FIG. 5 is a block diagram of a quantization level selection circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the circuit connections in the first state of a cycle according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the circuit connections in a second state of a cycle in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram of a circuit configuration of a shared operational amplifier according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a fully differential structural implementation of a shared switched capacitor true random number generator, according to an embodiment of the present invention; and
FIG. 10 is a flow chart of a method of operation of a shared switched capacitor true random number generator according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments and technical solutions of the present invention, the technical solutions of the present invention will be described in more detail with reference to the accompanying drawings and embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without inventive step, are within the scope of the present invention.
According to an embodiment of the present invention, there is provided a shared switched capacitor true random number generator, including a first true random number generation unit and a second true random number generation unit, the first and second true random number generation units being connected in series in an end-to-end manner to form a loop, the first and second true random number generation units having a shared operational amplifier, and the first true random number generation unit and the second true random number generation unit alternately performing a random number generation operation under control of a first clock control signal and a second clock control signal, respectively. By sharing the operational amplifier and alternately controlling the true random number generating units, the number of components used can be reduced to reduce the chip area and reduce the power consumption.
The following describes a specific implementation of the shared switched capacitor true random number generator of the present invention in detail with reference to the accompanying drawings.
FIG. 3 is a diagram of a shared switched capacitor true random number generator according to an embodiment of the present invention. As shown, the switched capacitor true random number generator includes: the shared operational amplifier 100, the shared switch timing control circuit 110, the quantization level selection circuit 120, the capacitor group 130, the switch group 140, the switch group 150, and the shared reference voltage generation circuit 160. Two TRNG units (hereinafter, referred to as TRNG unit a and TRNG unit B) capable of performing the operation function of the equation (1-1) are included, where TRNG unit a is composed of an operational amplifier 100, a switching timing control circuit 110, a reference voltage generation circuit 160, a quantization level selection circuit a, a switch group 150, and switch groups 140(S1-S4) and capacitor groups 130(C1 and C2) in the upper half of fig. 3, and TRNG unit B is composed of an operational amplifier 100, a switching timing control circuit 110, a reference voltage generation circuit 160, a quantization level selection circuit B, a switch group 150, and switch groups 140(S5-S8) and capacitor groups 130(C3 and C4) in the lower half of fig. 3. The components in which the TRNG units a and B share multiplexing in time division include an operational amplifier 100, a switch timing control circuit 110, a switch group 150, and a reference voltage generation circuit 160. It should be understood by those skilled in the art that TRNG units a and B may not share the switch timing control circuit, the switch group, and the reference voltage generating circuit but may have respective circuits.
Wherein the switch group 150 corresponds to a first switch group, the switches S10, S11 and S14 correspond to a first switch set of the first switch group, the switches S9, S12, S13 correspond to a second switch set of the first switch group, the switch group 140 corresponds to a second switch group, the switches S1 and S4 correspond to a second switch set of the second switch group of the first true random number generating unit, the switches S2 and S3 correspond to a first switch set of the second switch group of the first true random number generating unit, the switches S5 and S8 correspond to a second switch set of the second switch group of the second true random number generating unit, and the switches S6 and S7 correspond to a first switch set of the second switch group of the second true random number generating unit. Further, the capacitances C1 and C3 correspond to a first capacitance, and the capacitances C2 and C4 correspond to a second capacitance.
The shared operational amplifier 100 is a core element for performing the operation function of the above equation (1-1).
The switching timing control circuit 110 is capable of generating two-phase non-overlapping clock signals as shown in fig. 4. For controlling the on and off of the switches in the switch bank 140 and the switch bank 150, and for providing timing for the comparator 122 with latch function in the quantization level generation circuit 120.
The two capacitor banks 130 belong to two random number generation units, respectively, wherein the capacitor C1 and the capacitor C2, and the capacitors C3 and C4 are important elements for completing the formula (1-1), the capacitor C1 and the capacitor C2 are equal and need to be matched, and the capacitors C3 and C4 need to be matched. More preferably, the capacitances C1, C2, C3, C4 are all equal and need to be matched.
The switch group 140 and the switch group 150 perform the operation of the equation (1-1) by matching the internal switches according to the timing control signal output from the switching timing generation circuit 110.
The reference voltage generation circuit 160 is configured to generate a reference voltage Vref, a reference voltage Vr1, a reference voltage Vr2, a reference voltage Vr3, and a reference voltage Vr4, to supply the reference voltage Vref to the switch group 150, to supply the reference voltages Vr1, Vr2 to the latch-enabled comparator 122 in the quantization level selection circuit 120, and to supply the reference voltages Vr3, Vr4, and Vref to the multiplexer 123.
The quantization level generation circuit 120 is described in detail below with reference to fig. 5. As shown in fig. 5, the quantization level generation circuit 120 includes: a detection correction circuit 121, two comparators 122 with latch function, a multiplexer 123 and a digital post-processor 124.
The detection correction circuit 121 is configured to detect a voltage range of the input signal Vin (operation result of the TRNG unit a or TRNG unit B) of the quantization level generation circuit 120, and correct the output of the entire TRNG circuit after the input signal Vin exceeds a maximum threshold value outside a normal voltage range, so that the output of the TRNG returns to the normal range.
The non-inverting input terminal of the comparator 122 with latch function is connected to the input signal Vin, and the two inverting input terminals are respectively connected to the reference voltages Vr1 and Vr 2. Under the clock provided by the switching timing control circuit 110, logic signals D1 and D2 are output for the control inputs of the multiplexer 123 and the operation of the digital post-processor 124 to generate the final random number output.
The digital post-processor 124 is used to process the outputs D1 and D2 of the comparator 122 with latch function, thereby outputting the final random number output RNG. The algorithm of the digital post-processing may be a simple exclusive-or operation, or may be another algorithm that is complex and increases randomness, and the algorithm complexity of the digital post-processing is not limited herein.
As described above, in the above embodiment, the operation of the equation (1-1) can be alternately performed by two true random number generating units in a head-to-tail connection manner as a clock by sharing the multiplexing operational amplifier 100, the switch group 150, the switch timing control circuit 110, and the reference voltage generating circuit 160 in a time division manner. Thereby, an operational amplifier can be saved, and the circuit area and power consumption of the random number can be saved.
Referring back to FIG. 4, two non-overlapping clock output signals generated by the switch timing control circuit 110 are shown, CLK1 and CLK2, respectively. In one clock cycle, CLK1 is high and CLK2 is high, respectively, to define a Φ 1 state and a Φ 2 state. As can be seen from fig. 4, the durations of the high levels of CLK1 and CLK2 are slightly less than T/2, and the dead time is used to ensure that the switching process of switch group 140 and switch group 150 does not affect the normal operation result of the circuit.
Each TRNG unit needs two states (Φ 1 state and Φ 2 state) to complete the arithmetic function of expression (1-1), which is summarized as sampling operation and arithmetic operation (random number generation operation) on input. The two TRNG units finish sampling and operation operations in turn at intervals of half clock period, so that the operation relation of the formula (1-1) can be finished in one period. The two TRNG units perform sampling and operation operations (arithmetic and sampling operations) in the Φ 1 state (or Φ 2 state), respectively.
The specific operation of the circuit according to the embodiment of the present invention, i.e. the specific operation of the n-th cycle Φ 1 state and Φ 2 state defined in fig. 4, is described below with reference to fig. 6 and 7, respectively.
In FIG. 6, the nth period T is shownnIn the first state (Φ 1 state), the switching states of the switch group 140 and the switch group 150. Wherein TRNG unit B is at Tn-1Sample the input V1 at TnThe Φ 1 state of (1) is the operation of equation (1-1) input as V1. TRNG Unit A then at TnIs detected, the sampling operation of the output V2 of the TRNG unit B is completed in the Φ 1 state of (c).
Specifically, switches S2, S3, S5, S8, S10, S11, and S14 in switch group 140 and switch group 150 are closed, and the remaining switches are all open. The shared operational amplifier 100 and the capacitors C3 and C4 in the capacitor bank 130 form a negative feedback operational circuit of multiplication 2 and addition and subtraction operations, wherein the inverting input terminal of the shared operational amplifier 100 is connected to one end of the capacitors C3 and C4, the non-inverting input terminal thereof is connected to the reference voltage Vref provided by the reference voltage generating circuit 160 through the switch S11 of the switch bank 150, the output of the shared operational amplifier 100 in the Φ 1 state is V2, the other end of the capacitor C4 is connected to the output V2, the other end of the capacitor C3 is connected to the output Vout of the quantization level selecting circuit B120, and the shared operational amplifier output V2 is connected to the input Vin of the quantization level selecting circuit a 120. The TRNG unit B completes the operation in the Φ 1 state.
Meanwhile, in the Φ 1 state, one end of the capacitor bank 130, the capacitors C1 and C2 in the TRNG unit a is connected to the reference voltage Vref through the switch S10 of the switch bank 150, and the other input ends of the capacitors C1 and C2 are connected to the output end V2 of the shared operational amplifier through the switches S2 and S3 of the switch bank 140, thereby completing the sampling operation of the TRNG unit a. The quantization level selection circuit a120 performs voltage comparison of the output voltage V2, latches the comparison result, provides a quantization level for the operation stage of the TRNG unit a, and outputs the random number of the TRNG unit B in the current period to output RNG 1.
FIG. 7 shows the operation in the nth period TnIn the second state (Φ 2 state), the switching states of the switch group 140 and the switch group 150. Wherein TRNG unit A is at TnSample the input V2 at TnThe Φ 2 state of (1) is the operation of equation (1-1) input as V2. TRNG unit B completes the sampling operation of the output V1 of TRNG unit a in the Φ 2 state.
Specifically, switches S1, S4, S6, S7, S9, S12, and S13 in switch group 140 and switch group 150 are closed, and the remaining switches are all open. The shared operational amplifier 100 and the capacitors C1 and C2 in the capacitor bank 130 form a negative feedback operational circuit of multiplication 2 and addition and subtraction operations, wherein the non-inverting input terminal of the shared operational amplifier 100 is connected to one end of the capacitors C1 and C2, and the inverting input terminal thereof is connected to the reference voltage Vref provided by the reference voltage generating circuit 160 through the switch S13 in the switch bank 150, the output terminal of the shared operational amplifier in the Φ 2 state is V1, the other terminal of the capacitor C1 is connected to the output V1, the other terminal of the capacitor C2 is connected to the output Vout of the quantization level selection circuit a120, and the shared operational amplifier output V1 is connected to the input Vi n of the quantization level selection circuit B120. The TRNG unit a completes the operation in this Φ 2 state.
Meanwhile, in the Φ 2 state, one end of the capacitor bank 130, the capacitors C3 and C4 in the TRNG unit B is connected to the reference voltage Vref through the switch S12 of the switch bank 150, and the other input ends of the capacitors C3 and C4 are connected to the output end V1 of the shared operational amplifier through the switches S6 and S7 of the switch bank 140, thereby completing the sampling operation of the TRNG unit B. The quantization level selection circuit B120 performs voltage comparison of the output voltage V1, latches the comparison result, provides a quantization level for the operation stage of the following TRNG unit B, and outputs the random number of the TRNG unit a in the present cycle to output RNG 2.
The above-described sampling and operation operations of the two TRNG units of the nth period are repeated in each period before and after the nth period. Thus, both RNG1 and RNG2 produce a 1-bit binary random number output in each cycle.
The whole system continuously generates true random number output under the action of the clock.
Further, fig. 8 shows a structure of a shared operational amplifier 100 having a structure of a differential input, double single-ended output form. It should be understood that fig. 8 provides only one implementation of a shared operational amplifier and is not limited thereto, and that amplifiers that are similarly capable of performing this function may be used for operational amplifier 100. For example, fig. 9 shows a schematic diagram of a shared operational amplifier in a fully differential form according to an embodiment of the present invention, characterized in that the voltage is in a differential form throughout the sampling and operational phases. These structures will be apparent to those skilled in the art and will not be described in detail herein.
FIG. 10 is a flow diagram of a method of operating a shared switched-capacitor true random number generator according to an embodiment of the present invention, wherein the switched-capacitor true random number generator includes a first true random number generation unit and a second true random number generation unit.
As shown in fig. 10, the method includes: step S1002, connecting a first true random number generating unit and a second true random number generating unit in series in an end-to-end connection mode to form a loop, wherein the first true random number generating unit and the second true random number generating unit are provided with a shared operational amplifier; and step S1004 of alternately completing the random number generating operation by controlling the first true random number generating unit and the second true random number generating unit with the first clock control signal and the second clock control signal, respectively.
As described above, the key point of the present invention is to share the operational amplifier and alternately control the true random number generating units, and although the embodiment of the present invention only shows two true random number generating units, the skilled person can also think of the embodiment of the present invention that the switched capacitor true random number generator has an even number of true random number generating units, wherein the even number of true random number generating units also share the operational amplifier and alternately control the even number of true random number generating units by using the clock control signal, and the implementation principle and structure thereof are similar to those of the above-mentioned embodiment. Of course, an appropriate number of true random number generating units should be selected by taking comprehensive consideration of the cost that can be borne, the random number generation effect that needs to be achieved, and the like.
The embodiment provides a shared switched capacitor true random number generator and an operation method thereof, wherein TRNG units capable of completing the operation of the formula (1-1) are connected end to form a loop, and simultaneously, through the control of a clock, the two TRNG units alternately complete sampling and operation operations, and through the time-sharing shared multiplexing operational amplifier, the utilization efficiency of the 2-time-gain operational amplifier is improved while the true random numbers with the same yield and high performance are ensured to be generated, so that the circuit chip area and the power consumption required for generating the random numbers with the same yield are saved.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (12)
1. The utility model provides a shared switch capacitor true random number generator, its characterized in that, switch capacitor true random number generator includes first true random number generation unit and second true random number generation unit, first true random number generation unit with second true random number generation unit forms the loop with end to end's mode series connection together, first true random number generation unit with second true random number generation unit has shared operational amplifier, first true random number generation unit accomplishes the random number and generates the operation under the control of first clock control signal and second clock control signal, and second true random number generation unit also accomplishes random number in turn under the control of first clock control signal and second clock control signal and generates the operation.
2. The shared switched-capacitor true random number generator of claim 1, wherein the first and second true random number generation units further share a first switch set, a reference voltage generation circuit, and a switch timing control circuit for generating the first and second clock control signals, switches in the first switch set are closed or opened under control of the first and second clock control signals, and each of the first and second true random number generation units further comprises:
a quantization level selection circuit for generating a random number from an output from the operational amplifier and a reference voltage generated by the reference voltage generation circuit under control of a first clock control signal or a second clock control signal generated by the switching timing control circuit;
a second switch group in which switches are closed or opened under control of a first clock control signal and a second clock control signal generated by the switch timing control circuit; and
and the first capacitor and the second capacitor are used for completing the sampling or random number generation operation of the true random number generation unit together with the quantization level selection circuit and the operational amplifier under the condition that the switches in the first switch group and the second switch group are opened or closed under the control of the first clock control signal and the second clock control signal.
3. The shared switched-capacitor true random number generator of claim 2, wherein the first and second capacitors are the same and matched, or the first and second capacitors in the first and second true random number generation units are the same and matched.
4. The shared switched-capacitor true random number generator of claim 2, wherein the quantization level selection circuit further comprises:
a detection correction circuit for determining whether or not the output of the operational amplifier exceeds a predetermined threshold, and correcting the output of the operational amplifier if the threshold is exceeded;
a comparator having a latch function for comparing an output of the operational amplifier with the reference voltage and outputting a logic signal under the control of the first clock control signal or the second clock control signal;
a multiplexer for selectively outputting a reference voltage generated by the reference voltage generating circuit according to the logic signal; and
a post-processor that post-processes the logic signal to generate a random number.
5. The shared switched-capacitor true random number generator of claim 2, wherein under control of the first and second clock control signals:
during a first half cycle of a clock cycle, a first set of switches in the first set of switches, a first set of switches in the second set of switches of the first true random number generating unit, and a second set of switches in the second set of switches of the second true random number generating unit are closed and a second set of switches in the first set of switches, a second set of switches in the second set of switches of the first true random number generating unit, and a first set of switches in the second set of switches of the second true random number generating unit are open such that: operational amplifier's inverting input end passes through first switch block connects the first electric capacity of second true random number generation unit and the one end of second electric capacity just operational amplifier's second output connection the input of the quantization level selection circuit of first true random number generation unit and pass through the second switch block of second true random number generation unit connects the other end of the second electric capacity of second true random number generation unit, the other end of the first electric capacity of second true random number generation unit passes through the second switch block of second true random number generation unit connects the output of the quantization level selection circuit of second true random number generation unit, the first electric capacity of first true random number generation unit and the one end of second electric capacity pass through first switch block connects the reference voltage that reference voltage generation circuit generated and the other end pass through the second switch block of first true random number generation unit connects operational amplifier's first switch block Outputting, so that the first true random number generating unit completes a sampling operation and the second true random number generating unit completes a random number generating operation; and
in a second half of one clock cycle, the second set of switches in the first group of switches, the second set of switches in the second group of switches of the first true random number generating unit and the first set of switches in the second group of switches of the second true random number generating unit are closed and the first set of switches in the first group of switches, the first set of switches in the second group of switches of the first true random number generating unit and the second set of switches in the second group of switches of the second true random number generating unit are open, such that: the non inverting input end of the operational amplifier is connected with one end of a first capacitor and a second capacitor of the first true random number generating unit through the first switch set, the first output of the operational amplifier is connected with the input of a quantization level selection circuit of the second true random number generating unit and the second switch set of the first true random number generating unit is connected with the other end of the first capacitor of the first true random number generating unit, the other end of a second capacitor of the first true random number generating unit is connected with the second switch set of the first true random number generating unit, the output of the quantization level selection circuit of the first true random number generating unit is connected with the output of the quantization level selection circuit of the second true random number generating unit through the first switch set, the first capacitor of the second true random number generating unit and one end of the second capacitor are connected with the first switch set, the reference voltage generated by the reference voltage generating circuit and the other end of the second switch set of the second true random number generating unit are connected with the first switch set of the operational amplifier An output such that the second true random number generating unit completes the sampling operation and the first true random number generating unit completes the random number generating operation.
6. The shared switched-capacitor true random number generator of claim 5, wherein the duty cycle of the first and second clock control signals is less than 50% and the first and second clock control signals do not overlap each other to have dead time in one clock cycle.
7. A method of generating true random numbers with a switched capacitor true random number generator comprising a first true random number generating unit and a second true random number generating unit, the method comprising:
connecting the first true random number generating unit and the second true random number generating unit in series in an end-to-end connection mode to form a loop, wherein the first true random number generating unit and the second true random number generating unit are provided with a shared operational amplifier; and
the first true random number generating unit is controlled by a first clock control signal and a second clock control signal to perform a random number generating operation, and the second true random number generating unit is controlled by the first clock control signal and the second clock control signal to alternately perform a random number generating operation.
8. The method of claim 7, wherein the first true random number generating unit and the second true random number generating unit further share a first switch group, a reference voltage generating circuit, and a switch timing control circuit for generating the first clock control signal and the second clock control signal, wherein switches in the first switch group are closed or opened by the control of the first clock control signal and the second clock control signal, and wherein in each of the first true random number generating unit and the second true random number generating unit:
generating, with a quantization level selection circuit, a random number from an output from the operational amplifier and a reference voltage generated by the reference voltage generation circuit under control of the first clock control signal or the second clock control signal;
closing or opening switches in the second switch group by using the first clock control signal and the second clock control signal; and
and under the condition that the switches in the first switch group and the second switch group are opened or closed under the control of the first clock control signal and the second clock control signal, completing the sampling or random number generation operation of the true random number generation unit by utilizing a first capacitor and a second capacitor together with the quantization level selection circuit and the operational amplifier.
9. The method of claim 8, wherein the first and second capacitors are the same and matched, or wherein the first and second capacitors in the first and second true random number generating units are the same and matched.
10. The method of claim 8, wherein in the quantization level selection circuit:
determining with a detection correction circuit whether the output of the operational amplifier exceeds a predetermined threshold and correcting the output of the operational amplifier if the threshold is exceeded;
comparing the output of the operational amplifier with the reference voltage by using a comparator with a latch function, and outputting a logic signal under the control of the first clock control signal or the second clock control signal;
selecting and outputting a reference voltage generated by the reference voltage generating circuit according to the logic signal by using a multiplexer; and
post-processing the logic signal with a post-processor to generate a random number.
11. The method of claim 8, wherein under control of the first and second clock control signals:
during a first half cycle of a clock cycle, a first set of switches in the first set of switches, a first set of switches in the second set of switches of the first true random number generating unit, and a second set of switches in the second set of switches of the second true random number generating unit are closed and a second set of switches in the first set of switches, a second set of switches in the second set of switches of the first true random number generating unit, and a first set of switches in the second set of switches of the second true random number generating unit are open such that: operational amplifier's inverting input end passes through first switch block connects the first electric capacity of second true random number generation unit and the one end of second electric capacity just operational amplifier's second output connection the input of the quantization level selection circuit of first true random number generation unit and pass through the second switch block of second true random number generation unit connects the other end of the second electric capacity of second true random number generation unit, the other end of the first electric capacity of second true random number generation unit passes through the second switch block of second true random number generation unit connects the output of the quantization level selection circuit of second true random number generation unit, the first electric capacity of first true random number generation unit and the one end of second electric capacity pass through first switch block connects the reference voltage that reference voltage generation circuit generated and the other end pass through the second switch block of first true random number generation unit connects operational amplifier's first switch block Outputting, so that the first true random number generating unit completes a sampling operation and the second true random number generating unit completes a random number generating operation; and
in a second half of one clock cycle, the second set of switches in the first group of switches, the second set of switches in the second group of switches of the first true random number generating unit and the first set of switches in the second group of switches of the second true random number generating unit are closed and the first set of switches in the first group of switches, the first set of switches in the second group of switches of the first true random number generating unit and the second set of switches in the second group of switches of the second true random number generating unit are open, such that: the non inverting input end of the operational amplifier is connected with one end of a first capacitor and a second capacitor of the first true random number generating unit through the first switch set, the first output of the operational amplifier is connected with the input of a quantization level selection circuit of the second true random number generating unit and the second switch set of the first true random number generating unit is connected with the other end of the first capacitor of the first true random number generating unit, the other end of a second capacitor of the first true random number generating unit is connected with the second switch set of the first true random number generating unit, the output of the quantization level selection circuit of the first true random number generating unit is connected with the output of the quantization level selection circuit of the second true random number generating unit through the first switch set, the first capacitor of the second true random number generating unit and one end of the second capacitor are connected with the first switch set, the reference voltage generated by the reference voltage generating circuit and the other end of the second switch set of the second true random number generating unit are connected with the first switch set of the operational amplifier An output such that the second true random number generating unit completes the sampling operation and the first true random number generating unit completes the random number generating operation.
12. The method of claim 11, wherein a duty cycle of the first clock control signal and the second clock control signal is less than 50% and the first clock control signal and the second clock control signal do not overlap with each other to have a dead time in one clock cycle.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510695410.7A CN106610814B (en) | 2015-10-23 | 2015-10-23 | Shared switch capacitor true random number generator and method for generating true random number |
| TW105134077A TWI579764B (en) | 2015-10-23 | 2016-10-21 | Shared switched capacitor true random number generator and its method of generating true random number |
| PCT/CN2016/102836 WO2017067499A1 (en) | 2015-10-23 | 2016-10-21 | Shared switch-capacitor true random number generator and method therefor for generating true random number |
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| CN201510695410.7A CN106610814B (en) | 2015-10-23 | 2015-10-23 | Shared switch capacitor true random number generator and method for generating true random number |
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| CN106610814B true CN106610814B (en) | 2021-04-30 |
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| TW (1) | TWI579764B (en) |
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| CN110286878B (en) * | 2019-06-25 | 2021-06-01 | 电子科技大学 | A True Random Number Generator for MCU Switching Bridge Voltage at Random Intervals and Its Generating Method |
| CN114051607B (en) * | 2020-12-28 | 2024-11-19 | 深圳市汇顶科技股份有限公司 | ADC conversion unit, true random number generation method and device |
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| CN1420431A (en) * | 2002-12-12 | 2003-05-28 | 浙江大学 | Real random number generator |
| CN204216883U (en) * | 2014-12-04 | 2015-03-18 | 上海贝岭股份有限公司 | The background calibration circuit of pipeline ADC |
| CN104598198A (en) * | 2013-10-30 | 2015-05-06 | 国民技术股份有限公司 | True random number generator |
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| US5706218A (en) * | 1996-05-15 | 1998-01-06 | Intel Corporation | Random number generator |
| TWI272531B (en) * | 2003-07-17 | 2007-02-01 | Univ Nat Sun Yat Sen | Parameters programmable multi-bit random number generator |
| KR100594292B1 (en) * | 2004-09-09 | 2006-06-30 | 삼성전자주식회사 | Low Power Random Bit Generator and Random Number Generator |
| US20060098500A1 (en) * | 2004-11-09 | 2006-05-11 | Hongyi Chen | Truly random number generating circuit and method thereof |
| KR100725978B1 (en) * | 2005-07-06 | 2007-06-08 | 삼성전자주식회사 | Low Power Random Bit Generator and Generation Method Using Thermal Noise |
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- 2015-10-23 CN CN201510695410.7A patent/CN106610814B/en active Active
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- 2016-10-21 WO PCT/CN2016/102836 patent/WO2017067499A1/en not_active Ceased
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| CN1420431A (en) * | 2002-12-12 | 2003-05-28 | 浙江大学 | Real random number generator |
| CN104598198A (en) * | 2013-10-30 | 2015-05-06 | 国民技术股份有限公司 | True random number generator |
| CN204216883U (en) * | 2014-12-04 | 2015-03-18 | 上海贝岭股份有限公司 | The background calibration circuit of pipeline ADC |
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| 混沌随机数发生器的设计;王云峰;《半导体学报》;20051231;全文 * |
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| WO2017067499A1 (en) | 2017-04-27 |
| TWI579764B (en) | 2017-04-21 |
| TW201810021A (en) | 2018-03-16 |
| CN106610814A (en) | 2017-05-03 |
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