CN106603416B - A CDMA Routing Node Based on Parallel Structure CODEC - Google Patents
A CDMA Routing Node Based on Parallel Structure CODEC Download PDFInfo
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- CN106603416B CN106603416B CN201710045753.8A CN201710045753A CN106603416B CN 106603416 B CN106603416 B CN 106603416B CN 201710045753 A CN201710045753 A CN 201710045753A CN 106603416 B CN106603416 B CN 106603416B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/14—Routing performance; Theoretical aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/742—Route cache; Operation thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
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Abstract
The present invention relates to a kind of CDMA routing nodes based on parallel organization CODEC, it solves data in traditional CDMA network-on-chip routing node and jumps delay height, the problem that power consumption area is big and scalability is bad, including Port module, RC module, VA module, SA module and parallel organization CODEC module, Port module carries out storage to data packet and is forwarded to MUX data selector, and header packet information is transferred to RC module；RC module completes router-level topology according to the header packet information of data packet in FIFO buffer, and exports transmission request to VA module；VA module completes the distribution to junior's memory space, and be transferred to SA module according to transmission request and current resource situation；SA module is allocated the code word in parallel organization CODEC according to the output of VA module, and chooses the data in FIFO buffer by MUX data selector, is transmitted to parallel organization CODEC module；The data that the output of parallel organization CODEC module is chosen.Present invention reduces the complexities of design, reduce area and power consumption, and the performance of network can be improved in any topological structure network.
Description
Technical field
The present invention relates to network-on-chip fields, more particularly in extensive network-on-chip, the optimization design of routing node,
And application in engineering practice.
Background technique
In recent years, as the complexity of system on chip is higher and higher, it is based on the mutual connection of NoC (Network on Chip)
Structure due to that can keep good communication performance in complicated system on chip, and is increasingly becoming system on chip interconnection structure
Research hotspot.Nowadays, NoC technology has been widely used in multiprocessor systems on chips.But it is requested simultaneously in multi-user same
In the case where one channel, easily there is congestion in data exchange, and NoC communication performance is caused to decline rapidly.
To solve the above-mentioned problems, researcher introduces CDMA (Code Division Multiple Access) technology
Into network-on-chip, but there are following two disadvantages by existing serial CDMA NoC:
(1) transmission delay of CODEC (Coder-DECoder) and power consumption are high: in CODEC, each node is being transmitted
When data, data are encoded using one in one group of orthogonal code, it is therefore desirable to which p clock cycle could complete to encode
(wherein p is the length of orthogonal code code word, related with the number of nodes of CODEC).When number of nodes increases, the orthogonal code length that needs
Increase, the transmission delay of each jump will increase therewith.The power consumption of CODEC and the logical complexity of circuit are related, traditional
In CODEC, coded portion needs to guarantee the bit synchronous module and coding codeword and counter module of data orthogonality.Solution
Code part needs higher accumulator module of complexity etc., and the power consumption that these factors have resulted in CODEC is higher.
(2) scalability of routing node is poor: since transmission delay is larger in CODEC for data, the road based on above-mentioned CODEC
By node, it is also therefore larger that data in each routing node jump required delay, just because of this, present CDMA NoC mono-
As using required hop count between resource node less Star, Ring and the extension topological structure based on the two, but these are opened up
It flutters structure and does not have good scalability, is i.e. CDMA routing node scalability is poor.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of CDMA routing node based on parallel organization CODEC, tools
There is the features such as transmission delay is low, area small power consumption, scalability is high.
The technical scheme to solve the above technical problems is that a kind of CDMA routing based on parallel organization CODEC
Node, including Port module, RC module, VA module, SA module and parallel organization CODEC module,
The Port module, including 4 FIFO buffers and a MUX data selector, each FIFO buffer
For receiving the data packet of the corresponding Port module output of upper level routing node, and the destination address for including by packet header
Information is transferred to RC mould, and the MUX data selector chooses corresponding FIFO buffer according to the control signal that SA module generates
In data packet, and the data packet of selection is transmitted to parallel organization CODEC module；
The RC module, the destination address information for including according to packet header complete router-level topology, and export biography
It is defeated to request to VA module；
The VA module is used for according to transmission request and current resource situation, to the road junior CDMA being connected with the same level
It is allocated by node storage space, and distribution signal is transferred to SA module；
The SA module, the distribution signal control parallel organization CODEC module for being exported according to VA module is to its code word
It is allocated, and outputs control signals to MUX data selector；
The parallel organization CODEC module, for exporting the data packet of MUX data selector selection.
The beneficial effects of the present invention are: reducing area and power consumption present invention reduces the complexity of design, arbitrarily opening up
The performance that network can be improved is flutterred in structural network.
Based on the above technical solution, the present invention can also be improved as follows.
Further, the parallel organization CODEC module includes 4 parallel decoders and decoding code table module；
The decoding code table module is used to receive the control signal of SA module transmission, and according to control signal to parallel organization
Code word in CODEC module is allocated；
4 parallel decoders are used to receive the data packet of MUX data selector transmission, and according to decoding code table module
The code word of distribution is decoded data；Each parallel decoder includes 4 parallel decoders, and each decoder is used for
It receives the code word of decoding code table module assignment and data is decoded as parallel organization CODEC module according to the code word of distribution
Output；Each decoder by n parallel and Men Zucheng, n be data packet slice data bit width.
Using the parallel organization CODEC module of above-mentioned further scheme having the beneficial effect that using Unique physical design, greatly
The transmission delay of data is reduced greatly, to improve the performance of network-on-chip, while reducing hardware spending.
Further, the parallel organization CODEC module is the CODEC module based on one-hot encoding.
The coding used using the parallel organization CODEC module for having the beneficial effect that this programme of above-mentioned further scheme
With decoding code word be one-hot encoding, therefore with ' 0 ' be connected can be optimised with door, therefore, greatly reduce the biography of data
Defeated delay.
Further, the VA module uses one instance arbitration mode comprising 5 independent Arbiter modules are used for basis
The transmission request and current resource situation that RC module generates are completed the arbitration to junior CDMA routing node memory space and are distributed.
Using the basis of the special construction design for having the beneficial effect that Port module in the present case of above-mentioned further scheme
On, the VA module with specific structure that design matches with Port module, the VA module need to only use one instance arbitration, compared to
The two instance arbitration mode of existing VA module, can greatly reduce design complexities and computing overhead.
Further, the SA module uses one instance arbitration mode, including 5 independent Arbiter modules, for according to VA
The transmission request that the output of module and RC module generate is arbitrated, and according to arbitration result to parallel organization CODEC module
In code word be allocated, and output control signals to MUX data selector.
It is designed using the structure due to the SA module of this case that has the beneficial effect that of above-mentioned further scheme, only need
Design complexities and operation can be greatly reduced compared to the two instance arbitration mode of existing SA module using one instance arbitration mode
Expense.
Detailed description of the invention
Fig. 1 is the CDMA routing node schematic diagram based on parallel organization CODEC；
Fig. 2 is parallel structure CODEC schematic diagram；
Fig. 3 is VA modular structure schematic diagram；
Fig. 4 is SA modular structure schematic diagram；
Fig. 5 is two CDMA routing node annexation figures；
Fig. 6 is that the average packet delay under Ring type topology compares；
Fig. 7 is that the average packet delay under Star type topology compares；
Fig. 8 is that the average packet delay under Mesh type topology compares.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
The present invention provides a kind of CDMA network-on-chip routing node based on parallel organization CODEC, it is therefore intended that solve
Data jump delay height, the problem that power consumption area is big and scalability is bad in traditional CDMA network-on-chip routing node.
As shown in Figure 1, the routing node includes Port module, RC (Route-Compute) module, VA (Virtual-
Channel-Allocation) module, the CODEC module of SA (Switch-Allocation) module and parallel organization.Port
Module stores data packet, and header packet information (Head_Flit) is transmitted to RC module, each FIFO is slow in Port module
Storage (First-In-First-Out) corresponds to each input port of upper level routing node, example Port_W as shown in figure 1
In VC_L, which can only receive what the port Port_L in higher level's routing node adjacent with the routing node exported
Data.Other ports and FIFO buffer can with and so on, this design method, can effectively reduce data congestion and
The design complexities of VA module and SA module.
Fig. 5 is two CDMA routing node annexation figures, and the connection further illustrated between CDMA routing node is closed
System, as can be seen from the figure Node1 is the adjacent routing node of Node2, W (the as VC_ in the port Port_W in Node2
W the data for transmitting to come in Port_W in Node1) are only received；L (as VC_L) in the port Port_W in Node2 is only received
The data come are transmitted in Node1 in Port_L；MUX data selector in Port module, according to the secondary of VA module and SA module
Cut out the data in result selection reading FIFO buffer；RC module is completed according to the header packet information of data packet in FIFO buffer
Router-level topology, and output transmission request, to VA module and SA module, the routing algorithm of RC module can select according to the actual situation
Suitable routing algorithm.VA module and SA module make arbitration to transmission request, and VA module is according to transmission request and Current resource
Situation completes the distribution to junior's memory space, and SA module is then according to the output of VA module to the code word in parallel organization CODEC
It is allocated, CODEC module is used for transmission the data in the FIFO buffer of selection.
Based on the CDMA routing node of parallel organization CODEC in the complexity for reducing design, the same of area and power consumption is reduced
When, the performance of network can be improved in any topological structure network.
As shown in Fig. 2, parallel organization CODEC module, is improved to obtain, for exporting by serial CODECA modular structure
The data packet that MUX data selector is chosen comprising 4 parallel decoders and decoding code table module；Parallel organization CODEC module
The CODEC module based on one-hot encoding, the coding used and decoding code word for one-hot encoding, therefore with ' 0 ' be connected with door
Can be optimised, therefore, greatly reduce the transmission delay of data.
Decoding code table module is used to receive the control signal of SA module transmission, and according to control signal to parallel organization
Code word in CODEC module is allocated；
Each parallel decoder is used to receive the data packet of MUX data selector transmission, and according to decoding code table module point
The code word matched is decoded data, since in practical NoC application, the data packet that some direction sends over will not be by former road
Diameter returns, therefore the input of each parallel decoder is right to remove itself in 5 data input of parallel organization CODEC module
Answer other outer 4 data inputs, wherein each parallel decoder includes 4 parallel decoders, and each decoder is for connecing
It receives the code word of decoding code table module assignment and data is decoded as parallel organization CODEC module according to the code word of distribution
Output；Also, each decoder by n parallel and Men Zucheng, n are data bit width that data packet is sliced.
Port module includes 4 FIFO buffers and a MUX data selector, and each FIFO buffer is for receiving
The data packet of the corresponding Port module output of level-one routing node, and the destination address information that packet header includes is transferred to
RC module；The control signal that MUX data selector is generated according to SA module chooses the data packet in corresponding FIFO buffer, and
The data packet of selection is transmitted to parallel organization CODEC module；
RC module, the destination address information for including according to packet header complete router-level topology, and export transmission and ask
It asks to VA module；
As shown in figure 3, VA module uses one instance arbitration mode comprising 5 independent Arbiter modules are used for basis
The transmission request and current resource situation that RC module generates are completed the arbitration to junior CDMA routing node memory space and are distributed.
As shown in figure 4, SA module uses one instance arbitration mode, including 5 independent Arbiter modules, for according to VA
The transmission request that the output of module and RC module generate is arbitrated, and according to arbitration result to parallel organization CODEC module
In code word be allocated, and output control signals to MUX data selector.
The routing node of design is carried out comprehensive analysis under Synopsys DC software, obtained by content according to the present invention
The power consumption and area of each functional module of routing node.The technology library that the experiment is selected is tcbn40lpbwptc, Model of wire load
For TSMC32K_Lowk_Aggressive, clock frequency 2GHz, Tables 1 and 2 is the power consumption test of CDMA routing node respectively
As a result with area test result.
The power consumption of table 1 and conventional serial CDMA routing node compares
The area of table 2 and conventional serial CDMA routing node compares
By upper table it can be concluded that power consumption and area based on CDMA routing node of the invention reduce 26.7% He respectively
14.5%, therefore have certain promotion in power consumption and area index.
Content according to the present invention carries out network performance emulation to the Novel CDMA routing node of design, and experiment exists respectively
It is carried out in Ring, Star and Mesh type structure, each node sends 10000 data packets, and the destination address of each data packet produces
Raw obey is uniformly distributed, and the time that data packet generates obeys Poisson distribution.
Fig. 6, Fig. 7 and Fig. 8 are the simulation result under 6 node R ing, 8 node Star and 4 × 4-Mesh topologys respectively, from
It can be obtained in figure, in common CDMA NoC topology, it is right that the packet average delay based on CDMA NoC of the invention reaches thresholding institute
The injection rate answered is high compared with conventional serial method, i.e., network has preferable anti-congestion performance.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (5)
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104169903A (en) * | 2012-03-28 | 2014-11-26 | 中兴通讯股份有限公司 | Method and system for implementing synchronous parallel transmission over multiple channels |
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| US8189578B2 (en) * | 2009-06-30 | 2012-05-29 | Oracle America, Inc. | Simple fairness protocols for daisy chain interconnects |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104169903A (en) * | 2012-03-28 | 2014-11-26 | 中兴通讯股份有限公司 | Method and system for implementing synchronous parallel transmission over multiple channels |
Non-Patent Citations (2)
| Title |
|---|
| 《A New CDMA Encoding/Decoding Method for on-Chip Communication Network》;王坚;《 IEEE Transactions on Very Large Scale Integration (VLSI) Systems 》;20150917;第2016卷(第24期);全文 * |
| 《片上网络通信性能分析建模与缓存分配优化算法》;王坚;《电子与信息学报》;20090515;第2009卷(第31期);全文 * |
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