CN106603067A - Orthogonal input divide-by-2 frequency divider - Google Patents

Abstract

The present invention is applicable to the field of frequency dividers, and provides an orthogonal input two-frequency divider, including: a filter circuit that inputs an external power supply and outputs after filtering; a tuning circuit connected to the output end of the filter circuit; and an output terminal of the filter circuit The end is connected to the mixing stage of the output terminal OUTI, the output terminal OUTIB, the output terminal OUTQB and the output terminal OUTQ of the quadrature input two frequency divider; respectively with the input terminal INI and the input terminal of the quadrature input two frequency divider INIB, the input terminal INQ and the input terminal INQB are connected to input a voltage signal, and the voltage signal is converted into a current signal and then output to the transconductance stage of the common source terminal of the mixing stage; connected to the common source terminal of the transconductance stage, by injecting an external The current source makes the transconductance stage form a current source bias circuit of a variable current source. The invention injects an external current source into the current source bias circuit to make the transconductance stage constitute a variable current source to increase the current of the transconductance stage, which can effectively improve the conversion gain, linearity and working efficiency of the quadrature input frequency divider Frequency Range.

Description

A Quadrature Input Two-Frequency Divider

technical field

The invention belongs to the field of frequency dividers, in particular to a quadrature input two frequency divider.

Background technique

Frequency dividers are widely used in the communication field, including quadrature input frequency dividers, phase shift based frequency dividers, etc.

However, the disadvantage of the existing quadrature input frequency divider is that its operating frequency range is limited, and it cannot be well applied to devices with higher requirements on the operating frequency range.

Contents of the invention

The object of the present invention is to provide a quadrature input frequency divider by two, which aims to solve the disadvantage of the existing quadrature input frequency divider that its operating frequency range is limited, and it cannot be well suited for applications that require a higher operating frequency range. Device problem.

The present invention is achieved like this, a kind of quadrature input frequency divider by two, comprising:

A filter circuit that inputs an external power supply and outputs it after filtering;

a tuning circuit connected to the output of the filter circuit;

A mixing stage that is commonly connected to the first output terminal OUTI, the second output terminal OUTIB, the third output terminal OUTQB, and the fourth output terminal OUTQ of the quadrature input two-frequency divider with the output terminal of the filter circuit;

Connect to the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input frequency divider respectively to input voltage signals, and convert the voltage signals into currents After the signal is output to the transconductance stage of the common source end of the mixing stage;

It is connected with the common source terminal of the transconductance stage, and injects an external current source to make the transconductance stage constitute a current source bias circuit of a variable current source.

Preferably, the injection ratio of the external current source injected by the current source bias circuit is adjustable, and the injection ratio of the external current source is proportional to the size of the variable current source formed by the transconductance stage; when increasing the When the injection ratio of the external current source is increased, the conversion gain of the transconductance stage increases, the overdrive voltage of the mixing stage decreases, and the frequency range of the quadrature input two-frequency divider increases.

Preferably, the filter circuit includes a first inductance L1 and a second inductance L2, and the center taps of the first inductance L1 and the second inductance L2 are commonly connected to form an input end of the filter circuit to input an external power supply; the first inductance L1 The two output terminals of the first inductance L1 and the two output terminals of the second inductance L2 are the output terminals of the filter circuit, wherein the two output terminals of the first inductance L1 are respectively connected with the first The output terminal OUTI is connected to the second output terminal OUTIB in a one-to-one correspondence, and the two output terminals of the second inductor L2 are respectively connected to the third output terminal OUTQB and the fourth output terminal OUTQ of the quadrature input two-frequency divider in a one-to-one correspondence. .

Preferably, the tuning circuit includes a load unit connected to the output end of the filter circuit and a switch unit connected between the load unit and ground.

Preferably, the load unit includes first to eighth capacitors C1-C8 used as loads of the filter circuit, and the switch unit includes first to eighth switches K1-K8;

Wherein, one end of the first capacitor C1 and the second capacitor C2 and the output end of the filter circuit are commonly connected to the first output end OUTI of the quadrature input two-frequency divider;

One terminal of the third capacitor C3 and the fourth capacitor C4 and the output terminal of the filter circuit are commonly connected to the second output terminal OUTIB of the quadrature input frequency divider by two;

One terminal of the fifth capacitor C5 and the sixth capacitor C6 and the output terminal of the filter circuit are connected to the third output terminal OUTQB of the quadrature input frequency divider by two;

One terminal of the seventh capacitor C7 and the eighth capacitor C8 and the output terminal of the filter circuit are commonly connected to the fourth output terminal OUTQ of the quadrature input two-frequency divider;

The other ends of the first to eighth capacitors C1 to C8 are grounded through the first to eighth switches K1 to K8 respectively.

Preferably, the mixing stage includes eleventh to twenty-sixth NMOS transistors M11-M26, and the transconductance stage includes seventh to tenth PMOS transistors M7-M10 and third to sixth NMOS transistors M3-M6 ;

Among them, the gates of the eleventh NMOS transistor M11, the fourteenth NMOS transistor M14, the twenty-third NMOS transistor M23, the twenty-sixth NMOS transistor M26, the eleventh NMOS transistor M11, the thirteenth NMOS transistor M13, the The drains of the nineteenth NMOS transistor M19 and the twenty-first NMOS transistor M21 are both connected to the first output terminal OUTI of the quadrature input two-frequency divider;

The gates of the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the twenty-fourth NMOS transistor M24, the twenty-fifth NMOS transistor M25 and the gates of the twelfth NMOS transistor M12, the fourteenth NMOS transistor M14, the twenty The drains of the NMOS transistor M20 and the twenty-second NMOS transistor M22 are both connected to the second output terminal OUTIB of the quadrature input two-frequency divider;

Gates of the sixteenth NMOS transistor M16, the seventeenth NMOS transistor M17, the twentieth NMOS transistor M20, the twenty-first NMOS transistor M21, the fifteenth NMOS transistor M15, the seventeenth NMOS transistor M17, the twenty-fourth The drains of the NMOS transistor M24 and the twenty-sixth NMOS transistor M26 are both connected to the third output terminal OUTQB of the quadrature input two-frequency divider;

The gates of the fifteenth NMOS transistor M15, the eighteenth NMOS transistor M18, the nineteenth NMOS transistor M19, the twenty-second NMOS transistor M22, the sixteenth NMOS transistor M16, the eighteenth NMOS transistor M18, the twenty-third The drains of the NMOS transistor M23 and the twenty-fifth NMOS transistor M25 are both connected to the fourth output terminal OUTQ of the quadrature input two frequency divider;

The sources of the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are connected to the drain of the seventh PMOS transistor M7;

The sources of the thirteenth NMOS transistor M13 and the fourteenth NMOS transistor M14 are commonly connected to the source of the eighth PMOS transistor M8 and the drain of the fourth NMOS transistor M4;

The sources of the fifteenth NMOS transistor M15 and the sixteenth NMOS transistor M16 are connected to the source of the seventh PMOS transistor M7 and the drain of the third NMOS transistor M3;

The sources of the seventeenth NMOS transistor M17 and the eighteenth NMOS transistor M18 are connected to the drain of the eighth PMOS transistor M8;

The sources of the nineteenth NMOS transistor M19 and the twentieth NMOS transistor M20 are connected to the drain of the ninth PMOS transistor M9;

The sources of the twenty-first NMOS transistor M21 and the twenty-second NMOS transistor M22 are connected to the source of the tenth PMOS transistor M10 and the drain of the sixth NMOS transistor M6;

The sources of the twenty-third NMOS transistor M23 and the twenty-fourth NMOS transistor M24 are connected to the source of the ninth PMOS transistor M9 and the drain of the fifth NMOS transistor M5;

The sources of the twenty-fifth NMOS transistor M25 and the twenty-sixth NMOS transistor M26 are connected to the source of the tenth PMOS transistor M10;

The gates of the seventh to tenth PMOS transistors M7-M10 are respectively connected to the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input two-frequency divider. Corresponding connection to input voltage signal;

The sources of the third to sixth NMOS transistors M3 to M6 are commonly connected to form the common source end of the transconductance stage, and the gates of the third to sixth NMOS transistors M3 to M6 are respectively connected to the quadrature input two frequency divider The first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB are connected in one-to-one correspondence to input voltage signals.

Preferably, the transconductance stage further includes ninth to sixteenth DC blocking capacitors C9-C16 and first to eighth bias resistors R1-R8;

Wherein, one end of the first DC-blocking capacitor C9 and the thirteenth DC-blocking capacitor C13 are connected to the first signal input terminal INI of the quadrature input two frequency divider, and the tenth DC-blocking capacitor C10 and the fourteenth DC-blocking capacitor One end of the capacitor C14 is commonly connected to the second signal input end INIB of the quadrature input two frequency divider, and one end of the eleventh DC blocking capacitor C11 and the fifteenth DC blocking capacitor C15 are commonly connected to the quadrature input two The third signal input terminal INQ of the frequency divider, one end of the twelfth DC blocking capacitor C12 and the sixteenth DC blocking capacitor C16 are jointly connected to the fourth signal input terminal INQB of the quadrature input two frequency divider;

The other ends of the ninth to the twelfth DC blocking capacitors C9-C12 are connected to the gates of the third to the sixth M3-M6 in one-to-one correspondence with the ends of the first to the fourth bias resistors R1-R4 respectively. The other ends of the third to sixteenth DC blocking capacitors C13-C16 are respectively connected to the gates of the seventh to tenth NMOS transistors M7-M10 in one-to-one correspondence with one end of the fifth to eighth bias resistors R5-R8;

The other ends of the first to fourth bias resistors R1-R4 are connected in common, and the other ends of the fifth to eighth bias resistors R5-R8 are connected in common;

The input signals of the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input frequency divider pass through the ninth to the twelfth DC blocking capacitors C9~ C12 is DC-blocked and biased by the first to eighth bias resistors R1 to R8, and then transmitted to the gates of the seventh to tenth PMOS transistors M7 to M10 and the third to sixth NMOS transistors M3 to M6 respectively.

Preferably, the current source bias circuit includes a first NMOS transistor M1 and a second NMOS transistor M2;

Wherein, the drain of the first NMOS transistor M1 is injected into the current source;

The gate and drain of the first NMOS transistor M1 are commonly connected with the gate of the second NOMS transistor M2 to form a current mirror;

The source of the first NMOS transistor M1 and the source of the second NOMS transistor M2 are commonly connected to the ground;

The drain of the second NMOS transistor M2 is connected to the common source end of the transconductance stage.

Compared with the prior art, the present invention has the beneficial effects of:

By injecting an external current source into the current source bias circuit, the transconductance stage forms a variable current source to increase the current of the transconductance stage, which can effectively improve the conversion gain and linearity of the quadrature input two-frequency divider, and realize the extended positive The purpose of crossing the operating frequency range of the input frequency divider;

By increasing the injection ratio of the external current source, the current of the variable current source composed of the transconductance stage increases, which can reduce the overdrive voltage of the switching tube of the mixing stage, increase the switch opening speed of the mixing stage, and improve the transconductance stage. conversion gain.

Description of drawings

FIG. 1 is a basic structural block diagram of an quadrature input two frequency divider provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a circuit structure of a quadrature input frequency divider by two provided by an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Fig. 1 is a basic structural block diagram of a quadrature input frequency divider by two provided by an embodiment of the present invention.

As shown in FIG. 1 , the quadrature input frequency divider by two provided in this embodiment includes a filter circuit 10 , a tuning circuit 20 , a mixing stage 30 , a transconductance stage 40 and a current source bias circuit 50 .

The filtering circuit 10 is used to input an external power supply and output it after filtering.

In a specific application, the filter circuit may use a filter capacitor or an inductance device.

The tuning circuit 20 is connected to the output terminal of the filter circuit 10 and is used for adjusting the frequency of the input signal.

In a preferred embodiment, the tuning circuit 20 includes a load unit connected to the output terminal of the filter circuit 10 and a switch unit connected between the load unit and ground.

In another preferred embodiment, the tuning circuit can also be selected from an LC oscillating circuit composed of a capacitor and an inductance, an RLC oscillating circuit composed of a capacitor, a resistor and an inductance, or an SC switched capacitor circuit composed of a capacitor and a switch. When switching capacitor circuits, the switches in the circuit can be either mechanical switches or electronic switches.

The mixing stage 30 is connected with the output end of the filter circuit 10 to the first output end OUTI, the second output end OUTIB, the third output end OUTQB and the fourth output end OUTQ of the quadrature input two frequency divider, for It is output after frequency division of the input signal.

The transconductance stage 40 is connected to the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input frequency divider to input a voltage signal, and convert the voltage signal After being a current signal, it is output to the common source end of the mixing stage 30 .

The current source bias circuit 50 is connected to the common source terminal of the transconductance stage 40, and makes the transconductance stage 40 constitute a variable current source by injecting an external current source.

The injection ratio of the external current source injected by the current source bias circuit is adjustable, and the injection ratio of the external current source is proportional to the size of the variable current source formed by the transconductance stage; when the external current source is increased When the injection ratio is higher, the conversion gain of the transconductance stage increases, the overdrive voltage of the mixing stage decreases, and the frequency range of the quadrature input two-frequency divider increases.

By increasing the injection ratio of the external current source, the conversion gain and linearity of the quadrature input frequency divider by two can be effectively improved, so as to realize the purpose of expanding the working frequency range of the quadrature input frequency divider.

FIG. 2 is a schematic diagram of a circuit structure of a quadrature input frequency divider by two provided by an embodiment of the present invention.

As shown in Figure 2, the circuit structure of the quadrature input two frequency divider provided in this embodiment is specifically as follows:

The filter circuit 10 includes a first inductance L1 and a second inductance L2, and the center taps of the first inductance L1 and the second inductance L2 are connected together to form an input end of the filter circuit to input an external power supply; two outputs of the first inductance L1 terminal and the two output terminals of the second inductance L2 constitute the output terminals of the filter circuit, which are respectively connected to the first output terminal OUTI and the second output terminal OUTIB of the quadrature input frequency divider in one-to-one correspondence, and the second The two output terminals of the inductor L2 are connected to the third output terminal OUTQB and the fourth output terminal OUTQ of the quadrature input frequency divider by two respectively in one-to-one correspondence.

In a specific application, the first inductance L1 and the second inductance L2 can be selected with appropriate inductances according to actual needs.

In this embodiment, the tuning circuit 20 includes a load unit connected to the output terminal of the filter circuit 10 and a switch unit connected between the load unit and the ground.

In a specific application, the switch unit can be an electronic switch tube or a common two-interface switch.

In this embodiment, the load unit includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor used as a load of the filter circuit 10. C7 and the eighth capacitor C8, the switch unit includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7 and an eighth switch K8;

Wherein, one end of the first capacitor C1 and the second capacitor C2 and the output end of the filter circuit are commonly connected to the first output end OUTI of the quadrature input two-frequency divider;

One terminal of the third capacitor C3 and the fourth capacitor C4 and the output terminal of the filter circuit are commonly connected to the second output terminal OUTIB of the quadrature input frequency divider by two;

One terminal of the fifth capacitor C5 and the sixth capacitor C6 and the output terminal of the filter circuit are connected to the third output terminal OUTQB of the quadrature input frequency divider by two;

One terminal of the seventh capacitor C7 and the eighth capacitor C8 and the output terminal of the filter circuit are commonly connected to the fourth output terminal OUTQ of the quadrature input two-frequency divider;

The other ends of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 respectively pass through the first switch K1 and the second switch K1. The second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7 and the eighth switch K8 are grounded.

The switched capacitor filter circuit composed of switched capacitors has a tuning function.

Specifically, the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7 and the eighth switch K8 may be mechanical switches or Electronic switch, the capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 can be tuned according to the specific The scope needs to be selected.

The frequency mixing stage 30 includes eleventh to twenty-sixth NMOS transistors M11-M26, and the transconductance stage 40 includes seventh to tenth PMOS transistors M7-M10 and third to sixth NMOS transistors M3-M6; wherein, the tenth Gates of an NMOS transistor M11, the fourteenth NMOS transistor M14, the twenty-third NMOS transistor M23, the twenty-sixth NMOS transistor M26, the eleventh NMOS transistor M11, the thirteenth NMOS transistor M13, and the nineteenth NMOS transistor The drains of M19 and the twenty-first NMOS transistor M21 are both connected to the first output terminal OUTI of the quadrature input two frequency divider;

The gates of the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the twenty-fourth NMOS transistor M24, the twenty-fifth NMOS transistor M25 and the gates of the twelfth NMOS transistor M12, the fourteenth NMOS transistor M14, the twenty The drains of the NMOS transistor M20 and the twenty-second NMOS transistor M22 are both connected to the second output terminal OUTIB of the quadrature input two-frequency divider;

Gates of the sixteenth NMOS transistor M16, the seventeenth NMOS transistor M17, the twentieth NMOS transistor M20, the twenty-first NMOS transistor M21, the fifteenth NMOS transistor M15, the seventeenth NMOS transistor M17, the twenty-fourth The drains of the NMOS transistor M24 and the twenty-sixth NMOS transistor M26 are both connected to the third output terminal OUTQB of the quadrature input two-frequency divider;

The gates of the fifteenth NMOS transistor M15, the eighteenth NMOS transistor M18, the nineteenth NMOS transistor M19, the twenty-second NMOS transistor M22, the sixteenth NMOS transistor M16, the eighteenth NMOS transistor M18, the twenty-third The drains of the NMOS transistor M23 and the twenty-fifth NMOS transistor M25 are both connected to the fourth output terminal OUTQ of the quadrature input two frequency divider;

The sources of the eleventh NMOS transistor M11 and the twelfth NMOS transistor M12 are connected to the drain of the seventh PMOS transistor M7;

The sources of the thirteenth NMOS transistor M13 and the fourteenth NMOS transistor M14 are commonly connected to the source of the eighth PMOS transistor M8 and the drain of the fourth NMOS transistor M4;

The sources of the fifteenth NMOS transistor M15 and the sixteenth NMOS transistor M16 are connected to the source of the seventh PMOS transistor M7 and the drain of the third NMOS transistor M3;

The sources of the seventeenth NMOS transistor M17 and the eighteenth NMOS transistor M18 are connected to the drain of the eighth PMOS transistor M8;

The sources of the nineteenth NMOS transistor M19 and the twentieth NMOS transistor M20 are connected to the drain of the ninth PMOS transistor M9;

The sources of the twenty-first NMOS transistor M21 and the twenty-second NMOS transistor M22 are connected to the source of the tenth PMOS transistor M10 and the drain of the sixth NMOS transistor M6;

The sources of the twenty-third NMOS transistor M23 and the twenty-fourth NMOS transistor M24 are connected to the source of the ninth PMOS transistor M9 and the drain of the fifth NMOS transistor M5;

The sources of the twenty-fifth NMOS transistor M25 and the twenty-sixth NMOS transistor M26 are connected to the source of the tenth PMOS transistor M10;

The gates of the seventh to tenth PMOS transistors M7-M10 are respectively connected to the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input two-frequency divider. Corresponding connection to input voltage signal;

The sources of the third to sixth NMOS transistors M3 to M6 are commonly connected to form the common source end of the transconductance stage, and the gates of the third to sixth NMOS transistors M3 to M6 are respectively connected to the quadrature input two frequency divider The first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB are connected in one-to-one correspondence to input voltage signals.

The transconductance stage 40 also includes ninth to sixteenth DC blocking capacitors C9-C16 and first to eighth bias resistors R1-R8;

Wherein, one end of the first DC-blocking capacitor C9 and the thirteenth DC-blocking capacitor C13 are connected to the first signal input terminal INI of the quadrature input two frequency divider, and the tenth DC-blocking capacitor C10 and the fourteenth DC-blocking capacitor One end of the capacitor C14 is commonly connected to the second signal input end INIB of the quadrature input two frequency divider, and one end of the eleventh DC blocking capacitor C11 and the fifteenth DC blocking capacitor C15 are commonly connected to the quadrature input two The third signal input terminal INQ of the frequency divider, one end of the twelfth DC blocking capacitor C12 and the sixteenth DC blocking capacitor C16 are jointly connected to the fourth signal input terminal INQB of the quadrature input two frequency divider;

The other ends of the ninth to the twelfth DC blocking capacitors C9-C12 are connected to the gates of the third to the sixth M3-M6 in one-to-one correspondence with the ends of the first to the fourth bias resistors R1-R4 respectively. The other ends of the third to sixteenth DC blocking capacitors C13-C16 are respectively connected to the gates of the seventh to tenth NMOS transistors M7-M10 in one-to-one correspondence with one end of the fifth to eighth bias resistors R5-R8;

The other ends of the first to fourth bias resistors R1-R4 are connected in common, and the other ends of the fifth to eighth bias resistors R5-R8 are connected in common;

The input signals of the first input terminal INI, the second input terminal INIB, the third input terminal INQ and the fourth input terminal INQB of the quadrature input frequency divider pass through the ninth to the twelfth DC blocking capacitors C9~ C12 is DC-blocked and biased by the first to eighth bias resistors R1 to R8, and then transmitted to the gates of the seventh to tenth PMOS transistors M7 to M10 and the third to sixth NMOS transistors M3 to M6 respectively.

The current source bias circuit 50 includes a first NMOS transistor M1 and a second NMOS transistor M2;

Wherein, the drain of the first NMOS transistor M1 is injected into the current source;

The gate and drain of the first NMOS transistor M1 are commonly connected with the gate of the second NOMS transistor M2 to form a current mirror;

The source of the first NMOS transistor M1 and the source of the second NOMS transistor M2 are commonly connected to the ground;

The drain of the second NMOS transistor M2 is connected to the common source end of the transconductance stage.

The current source injected by the current source bias circuit is an active current source.

By injecting the current source into the drain of the NMOS tube of the current source bias circuit, the NMOS tube of the transconductance stage can be made into a variable current source, which can improve the conversion gain and linearity of the quadrature input two-frequency divider; by changing the current The injection ratio of the current source of the source bias circuit can change the frequency range of the quadrature two-frequency divider; increasing the injection ratio of the current source can reduce the overdrive voltage of the switching tube of the mixing stage and improve the switch opening of the mixing stage Increase the conversion gain of the transconductance stage, thereby increasing the frequency range of the quadrature two-frequency divider and increasing its maximum phase shift.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (8)

1. a kind of orthogonal input two-divider, it is characterised in that the orthogonal input two-divider includes：

The filter circuit for being input into external power source and exporting after being filtered；

The tuning circuit being connected with the outfan of the filter circuit；

With the first outfan OUTI, the second output that the outfan of the filter circuit is connected to altogether the orthogonal input two-divider End OUTIB, the mixer stage of the 3rd outfan OUTQB and the 4th outfan OUTQ；

Respectively with the orthogonal input first input end INI of two-divider, the second input INIB, the 3rd input INQ and 4th input INQB connects with input voltage signal, and the voltage signal is changed into after current signal exports to described mixed The transconductance stage at the common source end of frequency level；

It is connected with the common source end of the transconductance stage, makes the transconductance stage constitute the electricity of variable current source by injecting external current source Stream source biasing circuit.

2. orthogonal input two-divider as claimed in claim 1, it is characterised in that what the current source bias circuit was injected The injection of external current source is than adjustable, the variable current source size injected than constituting with the transconductance stage of the external current source It is directly proportional；When improve the injection of the external current source than when, the conversion gain increase of the transconductance stage, the mistake of the mixer stage Drive voltage reduction, the frequency range increase of the orthogonal input two-divider.

3. orthogonal input two-divider as claimed in claim 1, it is characterised in that the filter circuit includes the first inductance L1 The input for constituting the filter circuit is connect altogether with the centre cap of the second inductance L2, the first inductance L1 and the second inductance L2, with Input external power source；Two outfans of the first inductance L1 and two outfans of the second inductance L2 are the filter circuit Outfan, wherein, two outfans of the first inductance L1 respectively with the first outfan OUTI of the orthogonal input two-divider Connect one to one with the second outfan OUTIB, two outfans of the second inductance L2 respectively with the orthogonal input two divided-frequency 3rd outfan OUTQB of device and the 4th outfan OUTQ connect one to one.

4. orthogonal input two-divider as claimed in claim 1, it is characterised in that the tuning circuit includes and the filtering The load unit of the outfan connection of circuit and the switch element being connected between the load unit and ground.

5. orthogonal input two-divider as claimed in claim 4, it is characterised in that the load unit is included as the filter The first to the 8th electric capacity C1～C8 that the load of wave circuit is used, the switch element includes first to the 8th switch K1～K8；

Wherein, one end of the first electric capacity C1 and the second electric capacity C2 is connected to altogether the orthogonal input with the outfan of the filter circuit First outfan OUTI of two-divider；

3rd electric capacity C3 and one end of the 4th electric capacity C4 are connected to altogether orthogonal two points of the input with the outfan of the filter circuit Second outfan OUTIB of frequency device；

5th electric capacity C5 and one end of the 6th electric capacity C6 are connected to altogether orthogonal two points of the input with the outfan of the filter circuit 3rd outfan OUTQB of frequency device；

7th electric capacity C7 and one end of the 8th electric capacity C8 are connected to altogether orthogonal two points of the input with the outfan of the filter circuit 4th outfan OUTQ of frequency device；

The other end difference switch K1～K8 ground connection of Jing first to the 8th of the first to the 8th electric capacity C1～C8.

6. orthogonal input two-divider as claimed in claim 1, it is characterised in that the mixer stage includes the tenth one to the second 16 NMOS tubes M11～M26, the transconductance stage includes the 7th to the tenth PMOS M7～M10 and the 3rd to the 6th NMOS tube M3 ～M6；

Wherein, the 11st NMOS tube M11, the 14th NMOS tube M14, the 23rd NMOS tube M23, the 26th NMOS tube M26 Grid and the 11st NMOS tube M11, the 13rd NMOS tube M13, the 19th NMOS tube M19, the leakage of the 21st NMOS tube M21 Extremely connect with the first outfan OUTI of the orthogonal input two-divider；

12nd NMOS tube M12, the 13rd NMOS tube M13, the 24th NMOS tube M24, the grid of the 25th NMOS tube M25 With the 12nd NMOS tube M12, the 14th NMOS tube M14, the 20th NMOS tube M20, the 22nd NMOS tube M22 drain electrode with The second outfan OUTIB connections of the orthogonal input two-divider；

16th NMOS tube M16, the 17th NMOS tube M17, the 20th NMOS tube M20, the grid of the 21st NMOS tube M21 and 15th NMOS tube M15, the 17th NMOS tube M17, the 24th NMOS tube M24, the 26th NMOS tube M26 drain electrode with The 3rd outfan OUTQB connections of the orthogonal input two-divider；

15th NMOS tube M15, the 18th NMOS tube M18, the 19th NMOS tube M19, the grid of the 22nd NMOS tube M22 and 16th NMOS tube M16, the 18th NMOS tube M18, the 23rd NMOS tube M23, the 25th NMOS tube M25 drain electrode with The 4th outfan OUTQ connections of the orthogonal input two-divider；

The source electrode of the 11st NMOS tube M11 and the 12nd NMOS tube M12 is connected to altogether the drain electrode of the 7th PMOS M7；

The source electrode of the 13rd NMOS tube M13 and the 14th NMOS tube M14 is connected to altogether the 8th PMOS M8 source electrode and the 4th NMOS tube The drain electrode of M4；

The source electrode of the 15th NMOS tube M15 and the 16th NMOS tube M16 is connected to altogether the 7th PMOS M7 source electrode and the 3rd NMOS tube The drain electrode of M3；

The source electrode of the 17th NMOS tube M17 and the 18th NMOS tube M18 is connected to altogether the drain electrode of the 8th PMOS M8；

The source electrode of the 19th NMOS tube M19 and the 20th NMOS tube M20 is connected to altogether the drain electrode of the 9th PMOS M9；

The source electrode of the 21st NMOS tube M21 and the 22nd NMOS tube M22 is connected to altogether the tenth PMOS M10 source electrode and the 6th The drain electrode of NMOS tube M6；

The source electrode of the 23rd NMOS tube M23 and the 24th NMOS tube M24 is connected to altogether the source electrode and the 5th of the 9th PMOS M9 The drain electrode of NMOS tube M5；

The source electrode of the 25th NMOS tube M25 and the 26th NMOS tube M26 is connected to altogether the source electrode of the tenth PMOS M10；

The grid of the 7th to the tenth PMOS M7～M10 first input end INI respectively with the orthogonal input two-divider, the Two input INIB, the 3rd input INQ and the 4th input INQB connect one to one with input voltage signal；

The source electrode of the 3rd to the 6th NMOS tube M3～M6 connects altogether the common source end for constituting the transconductance stage, the 3rd to the 6th NMOS tube M3 The grid of～M6 respectively with it is described it is orthogonal input two-divider first input end INI, the second input INIB, the 3rd input INQ and the 4th input INQB connect one to one with input voltage signal.

7. orthogonal input two-divider as claimed in claim 6, it is characterised in that the transconductance stage also includes the 9th to the tenth The six capacitance C9～biasing resistor R1 of C16 and first to the 8th～R8；

Wherein, one end of the first capacitance C9 and the 13rd capacitance C13 is connected to altogether the orthogonal input two-divider First signal input part INI, one end of the tenth capacitance C10 and the 14th capacitance C14 is connected to altogether the orthogonal input The secondary signal input INIB of two-divider, one end of the 11st capacitance C11 and the 15th capacitance C15 is connected to altogether The 3rd signal input part INQ, the 12nd capacitance C12 and the 16th capacitance C16 of the orthogonal input two-divider One end be connected to altogether it is described it is orthogonal input two-divider the 4th signal input part INQB；

The other end of the 9th to the 12nd capacitance C9～C12 respectively with one end one of the first to the 4th biasing resistor R1～R4 One correspondence is connected to altogether the 3rd to six M3～M6 grid, the other end difference of the 13rd to the 16th capacitance C13～C16 The grid for being connected to the 7th to the tenth NMOS tube M7～M10 altogether is corresponded with one end of the 5th to the 8th biasing resistor R5～R8；

The other end of the first to the 4th biasing resistor R1～R4 connects altogether, and the other end of the 5th to the 8th biasing resistor R5～R8 is total to Connect；

The orthogonal first input end INI for being input into two-divider, the second input INIB, the 3rd input INQ and the 4th are defeated Enter to hold INQB input signal respectively through the 9th to the 12nd capacitance C9～C12 every straight and by the first to the 8th biasing After resistance R1～R8 biasings, it is respectively transmitted to the 7th to the tenth PMOS M7～M10's and the 3rd to the 6th NMOS tube M3～M6 Grid.

8. orthogonal input two-divider as claimed in claim 1 or 2, it is characterised in that the current source bias circuit includes First NMOS tube M1 and the second NMOS tube M2；

Wherein, the drain electrode injection current source of the first NMOS tube M1；

The grid of the first NMOS tube M1 and drain electrode connect altogether composition current mirror with the grid of the 2nd NOMS pipe M2；

The source electrode of the source electrode of the first NMOS tube M1 and the 2nd NOMS pipe M2 is connected to ground altogether；

The drain electrode of the second NMOS tube M2 connects the common source end of the transconductance stage.