CN106601817A - A GaAs-Based Heterojunction Tunneling Field-Effect Transistor - Google Patents

Abstract

The invention discloses a gallium arsenide-based heterojunction tunneling field effect transistor structure, which comprises: an N-type doped GaAs semiconductor layer; an intrinsic gallium arsenide semiconductor layer; a P-type gallium antimonide semiconductor layer; a drain electrode formed on the N-type doped gallium arsenide semiconductor layer; a source electrode formed on the P-type gallium antimonide semiconductor material; an alumina dielectric layer grown on the intrinsic gallium arsenide semiconductor layer; a gate metal electrode formed on the alumina dielectric layer.

Description

A GaAs-Based Heterojunction Tunneling Field-Effect Transistor

technical field

The invention belongs to the field of microelectronics, and in particular relates to a gallium arsenide-based heterojunction tunneling field effect transistor structure.

Background technique

Modern integrated circuits based on silicon-based CMOS technology continue to improve in terms of integration, power consumption, and device characteristics as the feature size of CMOS devices shrinks. After the CMOS technology node enters 10 nanometers, it faces challenges in both process and physical properties. III-V semiconductor materials are considered to be one of the options to replace silicon as device channel materials due to their high electron mobility characteristics. It has become a current research hotspot and an important direction for technological breakthroughs. On the other hand, the tunneling field effect transistor (TFET) developed by tunneling effect has become an important research direction of memory cell application devices due to its low power consumption and low subthreshold swing. In this context, the tunneling field effect transistor developed by using III-V semiconductor materials instead of silicon can effectively improve the maximum current and switching ratio of the device. It has become an important technical breakthrough direction to improve the performance of tunneling field effect transistor devices.

Contents of the invention

The purpose of the present invention is to provide a GaAs channel field effect transistor structure to provide the maximum saturation current that cannot be achieved by silicon-based TFET devices while maintaining the current switching ratio of the device.

The invention provides a silicon-based heterojunction tunneling field effect transistor structure, which specifically includes:

an n-type doped gallium arsenide semiconductor layer;

a 10 nm thick intrinsic gallium arsenide semiconductor layer;

A p-type gallium antimonide semiconductor layer;

An aluminum oxide dielectric layer grown on the intrinsic gallium arsenide semiconductor layer;

a gate metal electrode formed on the aluminum oxide dielectric layer;

a source electrode formed on the p-type gallium antimonide semiconductor material;

A drain electrode formed on the N-type doped gallium arsenide semiconductor layer.

According to the structure of a silicon-based heterojunction tunneling field effect transistor described in this proposal, it is characterized in that the thickness of the P-type gallium antimonide semiconductor layer is 10 nanometers, and the doping concentration is 5×10 ¹⁹ cm ^-3 .

According to the silicon-based heterojunction tunneling field-effect transistor structure described in this solution, the feature is that the thickness of the aluminum oxide dielectric layer on the intrinsic semiconductor layer is 4 nanometers.

According to the silicon-based heterojunction tunneling field effect transistor structure described in this proposal, the gate metal electrode is titanium-tungsten metal, and the metal electrode is formed on the side wall of the vertical structure by ICP etching.

According to a silicon-based heterojunction tunneling field effect transistor structure described in this scheme, it is characterized in that a 20 nanometer thick N-type doped gallium arsenide layer, an intrinsically doped gallium arsenide layer and a P-type doped Doped gallium antimonide semiconductor layer forms a vertical mesa structure.

Beneficial effect

Through the implementation of this invention, the present invention can increase the valence band of the source material to be higher than the valence band of the drain material through III-V semiconductor energy band cutting technology, thereby realizing the tunneling barrier and tunneling of the PN junction The reduction of the distance improves the electronic tunneling efficiency of the device and increases the maximum saturation current of the device; on the other hand, the intrinsic layer is added in the middle of the PN junction to reduce the leakage current of the device under zero bias voltage; thereby increasing the current switching ratio of the device.

Description of drawings:

In order to fully understand the advantages of the embodiment, the reference figure is as follows:

Figure 1: Device structure of this embodiment.

Specific examples:

The making and using of embodiments of the invention are discussed in detail below. This embodiment is only illustrative and cannot be used to limit the scope of the present invention.

The invention provides a silicon-based heterojunction tunneling field effect transistor structure, which specifically includes:

an n-type doped gallium arsenide semiconductor layer (101) at a thickness of 100 nanometers;

an intrinsic gallium arsenide semiconductor layer (102) with a thickness of 10 nanometers grown on the n-type doped gallium arsenide layer (101);

a p-type gallium antimonide semiconductor layer (103) grown on the intrinsic gallium arsenide layer (102);

An aluminum oxide dielectric layer (104) grown on the intrinsic gallium arsenide semiconductor layer;

a gate metal electrode (105) formed on the aluminum oxide dielectric layer;

a source electrode (106) formed on the p-type gallium antimonide semiconductor layer (103);

A drain electrode (107) formed on the N-type doped gallium arsenide semiconductor layer (101).

In this embodiment, the thickness of the P-type gallium antimonide semiconductor layer (103) is 10 nanometers, and the doping concentration is 5×10 ¹⁹ cm ^-3 .

In this embodiment, the thickness of the aluminum oxide dielectric layer (104) on the intrinsic semiconductor layer is 4 nanometers.

The gate metal electrode (105) described in this embodiment is titanium-tungsten metal, and the metal electrode is formed on the sidewall of the vertical structure by ICP etching.

In this embodiment, an N-type doped gallium arsenide layer (101), an intrinsically doped gallium arsenide layer (102) and a P-type doped gallium antimonide semiconductor layer (103) are formed with a thickness of 20 nanometers. A vertical mesa structure.

In this embodiment, both the gate dielectric and the gate metal are grown and deposited on the side of the mesa structure.

In this embodiment, the source electrode (106) formed on the P-type gallium antimonide semiconductor material is a three-layer metal of platinum titanium gold.

In this embodiment, the drain electrode (107) formed on the N-type doped gallium arsenide semiconductor layer is a nickel-germanium-gold system multilayer metal.

Claims (5)

1. A silicon-based heterojunction tunneling field-effect transistor structure, specifically comprising: an n-type doped gallium arsenide semiconductor layer; a 10 nm thick intrinsic gallium arsenide semiconductor layer; A p-type gallium antimonide semiconductor layer; An aluminum oxide dielectric layer grown on the intrinsic gallium arsenide semiconductor layer; a gate metal electrode formed on the aluminum oxide dielectric layer; a source electrode formed on the p-type gallium antimonide semiconductor material; A drain electrode formed on the N-type doped gallium arsenide semiconductor layer. 2. A silicon-based heterojunction tunneling field effect transistor structure according to claim 1, characterized in that the thickness of the P-type gallium antimonide semiconductor layer is 10 nanometers, and the doping concentration is 5×10 ¹⁹ cm ^-3 . 3. A silicon-based heterojunction tunneling field-effect transistor structure according to claim 1, characterized in that the thickness of the aluminum oxide dielectric layer on the intrinsic semiconductor layer is 4 nanometers. 4. A silicon-based heterojunction tunneling field-effect transistor structure according to claim 1, characterized in that the gate metal electrode is titanium-tungsten metal, and the metal electrode is formed on the side wall of the vertical structure by ICP etching. 5. A silicon-based heterojunction tunneling field-effect transistor structure according to claim 1, characterized in that 20 nanometers of thick N-type doped gallium arsenide layer, intrinsically doped gallium arsenide layer and The P-type doped gallium antimonide semiconductor layer forms a vertical mesa structure.