CN106601796A - Semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device manufacturing method, comprising: forming a plurality of fins and STIs between the fins on a substrate, each fin comprising a high mobility material; ion implantation is performed to form a diffusion preventing layer in each fin to prevent diffusion of elements in the high mobility material to the substrate. According to the manufacturing method of the semiconductor device, ions are injected into the high-mobility fins to form the anti-diffusion layer, so that the concentration of high-mobility elements in the channel region is prevented from being reduced, and the stability of the device is improved at low cost.

Description

Semiconductor device manufacturing method

technical field

The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET with a channel of small size and high mobility.

Background technique

In order to continue to push forward Moore's Law, the driving current of the device needs to be further improved and the short-channel effect needs to be controlled. Bulk silicon fin field-effect transistor (finfet) devices with integrated high-mobility channels are considered to be the most promising devices to promote the development of Moore's Law.

The manufacturing method of the high mobility channel finfet device is usually to grow the high mobility channel material on the silicon substrate. High-mobility channels are usually made of high-mobility materials, such as germanium, silicon germanium, III-V group materials, II-VI group materials, and the like. Taking silicon germanium as an example, fins made of high-mobility materials are formed after the growth is completed. One integration solution is to epitaxially a layer of silicon germanium as a high mobility material after forming silicon fin and STI by conventional methods.

But high-mobility channel devices often face a problem. That is, the high-mobility material will diffuse into the substrate material (usually silicon) during the subsequent high-temperature process of forming the fin made of the high-mobility material. This will reduce the concentration of high-mobility elements in the fin channel region made of high-mobility materials, so that the mobility of the channel will be lower than the pre-designed channel mobility, which will deteriorate the performance of the device. The high-mobility channel finfet of the SOI substrate can avoid this problem, but it faces the problems of high substrate cost and poor heat dissipation of the SOI substrate.

Contents of the invention

From the above, the purpose of the present invention is to overcome the above technical difficulties and propose a FinFET manufacturing method with a small-sized high-mobility channel that can simplify the process and reduce the cost.

To this end, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a plurality of fins on a substrate and STIs between the fins, each fin comprising a high-mobility material; performing ion implantation at each An anti-diffusion layer is formed in the fins to prevent elements in the high-mobility material from diffusing to the substrate.

Wherein, the step of forming a plurality of fins and STIs between the fins on the substrate further includes: etching the substrate to form a plurality of fins and trenches between the fins; forming STIs in the trenches; etching At least a portion of each fin is removed, leaving a plurality of second trenches in the STI; high mobility material is epitaxially grown in the plurality of second trenches.

Wherein, after the step of leaving a plurality of second trenches, it further includes roughening the bottom of each second trench.

Wherein, the atomic number of the implanted ions is smaller than the elements in the high mobility material other than the substrate.

Wherein, the implanted ions are selected from any one of C, N, O, F, S and combinations thereof.

Wherein, before or after forming the anti-diffusion layer, it further includes performing a second ion implantation to form an anti-penetration barrier layer in each fin.

Among them, the doping elements of the anti-punching barrier layer are selected from elemental substances or compounds composed of group III or group V elements and the substrate itself or other group elements according to different types of devices.

Wherein, the high-mobility material is selected from group II-VI, group III-V or group IV, or compounds formed with this group or other groups.

Wherein, after forming the anti-diffusion layer, it further includes forming a gate stack across multiple fins, and forming source and drain regions in the fins on both sides of the gate stack.

According to the manufacturing method of the semiconductor device of the present invention, ions are implanted into the high-mobility fin to form an anti-diffusion layer, which prevents the concentration of high-mobility elements in the channel region from decreasing, and improves device stability at low cost.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 to 2 are cross-sectional views of various steps of the FinFET manufacturing method according to the present invention; and

FIG. 3 is a schematic flow chart of a method for manufacturing a FinFET device according to the present invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a FinFET manufacturing method of a small-sized high-mobility channel capable of simplifying the process and reducing the cost is disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

As shown in FIG. 3 and FIG. 1 , a plurality of high mobility fins are formed.

A substrate 1 is provided, and its material can be single crystal silicon, SOI, single crystal germanium, GeOI, strained silicon (Strained Si), silicon germanium (SiGe), or a compound semiconductor material, such as gallium nitride (GaN), arsenide Gallium (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, etc. In a preferred embodiment of the present invention, the substrate 1 is single crystal silicon, so as to be compatible with the CMOS process and reduce the manufacturing cost.

Using a mask pattern (not shown, it can be a soft mask of photoresist or a hard mask of dielectric material) to etch the substrate 1, a plurality of fin structures 1F extending along the first direction are formed, and adjacent fin structures 1F are formed. Trenches (not labeled) between fin structures. The etching process is preferably anisotropic dry etching, such as plasma dry etching or RIE, etching gas such as carbon-fluorine-based gas (containing at least carbon, fluorine atoms, and other atoms such as hydrogen, nitrogen, oxygen, etc. ), chlorine gas, bromine vapor, HCl, HBr, etc., and oxygen, CO, ozone and other oxidants can also be added to adjust the etching rate.

The trenches between the fin structures 1F are filled with an insulating material to form shallow trench isolation (STI) 2 , which completely fills the trenches between the fin structures 1F. For example, by thermal oxidation, LPCVD, PECVD and other processes, the STI 2 of insulating material is formed in the trenches between the fin structures 1F. In a preferred embodiment of the present invention, the material of STI 2 is silicon oxide or silicon nitride-based material, such as SiO _x , SiN _x , SiO _x N _y , SiO _x C _y , SiO _x F _{y ,} SiO _x H _y , SiN _x C _y, SiN _x F _y (each xy need not be an integer). The portion 1C exposing the fin 1F above the top of the STI 2 will serve as the source, drain and channel regions of the FinFET. In another preferred embodiment of the present invention, the material of STI 2 is a low-k material to reduce the parasitic capacitance of the device, and the formation process is spin coating, spray coating, and screen printing, wherein the low-k material includes but is not limited to organic low-k materials ( Such as organic polymers containing aryl groups or polycyclic rings), inorganic low-k materials (such as amorphous carbon-nitrogen films, polycrystalline boron-nitride films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (such as disilicon Trioxane (SSQ)-based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). In yet another preferred embodiment of the present invention, the material of STI2 further includes a sub-layer of negative thermal expansion dielectric material or positive thermal expansion dielectric material (preferably, the absolute value of the linear volume expansion coefficient is greater than 10 ^-4 /K at a temperature of 100K) , to further enhance the stress in the channel region, the negative thermal expansion dielectric material is a perovskite oxide including any one selected from Bi _0.95 La _0.05 NiO ₃ , BiNiO ₃ , ZrW ₂ O ₈ and a combination thereof, and the positive thermal expansion dielectric material is a frame material including Ag ₃ [Co(CN) ₆ ].

Thereafter, the selective etch removes at least a portion (eg, the top) of the fin 1F, leaving the remainder of the fin 1F in the STI 2 (lower portion shown in FIG. out). Preferably, an anisotropic etching method is used to etch the material of the fin 1F, for example, TMAH and KOH are used for Si material. Preferably, an additional microetching or roughening process is performed on the top of the remaining part of the fin 1F, so that the top has protrusions or depressions (roughened structure) with a certain orientation and a certain size (width, spacing) to improve subsequent epitaxy. The quality of the grown film (for example, a concave-convex structure of about 0.5-1 nm will make the epitaxial material use the concave-convex as a nucleation layer to accelerate the fusion between crystal grains).

Next, use HDPCVD, MOCVD, MBE, ALD and other processes to epitaxially grow high-mobility materials in multiple trenches (the carrier mobility of the material is greater than that of the substrate, for example, greater than the carrier mobility of the substrate material Si) A channel layer 1C is formed until it covers the top of the STI 2 . The high-mobility material of the channel layer 1C is selected from group II-VI, group III-V or group IV elemental substances or compounds formed with this group or other groups, such as group IV elemental substances, group IV compounds, and group III-V compounds , II-VI group compounds, such as SiGe, SiC, SiGeC, SiGeSn, SiGaN, SiGaP, SiGaAs, InSiN, InSiP, InSiAs, InSiSb, GaN, InSb, InP, InAs, GaAs, SiInGaAs any one and its combination of high mobility Ratio materials or their component ratio materials. In a preferred embodiment of the present invention, the material of the channel layer 1C is SiGe. The high mobility material layer is then preferably planarized using CMP until the top of the STI 2 is exposed.

Subsequently, the STI 2 is etched back until the channel layer 1C of high mobility material is completely exposed. The etch back can be a wet etch, such as HF etch for silicon oxide, or hot phosphoric acid etch for silicon nitride. Etching back can also be dry etching, such as plasma dry etching using fluorocarbon-based etching gas (adjusting the ratio of xyz in fluorocarbon C _x H _y F _z to increase the etching speed for certain materials) etching or reactive ion etching. Preferably, the etch-back stops at the top of the fin remainder 1F of substrate 1 material, for example at the interface of the fin 1F and the high mobility channel layer 1C.

Then, as shown in FIG. 3 and FIG. 2, ion implantation is performed to form an anti-diffusion layer 3 in the fin channel layer 1C of high-mobility material, that is, below the channel region 1C (for example, near the top of the STI 2, the fin at or below the interface between the rest of the chip 1F and the channel region 1C). The implantation energy is, for example, 500eV-3KeV and preferably 1KeV- ^2.5KeV , the implantation dose is, for example, ^1019-5 ×1021 atoms/ ^cm3 , and the atomic number of the implanted elements is smaller than that of the non-Si elements in the channel layer 1C made of high-mobility materials. That is, the element that will subsequently diffuse (Ge in a preferred embodiment of the present invention). Implanted ions are for example preferably selected from any one of C, N, O, F, S and combinations thereof, and the most optimal is C (C, Si, Ge are the same group IV elements, the atomic structure is similar, and the anti-diffusion layer can be viewed as As a network structure formed by Si and C, if you want to prevent the diffusion or migration of high-mobility materials such as Ge, the purpose of choosing a smaller atomic number is to reduce the mesh size, which can effectively prevent the migration of materials with a larger atomic number. ). The ion implantation may be vertical implantation or oblique implantation (toward the channel region 1C), and the angle of the oblique implantation is, for example, 5-15 degrees. Annealing can be performed after the implantation, so that the implanted impurities are activated and redistributed, and the concentration peak of the anti-diffusion layer 3 is precisely controlled at or near the top of the STI 2 (that is, below the channel region 1C at the top of the fin 1F, such as with The top of STI 2 is flush or slightly lower by 1~3nm). The annealing temperature is, for example, 550-1050°C, preferably 650-900°C, most preferably 700-800°C, and the annealing time is 1s-10min, 10s-5min, 1-3min.

Optionally or preferably, before or after ion implantation is performed to form the anti-diffusion layer, additional ion implantation is performed to form an anti-puncture barrier layer (not shown) in the fin 1F, thereby improving the distance between the substrate and the channel. The insulation isolation effect eliminates or reduces the substrate leakage current. The implanted doping elements of the anti-punching barrier layer are selected from group III or group V elements according to different types of devices, and can form simple substances or compounds with the substrate itself (such as Si) or with other group elements. In an embodiment of the present invention, the doping elements of the anti-punching barrier layer include B, BF ₂ , Al, Ga, In for nMOS, and include P, As, and Sb for pMOS. In other embodiments of the present invention, the implanted doping elements of the anti-puncture barrier layer are O and N, so as to react with Si in the substrate 1/fin 1F to form insulating materials of silicon oxide, silicon oxynitride, and silicon nitride. Further enhance the anti-penetration effect of the substrate. It is worth noting that the anti-penetration barrier layer should be located under the anti-diffusion layer 3 to ensure effective reduction of substrate leakage.

Thereafter, a gate stack across the channel region 1C can be deposited and formed, source and drain regions are formed in the fins on both sides of the gate stack, an interlayer dielectric layer (ILD) covering the entire wafer is formed, and the ILD is etched to form contact holes And fill metal to realize source-drain interconnection, and finally complete the manufacturing of FinFET devices.

In the above method, compared with the conventional bulk silicon high-mobility channel finfet, one more step of carbon implantation during PTSL implantation can solve the problem. The problem of diffusion of the channel material to the substrate of the device manufactured by this solution will be better suppressed. Therefore, the high mobility characteristic is maintained and the performance of the device is improved. In addition, compared with SOI devices, expensive SOI substrates are not required, and there is no problem of heat dissipation.

According to the manufacturing method of the semiconductor device of the present invention, ions are implanted into the high-mobility fin to form an anti-diffusion layer, which prevents the concentration of high-mobility elements in the channel region from decreasing, and improves device stability at low cost.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (9)

1. A method of manufacturing a semiconductor device, comprising: forming a plurality of fins on the substrate and an STI between the fins, each fin comprising a high mobility material; Ion implantation is performed to form an anti-diffusion layer in each fin to prevent elements in the high-mobility material from diffusing into the substrate. 2. The method of claim 1, wherein the step of forming the plurality of fins on the substrate and the STI between the fins further comprises: Etching the substrate to form a plurality of fins and trenches between the fins; Formation of STI in the trench; etching away at least a portion of each fin, leaving a plurality of second trenches in the STI; A high mobility material is epitaxially grown in the plurality of second trenches. 3. The method of claim 1, wherein after the step of leaving a plurality of second trenches, further comprising, roughening the bottom of each second trench. 4. The method of claim 1, wherein the implanted ions have an atomic number smaller than an element in the high mobility material other than the substrate. 5. The method of claim 4, wherein the implanted ions are selected from any one of C, N, O, F, S and combinations thereof. 6. The method of claim 1, further comprising, before or after forming the anti-diffusion layer, performing a second ion implantation to form an anti-puncture barrier layer in each fin. 7. The method according to claim 6, wherein the doping element of the anti-penetration barrier layer is selected as a simple substance or a compound composed of group III or group V elements and the substrate itself or other group elements according to different types of devices. 8. The method of claim 1, wherein the high-mobility material is selected from group II-VI, group III-V or group IV, or compounds formed with this group or other groups. 9 . The method of claim 1 , further comprising, after forming the anti-diffusion layer, forming a gate stack spanning multiple fins, and forming source and drain regions in the fins on both sides of the gate stack.