CN106601632A - Production method of semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device and relates to the technical field of semiconductors. The manufacturing method includes: step S101: providing a semiconductor wafer, forming a pad on the semiconductor wafer and a passivation layer covering the semiconductor wafer and exposing the pad; step S102: forming a pad on the pad Forming bumps; step S103 : performing surface treatment on the passivation layer to increase the surface roughness of the passivation layer; step S104 : performing a reflow process so that the bumps form a stable alloy. The manufacturing method of the semiconductor device of the present invention can improve the cohesive force between the passivation layer and the filler, thereby improving the yield of the flip-chip packaging process.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device.

Background technique

With the development of portable and high-performance microelectronic products in the direction of shortness, smallness, lightness, and thinning, the traditional wire bonding method (Wire Bonding) as a packaging technology for combining chips with various substrates can no longer meet the needs of current consumer electronics products. Demand, replaced by bump packaging has become the key technology of wafer-level packaging. The flip-chip bump structure has become a commonly used packaging technology due to its high mounting density of semiconductor devices. As shown in FIG. 1 , in the flip-chip bump structure, an under-ball metallurgy (UBM) 101 and a bump 102 on the UBM layer are formed on the chip 100 , and the bump is connected to one surface of the package substrate 200 The connection of the pad 201 on the chip 100 and the package substrate 200 can realize the connection between the chip 100 and the package substrate 200 . In addition, solder balls 202 are formed on the other surface of the substrate 200 , through which the packaged chip can be mounted on a printed circuit board (PCB) to form various electronic products.

Further, a passivation layer (not shown) is usually formed on the chip 100 to protect the chip structure, such as a polyimide (Polyimide) layer, but in the existing flip-chip structure, the passivation layer and the filler The bonding force between 300 is weak, and the delamination phenomenon shown in Figure 1 delamination interface 400 is prone to occur. In the flip-chip packaging process, it will undergo two high-temperature reflow processes (about 240 degrees). If the passivation layer and The delamination phenomenon between the fillers 300 will cause the tin-silver components in the bump 102 to be connected together through the delamination interface 400 in the subsequent high-temperature reflow process, thereby causing a chip short circuit.

Therefore, in order to solve the above technical problems, it is necessary to propose a new method for manufacturing semiconductor devices.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention proposes a method for manufacturing a semiconductor device, which can improve the bonding force between the passivation layer and the filler, thereby improving the yield of the flip-chip packaging process.

One embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: step S101: providing a semiconductor wafer, forming pads on the semiconductor wafer, covering the semiconductor wafer and exposing the pads a passivation layer; step S102: forming a bump on the pad; step S103: performing surface treatment on the passivation layer to increase the surface roughness of the passivation layer; step S104: performing a reflow process, so that the bumps form a stable alloy.

Further, in the step S103, the surface roughness of the passivation layer is increased by bombarding the passivation layer with plasma.

Further, in the step S103, the passivation layer is bombarded with oxygen plasma.

Further, in the step S103, oxygen plasma is used to bombard the passivation layer in a nitrogen environment.

Further, the step S102 includes the following steps:

Step S1021: forming an under-ball metal layer covering the passivation layer and the pad;

Step S1022: forming a patterned mask layer on the UBM layer, the patterned mask layer has openings at positions corresponding to the pads;

Step S1023: forming a bump in the opening;

Step S1024: removing the mask layer;

Step S1025 : removing the UBM layer located outside the bump, and retaining a portion located at the bottom of the bump.

Further, the mask layer is a photoresist layer.

Further, the step S103 is implemented between the step S1024 and the step S104.

Further, the following steps are also included: Step S105: providing a packaging substrate, the packaging substrate has a substrate pad corresponding to the bump, and the semiconductor wafer and the substrate pad are connected through the bump and the substrate pad. Packaging substrate; step S106: adding filler between the semiconductor wafer and the packaging substrate to complete packaging.

In the manufacturing method of the semiconductor device of the present invention, the surface treatment step is added before the reflow of the wafer bump, and the roughness of the passivation layer is increased by performing surface treatment on the passivation layer, thereby increasing the surface area and contact area of the passivation layer, In turn, the adhesion between the passivation layer and the filler is improved, and finally the yield of the flip-chip packaging process is improved.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1 shows a schematic diagram of an existing flip-chip bump package structure with a layered interface;

Fig. 2 shows a kind of flowchart according to the manufacturing method of semiconductor device of the present invention;

Fig. 3 shows a detailed step diagram of step S102 in Fig. 2;

FIG. 4 shows SEM photographs of defective chips and non-defective chips.

detailed description

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

As mentioned earlier, in the current flip-chip packaging structure, a delaminated interface is prone to appear between the passivation layer and the filler, resulting in the tin-silver components in the bump being connected together through the delaminated interface in the subsequent high-temperature reflow process , resulting in a short circuit of the chip. This is because the coefficient of thermal expansion and internal stress between the passivation layer and the filler are different at high temperature, and delamination is likely to occur during the high-temperature reflow process of the bump. In order to avoid short circuits due to delamination between the passivation layer and the filler, the present invention proposes a manufacturing method of a semiconductor device, which adds a surface treatment step before wafer bump reflow, by performing surface treatment on the passivation layer, The roughness of the passivation layer is increased, thereby increasing the surface area and contact area of the passivation layer, thereby improving the adhesion between the passivation layer and the filler, and finally improving the yield of the flip-chip packaging process.

In order to thoroughly understand the present invention, detailed steps and detailed structures will be provided in the following description, so as to illustrate the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described with reference to FIGS. 2 to 4 . Wherein, Fig. 2 shows a kind of flow chart according to the manufacturing method of semiconductor device of the present invention; Fig. 3 shows the detailed step diagram of step S102 in Fig. 2; SEM photo.

As shown in FIG. 2, the method for manufacturing a semiconductor device according to Embodiment 1 of the present invention includes the following steps:

Step S101: providing a semiconductor wafer, forming a pad on the semiconductor wafer and a passivation layer covering the semiconductor wafer and exposing the pad;

Wherein, the semiconductor wafer can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and multilayers composed of these semiconductors The structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

A plurality of chips containing circuits, which may be formed of semiconductor elements such as NMOS and/or PMOS, and metal interconnect structures electrically connected to transistors, are formed in a semiconductor wafer by various methods to implement various functions. And finally, these circuits are led out to pads through corresponding interconnection structures, so as to be electrically connected with subsequent packaging substrates. The pads can be formed with a metal layer by processes such as PVD, CVD, etc., and the corresponding pads can be formed by etching and other methods, and the pads can be made of suitable conductive materials such as aluminum.

The passivation layer covers the semiconductor wafer and exposes the bonding pads, for protecting devices formed on the semiconductor wafer. The passivation layer can be formed by common methods such as PECVD, which can use silicon nitride, silicon oxynitride, silicon dioxide, BPSG, PSG, and polyimide (Polyimid), etc., through the patterned passivation layer can expose solder The disc can be specifically formed by photolithography and etching methods commonly used in the art, and will not be described in detail here.

It can be understood that the above-mentioned passivation layer and bonding pad can be the passivation layer and bonding pad originally formed on the semiconductor wafer, and can also be a second passivation layer and new bonding pad formed through redistribution layer (RDL) subsequently. plate.

Exemplarily, in this embodiment, the passivation layer is a new passivation layer formed by a redistribution layer (RDL), which uses polyimide (Polyimid) material, and can simultaneously serve as a stress buffer layer for a semiconductor wafer .

Step S102, forming a bump on the pad.

Exemplarily, as shown in FIG. 3, in this implementation, the bump is formed through the following steps:

Step S1021 : forming an under-ball metal layer covering the passivation layer and the pad. Specifically, the metal layer at the bottom of the ball can be sputtered on the passivation layer and the pad by sputtering, and the metal layer at the bottom of the ball can include multiple layers of metal, such as forming a layer of titanium at the bottom layer as a diffusion barrier layer, so as to Prevent the upper layer metal from diffusing downward to contaminate the semiconductor wafer. A seed layer is formed on the titanium layer for subsequent bump formation. The thickness of the metal layer at the bottom of the ball can be determined as required. Exemplarily, in this implementation, the thickness of the metal layer at the bottom of the ball is

Step S1022: forming a patterned mask layer on the UBM layer, the patterned mask layer having openings at positions corresponding to the pads.

Exemplarily, in this implementation, the mask layer is a photoresist layer. That is, a photoresist layer is coated on the UBM layer, and an opening for forming a bump is formed through operations such as exposure and development, and the position of the opening is located corresponding to the position of the pad.

Step S1023: forming bumps in the openings.

Exemplarily, in this implementation, a bump is formed on the opening by electroplating, and the height of the bump is determined as required.

Step S1024: removing the mask layer.

Exemplarily, in this embodiment, the mask layer is a photoresist layer, and the photoresist layer can be removed by a suitable adhesive removing solvent, or the photoresist layer can be peeled off by an ashing (Ashing) method, both of which are Commonly used methods in this field will not be repeated here.

Step S1025 : removing the UBM layer on the outside of the bump, and retaining the part on the bottom of the bump.

Exemplarily, the UBM layer located outside the bump is removed by a suitable wet or dry etching method, and the portion located at the bottom of the bump is reserved.

Exemplarily, in this embodiment, Cu is removed by using Microetch 85 etchant; ② Ti is removed by using HF Acid etchant. Of course, if the metal layer at the bottom of the ball is made of other materials, other suitable removal methods can be selected, and are not limited to the examples provided by the present invention.

Step S103: performing surface treatment on the passivation layer to increase the surface roughness of the passivation layer.

Exemplarily, in this embodiment, the surface roughness of the passivation layer is increased by bombarding the passivation layer with plasma. For example, by bombarding the passivation layer with oxygen plasma, the surface roughness of the passivation layer is increased, thereby increasing the surface area of the passivation layer, so that when the filler is subsequently formed, the gap between the passivation layer and the filler As the contact area increases, the bonding force between the corresponding passivation layer and the filler will also increase, which can reduce the possibility of delamination and improve the reliability of the package.

Preferably, in this implementation, the passivation layer is bombarded with oxygen plasma in a nitrogen environment.

Exemplarily, in this embodiment, the above-mentioned surface treatment is performed by using the Desum process, using oxygen and nitrogen to etch the passivation layer, wherein the temperature is 30°C, the pressure is 1000mTorr, the microwave power is 2700Watts, and the O2 flow rate is 4500sccm, The N2 flow rate is 455 sccm, and the time is about 2 to 5 minutes.

Step S104 : performing a reflow process so that the bumps form a stable alloy.

Exemplarily, a high temperature reflow process is performed at about 240° C. so that the bumps form a stable alloy.

Step S105: providing a package substrate, the package substrate has a base pad corresponding to the bump, and the semiconductor wafer and the package substrate are connected through the bump and the base pad.

Referring to FIG. 1 for the structure of the packaging substrate, the semiconductor wafer and the packaging substrate can be connected by welding bumps on the semiconductor wafer and corresponding base pads on the packaging substrate.

Step S106: adding filler between the semiconductor wafer and the package substrate to complete the package.

A filler, such as epoxy resin, is added between the semiconductor wafer and the packaging substrate to seal the gap between the semiconductor wafer and the packaging substrate to complete the packaging.

So far, all the steps of the implementation of the semiconductor device have been completed. It can be understood that other steps may be included before, during or after the above steps, such as wafer thinning and dicing steps before packaging, which all cover In the present invention.

In the manufacturing method of the semiconductor device of this embodiment, a surface treatment step is added before the reflow of the wafer bump, and the roughness of the passivation layer is increased by performing surface treatment on the passivation layer, thereby increasing the surface area and contact area of the passivation layer , thereby improving the adhesion between the passivation layer and the filler, and ultimately improving the yield of the flip-chip packaging process. As shown in Figure 4, among the figure (a) does not adopt the SEM picture of the chip that the manufacturing method of semiconductor device of the present invention obtains, and it has the defect such as delamination, among the figure (b) adopts the manufacturing method of semiconductor device of the present invention to obtain The SEM photograph of the chip obtained, which is free from defects such as delamination.

It can be understood that the above-mentioned embodiment is only an example, which provides a preferred embodiment according to the present invention, but the present invention is not limited thereto, for example, the order of each step of the above-mentioned manufacturing method of the semiconductor device can be adjusted as required For example, although implementing step S103 between step S1025 and step S104 is a preferred implementation mode, it can avoid reducing the impact of the Desum process on bumps, but can implement step S103 between other steps as required, as long as the bluntness can be increased. The adhesion between the chemical layer and the subsequent filler is enough.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (8)

1. a kind of manufacture method of semiconductor device, it is characterised in that comprise the steps：

Step S101：There is provided semiconductor crystal wafer, on the semiconductor crystal wafer formed pad with And cover the semiconductor crystal wafer and expose the passivation layer of the pad；

Step S102：Projection is formed on the pad；

Step S103：The passivation layer is surface-treated, to increase the passivation layer Surface roughness；

Step S104：Reflux technique is performed, so that the projection forms stable alloy.

2. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that In step S103, the passivation is increased by passivation layer described in plasma bombardment The surface roughness of layer.

3. the manufacture method of semiconductor device as claimed in claim 2, it is characterised in that The passivation layer is bombarded using oxygen plasma in step S103.

4. the manufacture method of semiconductor device as claimed in claim 3, it is characterised in that The passivation layer is bombarded using oxygen plasma in nitrogen environment in step S103.

5. the manufacture method of the semiconductor device as described in one of claim 1-4, its feature It is that step S102 comprises the steps：

Step S1021：Form the ball bottom metal layer for covering the passivation layer and pad；

Step S1022：Patterned masking layer, the figure are formed on the ball bottom metal layer Change mask layer and there is opening in position corresponding with the pad；

Step S1023：Projection is formed in said opening；

Step S1024：Remove the mask layer；

Step S1025：The ball bottom metal layer on the outside of projection is removed, is retained positioned at described convex The part of block bottom.

6. the manufacture method of semiconductor device as claimed in claim 5, it is characterised in that The mask layer is photoresist layer.

7. the manufacture method of semiconductor device as claimed in claim 5, it is characterised in that Implement step S103 between step S1024 and step S104.

8. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that Also comprise the steps：

Step S105：Base plate for packaging is provided, the base plate for packaging has corresponding with the projection Substrate pad, the semiconductor crystal wafer and envelope are connected by the projection and the substrate pad Dress substrate；

Step S106：Between the semiconductor crystal wafer and the base plate for packaging add filler with Complete encapsulation.