CN106601634A - Chip package technology and chip package structure - Google Patents

Abstract

The present invention provides a chip packaging process and a chip packaging structure. In the chip packaging process provided by the present invention, after the chip is attached to the packaging carrier, the position data of the electrode pad on the chip is obtained first, and then the obtained electrode pad is used to The position data of the pad forms a rewiring layer on the encapsulation body encapsulating the chip, so as to rearrange the electrodes of the chip. Therefore, the formed rewiring layer has a higher degree of direct alignment with the chip, Moreover, the packaging process is simple, and the packaging structure formed by the process has low manufacturing cost and high reliability and integration.

Description

Chip packaging process and chip packaging structure

technical field

The invention relates to the technical field of chip packaging, in particular to a chip packaging process and a chip packaging structure.

Background technique

In the manufacture of integrated circuits, chips are typically packaged prior to integration with other electronic assemblies. The chip packaging process that was widely used in the early days was the wire bonding packaging process, that is, the electrode terminals on the chip are bonded to the lead frame through metal wires, and then the packaging method is plastic-encapsulated. However, the area of the packaging structure formed by the wire bonding packaging process is relatively large, and the packaging performance cannot be effectively improved due to the influence of metal lead resistance and parasitic capacitance. Therefore, the flip-chip packaging process emerged as the times require, and the flip-chip packaging structure formed by the flip-chip packaging process has attracted much attention due to its small package size and high packaging performance.

Figure 1 is a schematic diagram of the structure of a flip-chip package formed by a flip-chip packaging process. The chip 02 is electrically connected to the lead frame 01 through the conductive bump 021 on its active surface, and the plastic compound 03 encapsulates the chip 02 and exposes the lead frame. 01 as a pin for electrical connection with an external circuit. The flip-chip packaging process steps for forming this flip-chip packaging structure include chip bonding, flipping and plastic packaging. As shown in FIG. 2 , a plurality of chips 02 are pasted at predetermined positions on the package carrier 00 , wherein conductive bumps 021 are arranged on the electronic terminals on the active surface of each chip 02 , and then the chips on the package carrier 00 are It is buckled upside down onto the pre-set lead frame 01 as shown in FIG. 3 , so that the conductive bump 021 is electrically connected to the pad on the lead frame 01 , and finally plastic-encapsulated to form a plastic package 03 . However, as shown in FIG. 2 , some chips 02 cannot be pasted to the predetermined position on the package substrate 00 (the dotted line) very precisely. This inevitable deviation during pasting will cause the chip 02 to be buckled upside down on the lead frame 01. , as shown in FIG. 4 , the conductive bump 021 cannot be electrically connected to the corresponding pad on the lead frame, which may cause short circuit or open circuit of the package structure, which affects the reliability of the package.

In addition, in the prior art, when the electrodes on the chip 02 need to be rearranged by using the redistribution layer, the redistribution layer will be formed on the chip 02 with a preset pattern. However, the chip 02 is mounted on the In the process of packaging the carrier, it will deviate from the preset position, so that the position of the electrode pad on the chip 02 will also deviate from the preset position accordingly, so that the formed redistribution layer and the chip 02 cannot be accurately aligned. Accuracy, which will affect the reliability of the chip package.

Contents of the invention

In view of this, the present invention provides a chip packaging process and a chip packaging structure to simplify the process complexity, reduce packaging costs, improve the reliability of chip packaging, and increase the integration of packaged chips.

A chip packaging process, characterized in that, comprising:

Mounting at least one chip on the packaging carrier with the active surface facing up, the active surface of the chip is provided with electrode pads;

Obtain the position data of the electrode pad, and store the position data:

According to the position data, at least one redistribution layer is formed on the encapsulation body for encapsulating the chip, so as to rearrange the positions of the electrodes of the chip.

Preferably, the step of forming a first layer of the redistribution layer on the encapsulation body includes:

A metal layer is formed on the encapsulation body, the metal layer includes at least one layer of metal,

forming a layer of photoresist on the surface of the metal layer,

Correct the pattern to be exposed according to the position data so that the corrected exposure pattern matches the position of the electrode pad, and expose the photoresist according to the corrected exposure pattern to obtain patterned light Resist layer,

Using the patterned photoresist layer as a mask, the metal layer is etched and then the photoresist layer is removed to form the first secondary wiring layer.

Preferably, the step of forming a first layer of the redistribution layer on the encapsulation body includes:

forming a metal layer on the encapsulation,

forming a layer of photoresist on the surface of the metal layer,

Correct the pattern to be exposed according to the position data so that the corrected exposure pattern matches the position of the electrode pad, and expose the photoresist according to the corrected exposure pattern to obtain patterned light Resist layer,

Using the patterned photoresist layer as a mask, performing electroplating on the metal layer to form a patterned electroplating layer, and then removing the photoresist layer,

Etching away the metal layer exposed by the electroplating layer to form the first redistribution layer.

Preferably, the pattern to be exposed is a pattern to be exposed in a laser direct imaging machine, and the laser direct imaging machine corrects the pattern to be exposed according to the position data, and directly scans the corrected exposure pattern imaging on the photoresist to obtain the patterned photoresist layer.

Preferably, the chip packaging process further includes forming a soldering layer on the surface of the topmost redistribution layer, and the chip is connected to the outside through the soldering layer.

Preferably, the chip packaging process further includes: forming the

an encapsulation body, and exposing the electrode pads from the encapsulation body before forming the rewiring layer.

Preferably, the encapsulation is formed before the position data is acquired and after the chip is mounted on the packaging carrier, and the electrode pads are visible through the encapsulation.

Preferably, the chip is encapsulated with a transparent insulating material to form the encapsulation body.

Preferably, said enclosure is formed after acquiring said position data.

Preferably, before forming the redistribution layer, the encapsulation body is opened according to the position data, so as to expose the electrode pad.

Preferably, positioning marks are provided on the packaging carrier.

The position data characterizes the relative position of the electrode pad relative to the positioning mark.

Preferably, the package carrier includes a package substrate and an insulating layer on the package substrate, after the solder layer is formed, the package substrate is removed, and the package is cut along a preset cutting line and an insulating layer to form at least one chip package structure covered by an insulating material.

Preferably, the position data is acquired by means of optical scanning and positioning.

Preferably, the step of obtaining the position data by means of optical scanning and positioning includes:

highlighting the colors or shapes on the contours of all the chips, then acquiring contour images of the chips, and finally performing image processing on the contour images to obtain the position data;

Alternatively, highlight the colors or shapes on the center points of all the electrode pads, then acquire a center point image composed of the center points of all the electrode pads, and finally perform image processing on the center point image to obtain the position data.

Preferably, the chip packaging process further includes, before mounting the chip on the package carrier, forming a conductor on the electrode pad,

After the encapsulation is subjected to opening treatment, the conductor is exposed by the encapsulation.

Preferably, the conductor is a copper ball, and the copper ball contacts and is electrically connected to the electrode pad.

Preferably, the chip packaging process further includes, before mounting the chip on the packaging carrier, forming at least two positioning marks on the packaging carrier for determining a coordinate axis,

The relative position of the electrode pad relative to the positioning mark is the position of the electrode pad in the coordinate axis.

Preferably, the positioning mark is a positioning hole or a pad of a solid circle.

Preferably, the step of opening the envelope includes:

Locating the position of the electrode pad according to the position data and the positioning mark,

A laser beam is used to open the encapsulation body at the position where the electrode pad is located, so as to remove the insulating material on the electrode pad.

Preferably, a laser drilling machine is used to perform the opening treatment on the enclosure, and the step of performing the opening treatment on the enclosure includes:

The laser drilling machine corrects the hole pattern to be drilled according to the position data, and drills the encapsulation body according to the corrected hole pattern, so as to transfer the corrected hole pattern to the On the encapsulation body, an opening exposing the electrode pad is formed on the encapsulation body.

A chip packaging structure manufactured according to any one of the chip packaging processes described above.

It can be seen from the above that in the chip packaging process and structure provided by the present invention, after the chip is mounted on the packaging carrier, first obtain the position data of the electrode pads on the chip, and then use the obtained position data of the electrode pads in the package A rewiring layer is formed on the encapsulation of the chip to rearrange the electrodes of the chip. Therefore, the formed rewiring layer has a higher degree of direct alignment with the chip, and the packaging process is simple. The packaging structure formed by the process has low manufacturing cost and high reliability and integration.

In addition, in the chip packaging process provided by the present invention, before the electrode of the chip is drawn out, an encapsulation body for protecting the chip is formed first, and the electrode of the chip is electrically connected to the outside through the rewiring layer located on the encapsulation body. Therefore, the chip packaging process provided by the present invention does not need to be used for the bottom filling process, the process is simple and the cost is low, and because there is no need to use conductive bumps to electrically connect with the lead frame, the chip packaging process provided by the present invention is suitable for ultra-fine spacing. The chip packaging of the electrode terminals is conducive to improving the integration of the packaged chips.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

FIG. 1 is a schematic diagram of a flip-chip packaging structure;

Fig. 2 is a structural schematic diagram of sticking the chip on the packaging carrier;

Fig. 3 is the structural representation of lead frame;

Fig. 4 is a structural schematic diagram of flipping the chip onto the lead frame;

5a-5e are schematic cross-sectional views of structures formed in various process steps in the chip packaging process according to an embodiment of the present invention.

detailed description

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various drawings, the same components are denoted by similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present invention are described, such as the structure, material, size, process and technique of each constituent part, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

5 a - 5 e are schematic diagrams of structures formed by various process steps in the chip packaging process according to an embodiment of the present invention. The chip packaging process provided by the present invention will be described in detail below with reference to FIGS. 5a-5e. In order to better show the structures formed in each process step, FIGS. 5a and 5b are top views of the structures formed in the corresponding process steps, and FIGS. 5c, 5d and 5e are partial cross-sectional views of the structures formed in the corresponding process steps.

The chip packaging process provided according to the embodiment of the present invention includes the following steps:

Step 1: As shown in Figure 5a, which is a top view of the structure formed by the chip mounting process, at least one chip 21 is mounted on the package carrier 11 with the active surface facing upward, and the active surface of the chip is provided with electrode soldering. disc 211 , in addition, positioning marks 111 may also be provided on the package carrier 11 .

Before the chip 21 is mounted on the package carrier 11 , it is generally required to form at least two positioning marks 111 on the package carrier 11 for determining a coordinate axis. For example, there are four positioning marks 111 in this embodiment, which are respectively located on the four corners of the package carrier 11 . In the present application, the relative position of the electrode pad 211 relative to the positioning mark 111 refers to the position of the electrode pad 211 in the coordinate axis determined by the positioning mark 111 . Wherein, the positioning mark 111 may be a positioning hole, or may be a pad of a solid circle.

Step 2: Obtain the position data of the electrode pad relative to the positioning mark 111, and store the position data.

The position data is the coordinate parameter of the electrode pad 211 in the coordinate axis described in step 1, which characterizes the relative position of the electrode pad 211 relative to the positioning mark 111 . In this embodiment, the position data is acquired through an optical scanning positioning method. Specifically, the step of obtaining the position data by means of optical scanning and positioning includes:

Step 21a: Highlight the colors or shapes of the contours of all the chips 21 . For example, the packaging carrier 11 after mounting the chip 21 is placed in the optical scanning area of the optical scanning positioning device, and illuminated by the light of the optical scanning device, so that the light illumination or contrast of the outline of the chip 21 is higher than that of other areas , so that the color or shape on the outline of the chip 21 is highlighted.

Step 22a: after the color on the outline of the chip 21 is highlighted, acquire the outline image of the chip 21 . For example, the contour image can be obtained by taking pictures or optical scanning.

Step 23a: Perform image processing on the obtained outline image to obtain the position data.

In other embodiments, the step of obtaining the position data by means of optical scanning and positioning may also be the following steps:

Step 21b: making the colors or shapes at the center points of all the electrode pads 211 stand out. The method for highlighting the color or shape at the center point of the electrode pad may be the same as that in step 21a.

Step 22b: After the color of the center point of the electrode pad 211 is highlighted, acquire the center point image formed by the center point of the electrode pad 211. For example, the center point image can be obtained by taking pictures or optical scanning.

Step 23b: Perform image processing on the central point image to obtain the position data.

Step 3: As shown in FIG. 5 b , encapsulate the chip 21 with an insulating material to form an encapsulation body 31 , and expose the encapsulation body 31 to the positioning mark 111 . Fig. 5c is a schematic cross-sectional structure diagram of a package unit structure in Fig. 5b, each of the package units is composed of a chip 21, a part of the package carrier 11 located under the chip 21, and an encapsulation body 31 encapsulating the chip 21 .

The insulating material used to form the encapsulation body 31 may be a molding compound, such as epoxy molding compound, and the encapsulation body 31 may be formed through a molding process. In addition, as shown in FIG. 5c, the chip 21 and the package carrier 11 are directly provided with an adhesive layer 213, and in this embodiment, the package carrier 11 includes a package substrate 112 and an insulating layer 113 on the package substrate, so The insulating layer may be a plastic encapsulant, that is, the insulating layer 113 and the encapsulation body 31 may be made of the same material. Therefore, in step 1, the chip 21 is pasted on the package carrier 11 at a predetermined position through the adhesive layer 213 . In this embodiment, the material forming the encapsulation 31 is an opaque plastic encapsulant, so the encapsulation 31 is opaque. Therefore, before forming the encapsulation, it is necessary to obtain the position data of the electrode pad relative to the positioning mark 111 .

In another embodiment according to the present invention, the encapsulation body 31 can also be formed before the position data of the electrode pad 211 relative to the positioning mark 111 is obtained, and after the chip 21 is mounted on the package carrier 11, that is, in the above-mentioned embodiment The order of steps 2 and 3 can be reversed. In this case, in order to obtain the position data better, at least a part of the encapsulation body 31 is transparent, and the at least part includes this part located on the electrode pad 211, so that when obtaining Before the position data, the electrode pads can be seen through the encapsulation body 31 , so that the position data can be better obtained in subsequent process steps. In order to practice the purpose of seeing the electrode pads through the encapsulation body 31 , the chip 21 may be encapsulated with a transparent insulating material to form the encapsulation body 31 . In some other embodiments, the way to form the encapsulation body 31 may be as follows: First, the chip 21 is encapsulated (that is, not completely encapsulated) with an opaque insulating material to form an encapsulation body, and the encapsulation body exposes the electrodes. The pad 211 , and then on the encapsulation body, a covering body covering the electrode pad 211 is formed with a transparent material, and the encapsulation body and the covering body together constitute the encapsulation body 31 . Step 4: As shown in FIG. 5d, according to the position data stored in step 2 and the positioning mark 111 (not shown in FIG. 5d), the encapsulation 31 is opened to remove the electrode pad 211 for The insulating material that makes up the enclosure.

Since the encapsulation body 31 needs to be opened in step 4, in order to prevent the electrode pads 211 on the chip 21 from being damaged during the opening process, thereby damaging the devices in the chip 21, as shown in Figures 5a-5e, The chip packaging process steps provided by the present invention may further include: before mounting the chip 21 on the package carrier 11, forming a conductor 212 on the electrode pad 211 of the chip 21, and the conductor 212 is also formed after step 3. The encapsulation body 31 encapsulates. The conductor 212 may be a copper ball, and the copper ball 212 is directly formed on the electrode pad 211 , that is, is in contact with and electrically connected to the electrode pad 211 . Due to the protection of the copper balls 212 , even if the encapsulation body 31 is opened, even if the opening depth is slightly deeper than the preset one, the electrode pads 211 will not be damaged.

In step 4, the specific steps of opening the envelope include:

Step 41: Locate the position of the electrode pad according to the position data stored in step 2 and the positioning mark.

Step 42: Opening the encapsulation body 31 with a laser beam at the position where the electrode pad is located, so as to remove the insulating material on the electrode pad.

When opening the encapsulation body 31, in order to ensure that the chip can be electrically connected to the rewiring layer, it is necessary to ensure that all insulating materials on the electrode pads 211 are removed, so that after the opening, the electrode pads The conductor 212 on the 211 is exposed by the encapsulation body 31 for electrical connection with the subsequently formed redistribution layer.

In another embodiment according to the present invention, a laser drilling machine can be used to perform the opening process on the encapsulation body 31, and the specific steps are: make the laser drilling machine correct the hole pattern to be drilled according to the position data , and drill the encapsulation body 31 according to the amended drilling pattern, so as to transfer the amended drilling pattern to the encapsulation body 31, thereby forming an exposed electrode pad on the encapsulation body 31 211 openings.

Step 5: As shown in FIG. 5 e , at least one rewiring layer, such as a rewiring layer 41 , is formed on the encapsulation body 31 to rearrange positions of the electrodes of the chip 21 . Each redistribution layer is a patterned metal layer, and two connected redistribution layers are electrically connected to each other, wherein the bottommost redistribution layer is electrically connected to the electrode pad 211 . The specific steps of forming the first redistribution layer on the encapsulation body 31 may include:

Step 51 a : forming a metal layer on the encapsulation body 31 , the metal layer includes at least one layer of metal, and the metal layer is electrically connected to the electrode pad 211 through the opening on the encapsulation body 31 .

Step 52a: Form a layer of photoresist on the surface of the metal layer formed in step 51.

Step 53a: Correct the pattern to be exposed according to the position data, so that the corrected exposure pattern matches the position of the electrode pad, and expose the photoresist according to the corrected exposure pattern to obtain a pattern layer of photoresist.

Step 54 a : using the patterned photoresist layer as a mask, etching the metal layer and removing the photoresist layer to form the first secondary wiring layer.

In addition, the specific steps of forming the first redistribution layer on the encapsulation body 31 may also include:

Step 51b: forming a metal layer on the encapsulation body 31 , the metal layer includes at least one layer of metal, and the metal layer is electrically connected to the electrode pad 211 through the opening on the encapsulation body 31 .

Step 52b: Form a layer of photoresist on the surface of the metal layer formed in step 51.

Step 53b: Correct the pattern to be exposed according to the position data, so that the corrected exposure pattern matches the position of the electrode pad, and expose the photoresist according to the corrected exposure pattern to obtain a pattern layer of photoresist.

Step 54b: using the patterned photoresist layer as a mask, performing electroplating on the metal layer to form a patterned electroplating layer, and then removing the photoresist layer,

Step 55b: Etching away the part of the metal layer exposed by the electroplating layer to form the first redistribution layer.

It should be noted that the patterns to be exposed in steps 53a and 53b are preset patterns for mapping onto the photoresist layer. The graphics can also be the laser direct imaging graphics scanned onto the photoresist by a laser direct imaging machine, and correcting the graphics to be exposed according to the position data refers to: acquiring the chip 21 mounted on the packaging carrier 11 according to the position data Offset (the deviation between the actual mounting position of the chip 21 and the preset mounting position), and after obtaining the offset, the corresponding position of the pattern to be exposed is shifted, so that the image is mapped on the photolithography The position of the exposure pattern on the glue matches the position of the electrode pad 211 of the chip 21 more closely, which improves the alignment of the redistribution layer relative to the electrode pad 211 .

Using negatives to draw exposure patterns, and then transferring the exposure patterns on the negatives to photoresists through images is complicated in process and low in production efficiency. Therefore, in order to simplify the process and improve efficiency, in this embodiment, a laser direct imaging machine is used to directly form the exposure pattern. The pattern to be exposed is preset in the laser direct imaging machine, and the laser direct imaging machine corrects the pattern to be exposed according to the position data, and directly scans the corrected exposure pattern imaging on the photoresist to obtain the patterned photoresist layer.

Step 6: A solder layer (not marked in FIG. 5e ) is formed on the surface of the topmost redistribution layer among the redistribution layers formed in step 5, and the chip 21 is connected to the outside through the solder layer. External can refer to other devices or printed circuit boards, etc.

Step 7: After step 6 is completed, remove the packaging substrate 112, and cut the encapsulation body 31 and the insulating layer 113 along a preset cutting line, so as to form at least one insulating material covered in step 3. The chip package structure is shown in Figure 5e.

In addition, the present invention also provides a chip packaging structure formed by the chip packaging process according to the embodiment of the present invention, and the structure may be as shown in FIG. 5e.

In the chip packaging process provided by the present invention, after the chip 21 is mounted, the position data of the electrode pad 211 on the chip is obtained and stored, and then the position of the chip pad 211 is positioned according to the obtained position data to package The body 31 is opened to realize the extraction of chip electrodes. Therefore, in the chip packaging process provided by the present invention, the deviation when mounting the chip 21 will not affect the reliability of the package. For example, as shown in Figure 5a, when the second chip 21 of the first row and the third chip 21 of the second row are mounted on the packaging carrier 11, they all deviate from the predetermined mounting position, then the chip 21 The electrode pad 211 also deviates from the preset position. However, since the position data of the electrode pad 211 obtained in step 2 is obtained after the chip 21 is mounted, when the encapsulation 31 is opened in step 4, according to the position data and the positioning mark The position of the electrode pad 211 can be accurately positioned, so that the electrode terminal of the chip 21 can be exposed outside the encapsulation body 31 , and then electrically connected to the outside through the redistribution layer. It can be seen that the chip packaging structure formed by adopting the chip packaging process provided by the present invention will not be short-circuited or disconnected, and thus has high packaging reliability.

In addition, in the chip packaging process provided by the present invention, before the electrodes of the chip 21 are drawn out, the encapsulation body 31 for protecting the chip is formed first, and the electrodes of the chip 21 are drawn out to the outside through the rewiring layer 41 on the encapsulation body 21. Electrical connection, unlike the existing flip-chip process, which needs to lead the electrodes of the chip to the lead frame through conductive bumps. Therefore, the chip packaging process provided by the present invention does not need to be used for the bottom filling process, the process is simple and the cost is low, and because there is no need to use conductive bumps to electrically connect with the lead frame, the chip packaging process provided by the present invention is suitable for ultra-fine spacing. The chip packaging of the electrode terminals is conducive to improving the integration of the packaged chips.

It can be seen from the above that in the chip packaging process provided by the present invention, after the chip is mounted on the packaging carrier, first obtain the position data of the electrode pads on the chip, and then use the obtained position data of the electrode pads to package the A rewiring layer is formed on the package of the chip to rearrange the electrodes of the chip. Therefore, the rewiring layer formed has a higher degree of direct alignment with the chip, and the packaging process is simple. Through the The packaging structure formed by the process has low manufacturing cost and high reliability and integration.

Embodiments according to the present invention are described above, and these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (21)

1. a kind of chip package process, it is characterised in that include：

At least chip piece is mounted on package carrier in active face-up mode, is provided with the active face of the chip Electrode pad；

The position data of the electrode pad is obtained, and stores the position data：

According to the position data, at least formed on the encapsulated member of the chip one layer of rewiring layer for encapsulating, with weight Newly arrange the electrode position of the chip.

2. chip package process according to claim 1, it is characterised in that ground floor institute is formed on the encapsulated member The step of stating rewiring layer includes：

Layer of metal layer is formed on the encapsulated member, the metal level at least includes layer of metal,

One layer of photoresist is formed in the layer on surface of metal,

Exposure figure is treated according to the position data to be modified so that revised exposure figure and the electrode pad Position matches, and the photoresist is exposed according to revised exposure figure, to obtain the photoresist layer of patterning,

Photoresist layer with the patterning removes the photoresist layer, with shape as mask after being etched to the metal level Into the ground floor from wiring layer.

3. chip package process according to claim 1, it is characterised in that ground floor institute is formed on the encapsulated member The step of stating rewiring layer includes：

Metal level is formed on the encapsulated member,

One layer of photoresist is formed in the layer on surface of metal,

Exposure figure is treated according to the position data to be modified so that revised exposure figure and the electrode pad Position matches, and the photoresist is exposed according to revised exposure figure, to obtain the photoresist layer of patterning,

Photoresist layer with the patterning is electroplated as mask on the metal level, to form the electrodeposited coating of patterning, Then the photoresist layer is removed,

Etch away by the metal level of the electrodeposited coating exposed part, to form the ground floor layer is rerouted.

4. the chip package process according to Claims 2 or 3, it is characterised in that

The figure to be exposed is the figure to be exposed in laser direct imaging machine, and the laser direct imaging machine is according to institute's rheme Put after data carry out correcting to the figure to be exposed, and by the direct scanning imagery of revised exposure figure in the photoetching On glue, to obtain the photoresist layer of the patterning.

5. chip package process according to claim 4, it is characterised in that also include, in top the table of layer is rerouted Face forms weld layer, and the chip is communicated with the outside by the weld layer.

6. chip package process according to claim 1, it is characterised in that also include：The encapsulated member is formed, and in shape The encapsulated member is set to expose the electrode pad into before the rewiring layer.

7. chip package process according to claim 6, it is characterised in that before the position data is obtained, and The chip attachment is formed into the encapsulated member after the package carrier, and through the visual electrode weldering of the encapsulated member Disk.

8. chip package process according to claim 7, it is characterised in that encapsulate the core with transparent insulant Piece, to form the encapsulated member.

9. chip package process according to claim 6, it is characterised in that form institute after the position data is obtained State encapsulated member.

10. the chip package process according to claim 7 or 9, it is characterised in that the root before the rewiring layer is formed Opening process is carried out to the encapsulated member according to the position data, to expose the electrode pad.

11. chip package process according to claim 1, it is characterised in that positioning mark is provided with the package carrier Note.

The position data characterizes the relatively described specifically labelled relative position of the electrode pad.

12. chip package process according to claim 5, it is characterised in that the package carrier includes base plate for packaging and position Insulating barrier on the base plate for packaging, after the weld layer is formed, removes the base plate for packaging, and along presetting Cutting Road cuts the encapsulated member and insulating barrier, to form at least one chip-packaging structure being coated by an insulating material.

13. chip package process according to claim 1, it is characterised in that the method positioned by optical scanning is obtained The position data.

14. chip package process according to claim 13, it is characterised in that the method positioned by optical scanning is obtained The step of position data, includes：

Color or shape on the profile of all chips are highlighted, the contour images of the chip are then obtained, it is finally right The contour images carry out image procossing to obtain the position data；

Or, color or shape on all electrode pad central points are highlighted, then obtain all electrode pads Central point constitute scattergram picture, finally the scattergram picture is carried out image procossing to obtain the position data.

15. chip package process according to claim 1, it is characterised in that also include, by the chip attachment in institute Before stating package carrier, electric conductor is formed on the electrode pad,

After the encapsulated member is carried out into opening process, the electric conductor is exposed by the encapsulated member.

16. chip package process according to claim 15, it is characterised in that the electric conductor be copper ball, the copper ball Contact and electrically connect with the electrode pad.

17. chip package process according to claim 1, it is characterised in that also include, by the chip attachment in institute Before stating package carrier, telltale mark described at least two is formed on the package carrier, for determining a coordinate axess,

The relatively described specifically labelled relative position of the electrode pad is position of the electrode pad in the coordinate axess.

18. chip package process according to claim 17, it is characterised in that the telltale mark is location hole or is The pad of filled circles.

19. chip package process according to claim 10, it is characterised in that the process that is open is carried out to the encapsulated member Step includes：

According to the position data and the telltale mark, the position that the electrode pad is located is oriented,

Opening process is carried out to the encapsulated member using laser beam at the position that the electrode pad is located, to remove the electricity The insulant on the pad of pole.

20. chip package process according to claim 1, it is characterised in that using laser drilling machine to the encapsulated member The opening process is carried out, the step of opening is processed is carried out to the encapsulated member to be included：

The laser drilling machine according to position data amendment hole pattern to be drilled, and according to the revised drillhole pattern pair The encapsulated member is drilled, and the revised drillhole pattern is transferred on the encapsulated member, so as in the encapsulating The opening of the exposed electrode pad is formed on body.

Chip-packaging structure manufactured by a kind of 21. chip package process according to claim 1.