CN106601160B - Refresh rate conversion device and method and display device - Google Patents
Refresh rate conversion device and method and display device Download PDFInfo
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Abstract
The application discloses a refresh rate conversion device, a method and a display device, wherein the refresh rate conversion device comprises: the device comprises a first conversion module, a first storage module, a filtering module, a storage control module, a second storage module, a reading module and a second conversion module. The first storage module is used for caching the image data across clock domains and sending a full-writing indication when caching a preset amount of the image data; the filtering module is connected between the first conversion module and the first storage module, and is used for writing the image data from the first conversion module into the first storage module and suspending writing the image data into the first storage module when receiving a full indication from the first storage module. The refresh rate conversion device, the refresh rate conversion method and the display device write one frame of picture into the frame buffer by using multi-frame time, thereby effectively preventing data written into the frame buffer from missing.
Description
Technical Field
The embodiment of the invention relates to a liquid crystal display technology, in particular to a refresh rate conversion device, a refresh rate conversion method and a display device.
Background
In the field of liquid crystal panel testing, such a situation is often encountered, and a certain liquid crystal panel needs to be driven by a high refresh rate, however, the output capability of a test signal source is limited, and the expected refresh rate output requirement cannot be met, and at this time, the signal refresh rate needs to be improved. The refresh rate conversion device of the prior art is realized by a control chip and an external high-speed memory.
However, with the increasing resolution of the liquid crystal panel, the data throughput of the external high speed memory is limited, and the data stream is likely to cause data overflow when being written into the fifo buffer, so that the input video signal cannot be written into the frame buffer via the fifo buffer, and the data written into the frame buffer is lost, thereby causing the output video signal to be abnormal, as shown in fig. 1.
Fig. 2 shows a schematic block diagram of a refresh rate conversion apparatus according to the prior art, the refresh rate conversion apparatus 20 comprising: a video signal conversion module 201, a first-in first-out buffer 202, an external high-speed memory controller 203, an external high-speed memory 204, a frame data reading module 205, and an RGB data conversion module 206. The refresh rate conversion device 20 receives video signals in real time and converts the video signals into output signals, which is suitable for processing various dynamic videos and static images, but with the increasing resolution of the liquid crystal panel, the data throughput rate of the external high speed memory is limited, and when data streams are written into the fifo 202, data overflow is easily caused, i.e. the input video signals are not as good as the input video signals are written into the external high speed memory 204 through the fifo 202, and the data written into the external high speed memory 204 is lost, as shown in fig. 1, so that the output video signals are abnormal, which causes the display of the liquid crystal panel to be different.
Disclosure of Invention
In view of the above, at least one object of the embodiments of the present invention is to write a frame into a frame buffer by using multi-frame time, so as to effectively prevent data written into the frame buffer from missing.
According to a first aspect of the present invention, there is provided a refresh rate conversion apparatus, comprising: the first conversion module is used for generating corresponding image data according to the video signal of the first frequency; the first storage module is used for caching the image data across clock domains and sending a full-writing instruction when caching a preset amount of the image data; the filtering module is connected between the first conversion module and the first storage module and used for writing the image data from the first conversion module into the first storage module and suspending writing the image data into the first storage module when a full indication from the first storage module is received; the storage control module is used for reading the cached image data from the first storage module and writing the image data into the second storage module; the second storage module is used for caching the image data; a reading module for reading the image data from the second storage module through the storage control module at a second frequency; and the second conversion module is used for generating a corresponding video signal according to the image data read by the reading module, wherein the first frequency is different from the second frequency.
Further, the filtration module comprises: a start position determination unit for determining a start position for the current frame image data from the first conversion module; a writing unit configured to write the current frame image data from the first conversion module to the first storage module from the start position determined by the start position determination unit; and the writing control unit is used for determining an end position when the full writing indication from the first storage module is received, and controlling the writing unit to stop providing the current frame image data after the end position until the writing unit receives the next frame image data.
Further, the start position determining unit is configured to determine whether the current frame image data is different from the previous frame image data, if so, use a predetermined position in the current frame image data as the start position, otherwise, use a position in the current frame image data corresponding to the end position determined by the write control unit as the start position.
Further, the write control unit is further configured to control the write unit to stop providing the image data to the first storage module until the start position determination unit determines that the image data different from the current frame image data is received, in a case where the first storage module buffers the image data of one frame across clock domains.
Further, the first storage module includes an asynchronous first-in first-out buffer FIFO.
According to a second aspect of the present invention, there is provided a display device characterized by comprising a refresh rate conversion device provided according to the first aspect of the present invention.
According to a third aspect of the present invention, there is provided a refresh rate conversion method, comprising: generating corresponding image data according to the video signal of the first frequency; caching the image data by using a first storage module across clock domains, and suspending writing the image data into the first storage module when receiving a full-write indication from the first storage module; reading the cached image data from the first storage module and writing the image data into a second storage module, and reading the image data from the second storage module at a second frequency; and generating a corresponding video signal according to the image data read at a second frequency, wherein the first frequency is different from the second frequency, and the first storage module sends a full-writing indication when a preset amount of the image data is cached.
Further, the caching, by the first storage module, the image data across clock domains and suspending writing of the image data to the first storage module when a full indication from the first storage module is received includes: determining a starting position for the current frame image data; writing the current frame image data into the first storage module from the starting position; when the full indication from the first storage module is received, determining an end position, and stopping providing the current frame image data after the end position to the first storage module until receiving the next frame image data.
Further, the determining a starting position for the current frame image data comprises: under the condition that the current frame image data is different from the previous frame image data, taking a preset position in the current frame image data as an initial position; and under the condition that the current frame image data is the same as the previous frame image data, taking the position corresponding to the end position in the current frame image data as a starting position.
Further, the refresh rate conversion method further includes: under the condition that the first storage module caches image data of one frame across clock domains, the current frame image data is not provided for the first storage module until image data different from the current frame image data is received.
In the embodiment of the invention, the process of data filtering processing is added on the basis of the prior art. A complete frame of picture is written into the second storage module by using multi-frame time, so that only part of data of the frame of picture needs to be acquired in each frame time and written into the second storage module through the first storage module, and the rest of data is shielded, thereby effectively preventing the overflow of the data written into the first storage module and the loss of the data written into the second storage module, and reducing the abnormal condition of the output video signal.
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The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 shows a signal timing diagram of a refresh rate conversion apparatus according to the prior art;
FIG. 2 shows a schematic block diagram of a refresh rate conversion apparatus according to the prior art;
FIG. 3 shows a schematic block diagram of a refresh rate conversion apparatus according to an embodiment of the present invention;
FIG. 4 shows a schematic block diagram of a filtering module according to an embodiment of the invention;
FIG. 5 shows a schematic block diagram of a display device according to an embodiment of the invention;
FIG. 6 shows a flow diagram of a refresh rate conversion method according to an embodiment of the invention;
FIGS. 7a, 7b and 7c are schematic diagrams illustrating a process of writing image data into a first storage module by a filtering module according to an embodiment of the present invention;
FIG. 8a, FIG. 8b and FIG. 8c are timing diagrams illustrating the buffering of image data when the first storage module is an asynchronous FIFO buffer according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without inventive faculty, are intended to be within the scope of the disclosure.
The flowcharts and block diagrams in the figures illustrate the possible architectures, functions, and operations of the methods, systems, and apparatuses according to the embodiments of the present invention, and the blocks in the flowcharts and block diagrams may represent modules, program segments, or code segments only, which are executable instructions for implementing specified logical functions. It should also be noted that the executable instructions that implement the specified logical functions may be recombined to create new modules and program segments. The blocks of the drawings, and the order of the blocks, are thus provided to better illustrate the processes and steps of the embodiments and should not be taken as limiting the invention itself.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 3 shows a schematic block diagram of a refresh rate conversion apparatus according to an embodiment of the present invention, the refresh rate conversion apparatus 30 including: a first conversion module 301, a filtering module 307, a first storage module 302, a storage control module 303, a second storage module 304, a reading module 305, and a second conversion module 306.
The first conversion module 301 is configured to generate corresponding image data, such as 24-bit rgb data, according to the video signal with the first frequency. To provide an example, the input video signal is 60HZ, and needs to be converted by the first conversion module 301 to generate an RGB data stream which is easy to process. The RGB color scheme is a color standard in the industry, and various colors are obtained by changing three color channels of red (R), green (G) and blue (B) and superimposing them on each other. By calculation, 256 levels of RGB colors can combine to form about 1678 thousands of colors, i.e., 256 × 256 × 16777216. Also commonly referred to simply as 1600 or million. The first conversion module 301 can convert the 60HZ video signal into 24-bit RGB data, the 24-bit RGB data uses 24 bits to represent one pixel, and the RGB components are all represented by 8 bits and have a value range of 0-255.
The first storage module 302 is configured to cache the image data across clock domains, and issue a full indication when a predetermined amount of the image data is cached. The first memory module 302 may be an asynchronous first-in-first-out buffer FIFO. Since the filtering module 307 needs to be closely matched with the first storage module 302, the following description will be made with reference to fig. 8a, 8b, and 8c to illustrate a timing diagram for buffering image data when the first storage module 302 is an asynchronous FIFO, and the detailed description will not be repeated herein.
The filtering module 307 is connected between the first converting module 301 and the first storing module 302, and is configured to write the image data from the first converting module 301 to the first storing module 302, and suspend writing the image data to the first storing module 302 when receiving a full indication from the first storing module 302. Because the static video signal appears as an independent picture when being output, and a time margin is left for switching between two adjacent pictures, that is, the content of each frame is the same during the stay period of the output picture, a frame of picture can be written into the frame buffer by using multi-frame time, so that only a part of data of the frame of picture needs to be acquired in each frame time and written into the second storage module 304 through the first storage module 302. For example, according to the above-mentioned 24-bit RGB data, the filtering module 307 needs to first determine whether the current frame data and the previous frame data of the received 24-bit RGB data are the same. If not, the filtering module 307 sends the current frame data to the first storage module 302 from a predetermined position, and when the full indication of the first storage module 302 is obtained, the filtering module 307 determines an end position and stops providing the current frame data after the end position to the first storage module 302; if the current frame data is the same as the current frame data, the filtering module 307 provides the current frame data to the first storage module 302 from a position corresponding to the end position, when the full indication of the first storage module 302 is obtained, the filtering module 307 updates the end position, and stops providing the current frame data after the end position to the first storage module 302. In the case where the first storage module 302 buffers a complete frame of image data across clock domains, the filtering module 307 does not provide the current frame of data to the first storage module 302 until the next frame of data of the received 24-bit RGB data is different from the current frame of data. Of course, the image data is not limited to the 24-bit RGB data, and may be image data of another format.
The storage control module 303 is used for reading the buffered image data from the first storage module 302 and writing the image data into the second storage module 304. The storage control module 303 may be an external high-speed storage controller.
The second storage module 304 is used for caching the image data. The second memory module 304 may be an external high speed memory, such as a second generation double speed synchronous dynamic random access memory DDR2 SDRAM. The second storage module 304 mainly functions as a frame buffer and can store one frame of image data. In some embodiments, the second storage module 304 may be configured as a storage space for two frames of image data.
The reading module 305 is configured to read the image data from the second storage module 304 through the storage control module 303 at a second frequency. For example, the video signal input to the first conversion module 301 is 60HZ, and the reading module 305 may read the image data from the second storage module 304 at a refresh rate of 120 HZ. Of course, the video signal input to the first conversion module 301 may also be 120HZ, and the reading module 305 may read the image data from the second storage module 304 at a refresh rate of 60 HZ. In some embodiments, the second storage module 304 is configured as a storage space for one frame of image data, and the reading module 305 may read the image data at a certain frequency during the process of buffering the image data by the second storage module 304. In some preferred embodiments, the second storage module 304 may be configured as a storage space for two frames of image data, such as an a storage area and a B storage area, and the reading module 305 reads image data from the a storage area at a certain frequency when the a storage area stores one frame of image data, and the storage control module 303 reads image data different from the previous frame from the first storage module 302 and writes to the B storage area when the filtering module 307 receives image data different from the previous frame, and the reading module 305 reads image data from the B storage area at a certain frequency when the B storage area stores one frame of image data again. Therefore, a complete frame of picture is displayed every time, and the user experience can be improved.
The second conversion module 306 is configured to generate a corresponding video signal according to the image data read by the reading module 305.
Typically, the first frequency is different from the second frequency, and the first frequency may be greater or less than the second frequency. The first conversion module 301, the filtering module 307, the first storage module 302, the storage control module 303, the reading module 305, and the second conversion module 306 may be implemented by a field programmable gate array FPGA.
Fig. 4 shows a schematic block diagram of a filtering module according to an embodiment of the invention, the filtering module 307 comprising: a home position determination unit 3071, a writing unit 3072, and a writing control unit 3073.
The start position determination unit 3071 is configured to determine a start position for the current frame image data from the first conversion module. In some optional embodiments, the start position determining unit 3071 is configured to determine whether the current frame image data is the same as the previous frame image data, where the current frame image data is different from the previous frame image data, the start position determining unit 3071 takes a predetermined position in the current frame image data as a start position, and where the current frame image data is the same as the previous frame image data, the start position determining unit 3071 takes a position in the current frame image data corresponding to the end position determined by the write control unit 3073 as a start position.
The writing unit 3072 is configured to write the current frame image data from the first conversion module to the first storage module 302 from the start position determined by the start position determination unit 3071.
The writing control unit 3073 is configured to determine an end position when receiving the full write indication from the first storage module 302, and control the writing unit 3072 to stop providing the current frame image data after the end position until the writing unit 3072 receives the next frame image data. In some embodiments, the write control unit 3073 may be further configured to control the write unit 3072 to stop providing the image data to the first storage module 302 in a case that the first storage module 302 buffers the image data of one frame across clock domains until the start position determination unit 3071 determines that the image data different from the image data of the current frame is received.
As an example, fig. 7a, 7b and 7c are schematic diagrams illustrating a process of writing image data into the first storage module by the filtering module according to an embodiment of the present invention, such as the first frame data shown in fig. 7a, each small square represents data of one pixel, the filtering module 307 writes the current frame data into the first storage module 302 from the start position a of the frame until the first storage module 302 is full, sends a full indication to the filtering module 307, the filtering module 307 records the position b corresponding to this time, and stops writing data into the first storage module 302, and discards image data remaining after the position b.
FIGS. 8a, 8b and 8c are timing diagrams illustrating the buffering of image data when the first storage module 302 is an asynchronous FIFO buffer according to an embodiment of the present invention. As shown in fig. 8a, when the FIFO full indication is 0 and the FIFO write enable is 1, the image data may be written into the FIFO, corresponding to the data between a and b in fig. 7a being valid data, and when the FIFO full indication is 1, the FIFO write enable is set to 0, and the filter module 307 masks the remaining data of the current frame and does not write into the FIFO. Similarly, as shown in the second frame data in fig. 7b, the filtering module 307 discards the data from the starting position a of the picture to the position b of the first frame record, writes the current frame data of the image data into the first storage module 302 from the position b, sets the full indication to the first storage module 302, sends the full indication to the filtering module 307, and the filtering module 307 records the position c corresponding to the moment, and stops writing the data into the first storage module 302, and discards the data remaining after the position c. As shown in fig. 8b, the FIFO full indication is 0, the FIFO write enable is 0, and at this time, data is not written into the FIFO and is masked by the filtering module 307 until the position b of the first frame record, the FIFO write enable is set to 1, corresponding to that the data between b and c in fig. 7b is valid data, when the FIFO full indication is 1, the FIFO write enable is 0, and the filtering module 307 masks the remaining data of the current frame and does not write into the FIFO. Fig. 7c shows the last frame data used by the filtering module in writing the image data into the first storage module, and assuming that the end position of the previous frame record is position d, the filtering module 307 discards the data between the start position a of the picture and the position d of the previous frame record, and writes the current frame data of the image data into the first storage module 302 from the position d until the last position e of the current frame. As shown in fig. 8c, the FIFO full indication is always 0, the FIFO write enable is set to 1 at position d corresponding to the last frame recording, the filtering module 307 masks all data before position d, and only valid data corresponding to the interval between d and e in fig. 7c is written into the FIFO. In the example, the predetermined position is the starting position a of one frame of image data, however, it should be noted that any other position may be selected to achieve the purpose of the embodiment of the present invention, except that in this case, after the filtering module 307 writes the last bit of data of the current frame into the first storage module 302, if a full indication sent by the first storage module 302 is not received, the unwritten image data may be continuously written into the first storage module 302 from the last data position back to the starting position. In some embodiments, the filtering module 307 writes the image data to the first storage module 302 in units of pixels.
Different from the refresh rate conversion apparatus 20 in the prior art, the refresh rate conversion apparatus 30 according to the embodiment of the present invention adds the filtering module 307 to the refresh rate conversion apparatus 20, and can perform data filtering processing. Because the static video signal appears as an independent picture when being output, and a time margin is left for switching between two adjacent pictures, that is, the content of each frame is the same during the stay period of the output picture, a complete picture can be written into the second storage module 304 by using multi-frame time, so that each frame time only needs to acquire a part of data of a frame and write the data into the second storage module 304 through the first storage module 302, and the rest of data is shielded through the filtering module 307, thereby effectively preventing the overflow of the data. According to the embodiment of the invention, a complete static image can be captured by a multi-frame input video signal and written into the second storage module 304, then the reading module 305 reads frame data from the second storage module 304 at a refresh rate different from that of the input video signal, and finally the second conversion module 306 converts the data for output.
Fig. 5 shows a schematic block diagram of a display device according to an embodiment of the present invention, the display device 50 including: a refresh rate conversion device 30 and a display panel 501.
The refresh rate conversion apparatus 30 has been described in detail above with reference to fig. 3, and will not be described in detail here. In the display device 50, the refresh rate conversion device 30 is mainly configured to generate a video signal of a second frequency from the received video signal of the first frequency, and transmit the video signal of the second frequency to the display panel 501.
The display panel 501 is used for displaying images according to the video signal of the second frequency sent by the refresh rate conversion device 30.
Generally, the first frequency is different from the second frequency, and the first frequency may be greater than or less than the second frequency.
According to the display device provided by the embodiment of the invention, the data filtering module is added on the basis of the prior art. Because the static video signal is represented as an independent picture when being output, and a time margin is left between two adjacent pictures by switching, namely the content of each frame is the same during the stay period of the output picture, a complete picture can be written into the second storage module by using multi-frame time, so that only part of data of one frame of picture needs to be acquired in each frame time and written into the second storage module through the first storage module, and the rest of data is shielded, thereby effectively preventing the overflow of the data. The display device of the embodiment of the invention can capture a complete static image through a plurality of frames of input video signals and write the complete static image into the second storage module, then read frame data from the second storage module at a refresh rate different from that of the input video signals, and finally convert and output the data, wherein the whole refresh rate conversion process may consume tens of frames of time, namely, the switching of an output picture of the device has a delay of tens of milliseconds to hundreds of milliseconds compared with a signal source, and the delay is within an acceptable range, so that the display device of the embodiment can adapt to the requirements of refresh rate conversion under various static pictures.
FIG. 6 shows a flow diagram of a refresh rate conversion method according to an embodiment of the present invention, the method comprising:
in step S601, corresponding image data is generated from the video signal of the first frequency.
For example, the input video signal is 60HZ and needs to be converted to generate an RGB data stream that is easy to handle. The RGB color scheme is a color standard in the industry, and various colors are obtained by changing three color channels of red (R), green (G) and blue (B) and superimposing them on each other. By calculation, 256 levels of RGB colors can combine to form about 1678 thousands of colors, i.e., 256 × 256 × 16777216. Also commonly referred to simply as 1600 or million. As an example, a 60HZ video signal may be converted into 24bit RGB data, the 24bit RGB data representing one pixel using 24 bits, and the RGB components all represented by 8 bits, with values ranging from 0 to 255.
In step S602, a first storage module is used to cache the image data across clock domains, and when a write-full indication from the first storage module is received, writing of the image data into the first storage module is suspended.
In some cases, because the static video signal appears as an independent picture when being output, and a time margin is left for switching between two adjacent pictures, that is, the content of each frame is the same during the stay period of the output picture, a frame of picture can be written into the frame buffer by using multi-frame time, so that only a part of data of the frame of picture needs to be acquired in each frame time and written into the second storage module through the first storage module. For example, according to the 24-bit RGB data, it is first necessary to determine whether the current frame data and the previous frame data of the received 24-bit RGB data are the same. If the current frame data is different from the current frame data, sending the current frame data to the first storage module from a preset position, determining an end position when a full indication of the first storage module is obtained, and stopping providing the current frame data after the end position to the first storage module; and if the current frame data are the same as the current frame data, starting to provide the current frame data to the first storage module from the position corresponding to the end position, updating the end position when the full indication of the first storage module is obtained, and stopping providing the current frame data after the end position to the first storage module until the next frame of image data is received. The first storage module issues a full indication when a predetermined amount of the image data is cached. Under the condition that the first storage module caches one frame of image data across a clock domain, the current frame data is not provided for the first storage module until the next frame data of the received 24-bit RGB data is different from the current frame data. Of course, the image data is not limited to the 24-bit RGB data, and may be image data of another format. As an example, fig. 7a, 7b and 7c are schematic diagrams illustrating a process of writing image data into a first storage module by a filtering module according to an embodiment of the present invention, such as the first frame data shown in fig. 7a, where each small square represents data of one pixel, the current frame data of the image data is written into the first storage module from a start position a of a picture, a full indication is sent to a full indication setting of the first storage module, a position b corresponding to the current time is recorded, meanwhile, the data is stopped being written into the first storage module, and the data remaining after the position b is discarded. FIG. 8a, FIG. 8b and FIG. 8c are timing diagrams illustrating the buffering of image data when the first storage module is an asynchronous FIFO buffer according to an embodiment of the present invention. As shown in fig. 8a, when the FIFO full indication is 0 and the FIFO write enable is 1, data can be written into the FIFO, corresponding to the data between a and b in fig. 7a being valid data, and when the FIFO full indication is 1, the FIFO write enable is set to 0, and the remaining data of the current frame is masked and is not written into the FIFO. Similarly, as shown in fig. 7b, in the second frame data, data between the start position a of the picture and the position b recorded in the first frame is discarded, the current frame data of the image data is written into the first storage module from the position b, the full indication is sent to the first storage module until the full indication setting of the first storage module, the corresponding position c at this time is recorded, and meanwhile, the data is stopped being written into the first storage module, and the data left after the position c is discarded. As shown in fig. 8b, the FIFO full indication is 0, the FIFO write enable is 0, the data is masked and is not written into the FIFO until the position b of the first frame record, the FIFO write enable is set to 1, which corresponds to the data between b and c in fig. 7b being valid data, when the FIFO full indication is 1, the FIFO write enable is 0, the remaining data of the current frame is masked and is not written into the FIFO. Fig. 7c shows the last frame data used by the filtering module during the process of writing the image data into the first storage module, assuming that the end position of the previous frame record is position d, discarding the pixel data between the start position a of the picture and the position d of the previous frame record, and writing the current frame data of the image data into the first storage module from position d until the last position e of the current frame. As shown in fig. 8c, the FIFO full indication is always 0, the FIFO write enable is set to 1 at pixel position d corresponding to the last frame recording, the data before pixel position d is all masked, and only valid data corresponding to the interval between d and e in fig. 7c is written into the FIFO. In the example, the predetermined position is the start position a of one frame of image data, however, it should be noted that the purpose of the embodiment of the present invention can be achieved by selecting any other pixel position, but in this case, after writing the last bit of data of the current frame into the first storage module, if a full indication sent by the first storage module is not received, the unwritten image data can be continuously written into the first storage module from the last data position back to the start position.
In step S603, the buffered image data is read from the first storage module and written into a second storage module, and the image data is read from the second storage module at a second frequency. The second memory module may be an external high speed memory, such as a second generation double speed synchronous dynamic random access memory DDR2 SDRAM. The second storage module mainly plays a role of frame buffer and can store one frame of image data. In some embodiments, the second storage module may be configured as a storage space for two frames of image data.
In step S604, a corresponding video signal is generated from the image data read at the second frequency. For example, the input video signal is 60HZ, and one frame of image data can be read from the second memory module at a refresh rate of 120 HZ. Of course, the input video signal may also be 120HZ, and one frame of image data may be read from the second memory module at a refresh rate of 60 HZ. In some embodiments, the second storage module is configured as a storage space for one frame of image data, and the image data can be read at a certain frequency during the process of buffering the image data by the second storage module. In some preferred embodiments, the second storage module may be configured as a storage space for two frames of image data, such as an a storage area and a B storage area, and when the a storage area stores one frame of image data, image data is read from the a storage area at a certain frequency, when image data different from the previous frame is received, the image data different from the previous frame is written to the B storage area via the first storage module, and when the B storage area stores one frame of image data again, image data is read from the B storage area at a certain frequency. Therefore, a complete frame of picture is displayed every time, and the user experience can be improved.
Typically, the first frequency is different from the second frequency, and the first frequency may be greater or less than the second frequency.
Unlike the refresh rate conversion method of the prior art, the refresh rate conversion method according to the embodiment of the present invention adds a process of data filtering processing to the prior art. Because the static video signal is represented as an independent picture when being output, and a time margin is left between two adjacent pictures by switching, namely the content of each frame is the same during the stay period of the output picture, a complete picture can be written into the second storage module by using multi-frame time, so that only part of data of one frame of picture needs to be acquired in each frame time and written into the second storage module through the first storage module, and the rest of data is shielded, thereby effectively preventing the overflow of the data. According to the embodiment of the invention, a complete static image can be captured by a multi-frame input video signal and written into the second storage module, then frame data is read from the second storage module at a refresh rate different from that of the input video signal, and finally the data is converted and output.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (6)
1. A refresh rate conversion apparatus, comprising:
the first conversion module is used for generating corresponding image data according to the video signal of the first frequency;
the first storage module is used for caching the image data across clock domains and sending a full-writing instruction when caching a preset amount of the image data;
the filtering module is connected between the first conversion module and the first storage module and used for writing the image data from the first conversion module into the first storage module and suspending writing the image data into the first storage module when a full indication from the first storage module is received;
the storage control module is used for reading the cached image data from the first storage module and writing the image data into the second storage module;
the second storage module is used for caching the image data;
a reading module for reading the image data from the second storage module through the storage control module at a second frequency;
a second conversion module for generating a corresponding video signal according to the image data read by the reading module,
wherein the first frequency is different from the second frequency;
the filtration module includes:
a start position determination unit for determining a start position for the current frame image data from the first conversion module;
a writing unit configured to write the current frame image data from the first conversion module to the first storage module from the start position determined by the start position determination unit;
a write control unit for determining an end position when receiving the full indication from the first storage module, controlling the write unit to stop providing the current frame image data after the end position until the write unit receives the next frame image data,
the starting position determining unit is further configured to determine whether the current frame image data is different from the previous frame image data, if so, use a predetermined position in the current frame image data as the starting position, otherwise, use a position in the current frame image data corresponding to the ending position determined by the write control unit as the starting position.
2. The refresh rate conversion apparatus according to claim 1, wherein the write control unit is further configured to control the write unit to stop supplying the image data to the first storage module until the start position determination unit determines that the image data different from the current frame image data is received, in a case where the first storage module buffers the image data of one frame across clock domains.
3. The refresh rate conversion apparatus of claim 1, wherein the first storage module comprises an asynchronous first-in-first-out buffer FIFO.
4. A display device comprising the refresh rate conversion device according to any one of claim 1 to claim 3.
5. A refresh rate conversion method, comprising:
generating corresponding image data according to the video signal of the first frequency;
caching the image data by using a first storage module across clock domains, and suspending writing the image data into the first storage module when receiving a full-write indication from the first storage module;
reading the cached image data from the first storage module and writing the image data into a second storage module, and reading the image data from the second storage module at a second frequency;
generating a corresponding video signal from the image data read at the second frequency,
wherein the first frequency is different from the second frequency, and the first storage module sends out a full indication when caching a predetermined amount of the image data;
the caching, by the first storage module, the image data across clock domains and suspending writing of the image data to the first storage module when a full indication from the first storage module is received includes:
determining a starting position for the current frame image data;
writing the current frame image data into the first storage module from the starting position;
determining an end position when the full indication from a first storage module is received, stopping providing the current frame image data after the end position to the first storage module until a next frame image data is received,
the determining a starting position for the current frame image data comprises:
under the condition that the current frame image data is different from the previous frame image data, taking a preset position in the current frame image data as an initial position; and under the condition that the current frame image data is the same as the previous frame image data, taking the position corresponding to the end position in the current frame image data as a starting position.
6. The refresh rate conversion method according to claim 5, further comprising:
under the condition that the first storage module caches image data of one frame across clock domains, the current frame image data is not provided for the first storage module until image data different from the current frame image data is received.
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