CN106528920B - A kind of process mapping method cascading look-up table - Google Patents

Abstract

A kind of process mapping method cascading look-up table provided by the invention, by obtaining gate level circuit, the gate level circuit includes combinatorial logic unit, and look-up table mapping is carried out to combinatorial logic unit, look-up table after mapping is grouped, obtain basic logic unit, wherein basic logic unit includes at least one path, each path includes at least two look-up tables, one-to-one connection is carried out by quick hardwired between two look-up tables in each path, finally according to the logical connection information of look-up table in basic logic unit, logic level counting number is carried out to path.The method reduce the logic series in path, so that fpga chip be made to possess higher fmax.

Description

A Process Mapping Method for Cascading Lookup Tables

technical field

The invention relates to the technical field of integrated circuits, and in particular, to a process mapping method for cascading lookup tables.

Background technique

At present, in the application of FPGA (Field Programmable Gate Array, Field Programmable Gate Array), the integrated circuit is required to have a programmable or configurable interconnection network, and the logic gates are connected to each other through the configurable interconnection network as an independent chip Or the FPGA, which is the core part of the system, has been widely used in a large number of microelectronic devices.

With the continuous development of FPGA chips, traditional FPGA chips can only generate a simple K input look-up table (English: Look-Up-Table, LUT) when performing process mapping. hardwired. However, the prior art cannot effectively utilize the fast hard wiring, so that the fast hard wiring is regarded as a common wiring through a general wiring resource. There is usually at least one transmission device such as a strobe between ordinary windings. Since the FPGA chip has not been placed and routed after process mapping, the delay of each connection passing through the general routing resource is unknown.

It can be seen that in the prior art, since fast hard wiring is regarded as ordinary wiring, the fmax of the entire FPGA chip will be greatly reduced when estimating the delay of each path and determining the critical path by calculating the number of logic levels . Among them, the number of logic levels refers to the number of look-up tables that pass through a path. In the partial FPGA chip structure shown in Figure 1, a critical path composed of the input terminal A[0] to the output terminal O, the path's The number of logical stages is 2.

SUMMARY OF THE INVENTION

In order to solve the above problems and improve the transmission efficiency of the FPGA chip, the present application provides a process mapping method for cascading look-up tables. The method includes: by acquiring a gate-level circuit including a combinational logic unit, and performing a look-up table mapping on the combinational logic unit , group the mapped look-up tables to obtain a basic logic unit, the basic logic unit includes at least one path, each path includes at least two look-up tables, and the two look-up tables in each path are connected by fast hard wiring. One-to-one connection, and finally, according to the logical connection information of the look-up table in the basic logic unit, the path is counted by the logical level.

In an optional implementation, the method further includes: connecting different paths in the basic logic unit through common wiring.

In an optional implementation, according to the logical connection information of the look-up table in the basic logic unit, the path is counted by the number of logical stages. The logical progression of the path through a look-up table is a preset value. If the logical connection between the look-up tables is carried out through common wiring, the logic level of the path of the signal passing through a look-up table via the common wiring is 1.

In an optional implementation, the preset value is proportional to the length of the fast hardwire, and the preset value is less than one.

In a process mapping method for cascading lookup tables provided by the present application, by acquiring a gate-level circuit, the gate-level circuit includes a combinational logic unit, performing lookup table mapping on the combinational logic unit, grouping the mapped lookup tables, and acquiring Basic logic unit, wherein the basic logic unit includes at least one path, each path includes at least two look-up tables, and the two look-up tables in each path are connected one-to-one by fast hard wiring, and finally according to the basic logic unit Look up the logical connection information of the table, and count the logical stages of the path. This method reduces the number of logic stages in the path, thus enabling the FPGA chip to have a higher fmax.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

Fig. 1 is the partial structure schematic diagram of FPGA chip in the prior art;

2 is a flowchart of a process mapping method for cascading lookup tables provided by an embodiment of the present invention;

3 is a schematic structural diagram of a 10-to-1 AND gate unit in the prior art;

4A is a schematic structural diagram of a basic logic unit provided by an embodiment of the present invention;

4B is a schematic structural diagram of a 10-to-1 AND gate unit after mapping provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of the logic stages of FIG. 4B .

Detailed ways

The technical solutions of the present invention will be further described in detail below through the accompanying drawings and embodiments.

FIG. 2 is a flowchart of a process mapping method for cascading lookup tables according to an embodiment of the present invention. As shown in Figure 2, the method may include:

Step 210: Obtain a gate-level circuit, where the gate-level circuit includes a combinational logic unit.

In the synthesis and library mapping stage of the FPGA chip, the user circuit needs to be converted into a gate-level circuit. User circuits can be compiled using a hardware description language (verilog or VHDL). The user circuit compiled by using high-level hardware description language will become a low-level gate-level circuit after synthesis. The gate-level circuit can include at least one combinational logic unit, and the combinational logic unit can be an AND gate, an OR gate, and a NOT gate. and other units, as shown in Figure 3 is a 10-to-1 AND gate unit.

Step 220: Perform lookup table mapping on the combinational logic unit, group the mapped lookup tables, and obtain a basic logic unit. The basic logic unit includes at least one path, each path includes at least two lookup tables, and two in each path. One-to-one connection between lookup tables is fast hardwired.

A look-up table mapping is performed on at least one combinational logic unit in the obtained gate-level circuit, and a mapping netlist containing the look-up table is obtained. The FPGA chip can group and package the lookup tables into a basic logic unit according to the logical connection relationship of the mapping netlist or the distance between the lookup tables. The obtained basic logic unit may include at least one path, each path may include at least two look-up tables, and one-to-one connection between the two look-up tables in each path may be performed through fast hard wiring. As shown in FIG. 4A , the basic logic unit includes path A and path B, path A includes 3 look-up tables, path B includes 4 look-up tables, and the adjacent look-up tables in each path are fast hardwired (solid line in the figure) for one-to-one connection.

FIG. 4B is a schematic structural diagram of a 10-to-1 AND gate unit after mapping provided by an embodiment of the present invention. As shown in the figure, after the 10-to-1 AND gate unit is mapped, it can be cascade-connected by three lookup tables of LUT0, LUT2 and LUT4. LUT0 and LUT2 are connected by fast hardwire, and LUT2 and LUT4 are connected by fast hardwire. A[0]-A[9] are the input terminals, and O is the output terminal.

Optionally, the lookup table between paths A and B can be connected through common routing resources. In FIG. 4A , the connection between LUT0 and LUT1 or between LUT2 and LUT5 can be performed through common routing resources (dashed lines in the figure).

It should be noted that fast hard wiring can realize fast transmission of signals, while common wiring resources are composed of gates, which are characterized by improving the success rate of wiring and occupying a relatively small hardware area. It also takes time to connect the switch, therefore, common routing resources cannot transmit signals quickly.

In addition, the gate-level circuit may further include at least one sequential logic unit, and the sequential logic unit performs register mapping during the mapping process.

Step 230: Count the logical stages of the path according to the logical connection information of the lookup table in the basic logical unit.

According to the logical connection information of the look-up table in the basic logic unit obtained in step 220, such as the behavior characteristics of the input signal in the path, the path is counted by the logic level, which may specifically include: if the logical connection between the look-up tables is performed by fast hard wiring , the path logic level of the signal passing through a look-up table through fast hard wiring is a preset value, such as 0.2; The path logic level is 1.

Wherein, the number of logic stages of the fast hard wiring is smaller than that of the common winding, that is, the preset value is less than 1. The preset value is proportional to the length of the fast hardwire, that is to say, the longer the length of the fast hardwire between the lookup tables, the greater the preset value of the corresponding logic level.

In one example, the preset value is set to 0.2. FIG. 5 is a schematic diagram of the logic stages of FIG. 4B . In the figure, in the path of the signal from the input terminal A[3] to the output terminal O, since the signal is not fast hardwired before passing through LUT0, the number of logic stages on the path passing through LUT0 is 1; the signal from the output terminal of LUT0 The fast hard-wired from O1 to the output terminal O2 of LUT2, so the number of logic stages on the path through LUT2 is 0.2; the fast hard-wired from the output terminal O2 of LUT2 to the output terminal O of LUT4, Therefore, the number of logic levels on the path of LUT4 is 0.2, and by synthesizing the above logic levels, it can be known that in the logic path of A[3]->O, the total number of logic levels is 1.4.

The present invention provides a method for counting the number of logical stages of a cascaded look-up table. By acquiring a gate-level circuit, the gate-level circuit includes a combinational logic unit, performing a lookup table mapping on the combinational logic unit, and grouping the mapped lookup tables into groups. , obtain the basic logic unit, wherein the basic logic unit includes at least one path, each path includes at least two lookup tables, and the two lookup tables in each path are connected one-to-one by fast hard wiring, and finally according to the basic logic The logical connection information of the lookup table in the unit is used to count the logical stages of the path. This method reduces the number of logic stages in the path, thus enabling the FPGA chip to have a higher fmax.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be implemented in hardware, a software module executed by a processor, or a combination of the two. Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory, flash memory, read-only memory, erasable programmable read-only register (English: erasableprogrammable read-only memory, EPROM) memory, electrical Erasable programmable read-only memory (English: electrically erasable programmable read-only memory, EEPROM), hard disk, CD-ROM (English: compact disc read-only memory, CD-ROM) or any other form of storage well known in the art in the medium. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium may reside in an ASIC. Alternatively, the ASIC may be located in the user equipment. Of course, the processor and storage medium may also exist in the user equipment as discrete components.

Those skilled in the art should appreciate that, in one or more of the above examples, the functions described in the present invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

The specific embodiments described above further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of the present invention shall be included within the protection scope of the present invention.

Claims (4)

1. a process mapping method of cascade lookup table, is characterized in that, described method comprises: Obtaining a gate-level circuit, the gate-level circuit includes a combinational logic unit; Perform lookup table mapping on the combinational logic unit, group the mapped lookup tables, and obtain a basic logic unit, where the basic logic unit includes at least one path, and each path includes at least two of the lookup tables, so One-to-one connection between the two look-up tables in each path is performed by fast hard wiring; the logic level of the fast hard wiring is less than the logic level of the ordinary winding, that is, the preset value is less than 1; According to the logical connection information of the look-up table in the basic logical unit, the path is counted in logical stages. 2. The method according to claim 1, wherein the method further comprises: The different paths in the basic logic unit are connected by ordinary wiring. 3. The method according to claim 2, characterized in that, according to the logical connection information of the lookup table in the basic logic unit, the path is counted in logical stages, specifically: If the look-up tables are logically connected through the fast hard-wired, the number of logical stages of a path through which a signal passes through one of the look-up tables via the fast hard-wired is a preset value; If the look-up tables are logically connected through the common routing, the logic level of a path for a signal to pass through one of the look-up tables via the common routing is 1. 4 . The method according to claim 3 , wherein the preset value is proportional to the length of the fast hardwire, and the preset value is less than 1. 5 .