CN106505006A - A kind of preparation method of the MOS structure for oxide layer full performance test - Google Patents

Abstract

A kind of preparation method of MOS structure for oxide layer full performance test that the present invention is provided, the preparation method include：One silicon chip substrate is provided；Passivation layer is formed in silicon chip substrate front, and will passivation layer open oxide windows mouth；Test oxide layer is formed in the bottom of oxidation window, the thickness of the thickness less than passivation layer of oxide layer is tested；Front electrode is formed in silicon chip substrate front；Front electrode is performed etching process up to passivation layer, and the thickness of passivation layer is more than the thickness of the test oxide layer；Backplate is formed at the silicon chip substrate back side.The preparation method solves the problems, such as MOS structure etching injury side wall, and then makes test oxide layer that there is reliability and integrity so that C V measuring technologies are more accurate to the reliability of test oxide layer and the monitoring of integrity.

Description

A method for preparing a MOS structure for oxide layer full performance testing

technical field

The invention relates to the technical field of semiconductor device manufacturing technology, and more specifically, to a method for preparing a MOS structure used for full performance testing of an oxide layer.

Background technique

In the production and development of semiconductor integrated circuits and devices, the C-V test of the MOS structure is an extremely important process monitoring test method for the oxide layer, especially the gate oxide layer, and is used for the full performance test (integrity and reliability test) of the oxide layer. , is also an effective tool for device and circuit parameter analysis and reliability research.

MOS C-V technology includes: high-frequency capacitance-voltage test of MOS structure, quasi-static very low frequency CL-V test, transient CH-t test, etc., which can be used to measure effective charge and movable charge in oxide, semiconductor surface space charge The electrical properties of the oxide layer such as the minority carrier generation lifetime, surface recombination velocity, and trap density in the region are used to evaluate the reliability and stability of the oxide layer (gate oxide layer), devices, and circuits. Among them, the MOS structure is the most important structure used in the C-V test technology, but in the process of patterning the sample preparation process, the MOS structure will be affected by the etching process in the process, and damage will be formed on the side wall of the MOS structure, thereby introducing defects. , which interferes with the actual test results.

In the traditional C-V test MOS structure manufacturing process, the silicon substrate is first oxidized, an oxide layer of required thickness is formed on the front of the silicon substrate, and the back oxide layer is removed, and the front electrode is formed through a deposition process, such as metal aluminum Electrodes, the front dot-shaped electrodes are engraved by patterning techniques such as photolithography and etching processes, which are used for electrode contact during testing. Subsequent deposition forms the back metal electrode, and forms an ohmic contact through the necessary annealing process.

However, when this method is used to etch and form front dot electrodes, due to the characteristics of the etching process itself, there is a certain degree of over-etching, as shown in Figure 1. An oxide layer step is formed at the edge. Due to the corrosion of the etching solution, a large number of defects will be generated at the step, which will interfere with the later C-V test.

Contents of the invention

In order to solve the above-mentioned technical problems, the present invention provides a method for preparing a MOS structure for the full performance test of the oxide layer. The preparation method can solve the problem of etching and damaging the sidewall of the MOS structure, so that the test oxide layer has reliability and Integrity, making C-V testing technology more accurate in monitoring the reliability and integrity of the oxide layer.

To achieve the above object, the present invention provides the following technical solutions:

A kind of preparation method of the MOS structure that is used for oxide layer full performance test, described preparation method comprises:

providing a silicon wafer substrate;

forming a passivation layer on the front surface of the silicon wafer substrate, and opening an oxidation window of the passivation layer;

forming a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is smaller than the thickness of the passivation layer;

forming a front electrode on the front surface of the silicon wafer substrate;

Etching the front electrode up to the passivation layer, and the thickness of the passivation layer is greater than the thickness of the test oxide layer;

A back electrode is formed on the back of the silicon wafer substrate.

Preferably, in the above preparation method, forming a passivation layer on the front side of the silicon wafer substrate, and opening the oxidation window of the passivation layer includes:

Carrying out oxidation treatment on the silicon substrate, forming a passivation layer on the front and back of the silicon substrate, and removing the passivation layer on the back of the silicon substrate;

The oxidation window of the passivation layer is opened through photolithography and etching processes.

Preferably, in the above preparation method, forming a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer being smaller than the thickness of the passivation layer includes:

Oxidize the silicon wafer substrate again, form a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is smaller than the thickness of the passivation layer, and remove the back surface of the silicon wafer substrate oxide layer.

Preferably, in the above preparation method, the silicon wafer substrate is oxidized in the form of wet oxygen oxidation, dry oxygen oxidation or chlorine-doped oxidation.

Preferably, in the above preparation method, the shape and size of the oxidation window are set corresponding to the front test contact electrodes.

Preferably, in the above preparation method, the area of the oxidation window is not less than 1E-4cm ^-2 .

Preferably, in the above preparation method, the shape of the oxidation window is circular, square or polygonal.

Preferably, in the above preparation method, the front electrode is a doped polysilicon electrode or an aluminum electrode.

Preferably, in the above preparation method, the back electrode is a doped polysilicon electrode or an aluminum electrode.

It can be seen from the above technical solutions that the present invention provides a method for preparing a MOS structure for oxide layer full performance testing. The preparation method includes: providing a silicon wafer substrate; and open the oxidation window of the passivation layer; form a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is less than the thickness of the passivation layer; form a front electrode on the front side of the silicon wafer substrate; etch the front electrode Process until the passivation layer, and the thickness of the passivation layer is greater than the thickness of the test oxide layer; form a back electrode on the back of the silicon wafer substrate. The method is by first forming a passivation layer on the surface of the silicon wafer substrate, and opening the oxidation window, forming a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is less than the thickness of the passivation layer, that is to say, the test oxide layer There will be an oxide layer step between the passivation layer, and then the front electrode is formed, and the front electrode is etched to the passivation layer. In the process of etching the front electrode, when the passivation layer is etched, it is inevitable that the passivation layer will also be etched, but because the thickness of the passivation layer is greater than the thickness of the test oxide layer, when the front electrode is etched After the etching is completed and the passivation layer appears, it will not cause etching of the test oxide layer, thereby solving the problem of etching the side wall of the MOS structure, and making the test oxide layer reliable and complete, making the C-V test technology More accurate monitoring of the reliability and integrity of the test oxide layer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

FIG. 1 is a schematic diagram of a MOS structure applied in a C-V test technology in the prior art;

FIG. 2 is a schematic flow chart of a method for preparing a MOS structure for oxide layer full performance testing provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a MOS structure applied in a C-V test technology provided by an embodiment of the present invention;

4 is a schematic diagram of another MOS structure applied in the C-V test technology provided by the embodiment of the present invention;

5 is a schematic diagram of another MOS structure applied in the C-V test technology provided by the embodiment of the present invention;

6 is a schematic diagram of another MOS structure applied in the C-V test technology provided by the embodiment of the present invention;

7 is a schematic diagram of another MOS structure applied in the C-V test technology provided by the embodiment of the present invention;

FIG. 8 is a schematic diagram of another MOS structure applied in the C-V test technology provided by the embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

According to the background technology, in the C-V test technology, in the process of manufacturing the MOS structure, when etching to form the front dot electrodes, due to the characteristics of the etching process itself, there is a certain program of over-etching, as shown in Figure 1. When over-etching occurs, an oxide layer step will be formed at the edge of the front dot electrode. Due to the corrosion of the etching solution, a large number of defects will be generated at the step, which will interfere with the later C-V test.

In order to solve the above problems, an embodiment of the present invention provides a method for preparing a MOS structure for testing the full performance of an oxide layer, the preparation method comprising:

providing a silicon wafer substrate;

forming a passivation layer on the front surface of the silicon wafer substrate, and opening an oxidation window of the passivation layer;

forming a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is smaller than the thickness of the passivation layer;

forming a front electrode on the front surface of the silicon wafer substrate;

Etching the front electrode up to the passivation layer, and the thickness of the passivation layer is greater than the thickness of the test oxide layer;

A back electrode is formed on the back of the silicon wafer substrate.

The preparation method firstly forms a passivation layer on the surface of the silicon wafer substrate, and opens the oxidation window, forms a test oxide layer at the bottom of the oxidation window, and the thickness of the test oxide layer is smaller than the thickness of the passivation layer, that is to say, the test oxide There is an oxide layer step between the layer and the passivation layer, and then the front electrode is formed, and the front electrode is etched to the passivation layer. In the process of etching the front electrode, when the passivation layer is etched, it is inevitable that the passivation layer will also be etched, but because the thickness of the passivation layer is greater than the thickness of the test oxide layer, when the front electrode is etched After the etching is completed and the passivation layer appears, it will not cause etching of the test oxide layer, thereby solving the problem of etching the side wall of the MOS structure, and making the test oxide layer reliable and complete, making the C-V test technology More accurate monitoring of the reliability and integrity of the test oxide layer.

In order to describe the embodiments of the present invention more accurately, the embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings.

Referring to FIG. 2, FIG. 2 is a schematic flow chart of a method for preparing a MOS structure for oxide layer full performance testing provided by an embodiment of the present invention. The preparation method includes:

S201: Provide a silicon wafer substrate.

First, a silicon wafer substrate is provided, and the silicon wafer substrate is processed as a carrier for the test contact electrodes.

S202: forming a passivation layer on the front surface of the silicon wafer substrate, and opening the oxidation window of the passivation layer.

Referring to Fig. 3 and Fig. 4, as shown in Fig. 3, carry out oxidation treatment to silicon substrate 31, form passivation layer 32 on silicon substrate 31 front and back, remove the passivation layer of silicon substrate 31 back, Thus, the purpose of forming the passivation layer 32 on the front surface of the silicon substrate 31 can be achieved. As shown in FIG. 4 , the oxidation window 41 of the passivation layer 32 is opened by means of photolithography and etching. The oxidation window 41 is for subsequent formation of a test oxide layer at the bottom of the oxidation window 41 .

S203: Form a test oxide layer at the bottom of the oxidation window, the thickness of the test oxide layer is smaller than the thickness of the passivation layer.

Referring to FIG. 5, as shown in FIG. 5, the silicon wafer substrate 31 is oxidized again to form a test oxide layer 51 at the bottom of the oxidation window 41. The thickness of the test oxide layer 51 needs to be smaller than the thickness of the passivation layer 32, that is to say , when the front electrode is subsequently formed, when the front electrode is etched, since the thickness of the test oxide layer 51 is smaller than the thickness of the passivation layer 32, the test oxide layer 51 will not be damaged during the etching process, play a protective role.

S204: Forming a front electrode on the front surface of the silicon wafer substrate.

Referring to FIG. 6, as shown in FIG. 6, by depositing a metal layer or other conductive medium on the front side of the silicon wafer substrate 31, the entire front side of the silicon wafer substrate 31 will be covered with a metal layer or other conductive medium due to deposition of the process means, Therefore, the deposited silicon substrate 31 needs to be etched to form the front electrodes.

S205: Etching the front electrode up to the passivation layer, and the thickness of the passivation layer is greater than the thickness of the test oxide layer.

Referring to FIG. 7, as shown in FIG. 7, that is to say, the deposited silicon wafer substrate 31 is processed by means of photolithography and etching until the passivation layer 32 appears to form a positive test contact electrode. The etchant cannot be accurately controlled, so the passivation layer 32 will also be etched, but the thickness of the test oxide layer 51 is less than the thickness of the passivation layer 32, and finally it is only necessary to ensure that the thickness of the passivation layer 32 continues to be greater than the thickness of the passivation layer 32 after the etching is completed. Testing the thickness of the oxide layer 51 can protect the test oxide layer 51 , thereby solving the problem in the prior art that the oxide layer is damaged due to etching and a large number of oxide layer defects are generated.

S206: forming a back electrode on the back of the silicon substrate.

Referring to FIG. 8 , as shown in FIG. 8 , finally a back electrode 81 is formed on the back of the silicon wafer substrate 31 and annealed to form an ohmic contact, and the MOS structure is completed.

Optionally, in step 202 and step 203, the oxidation method for oxidizing the silicon wafer substrate includes but not limited to wet oxygen oxidation, dry oxygen oxidation, or chlorine-doped oxidation and other oxidation methods.

And the oxidation window opened in step S202 is set according to the actual situation, the area of the oxidation window corresponds to the area of the front test contact electrode, and the area of the oxidation window is not less than 1E-4cm ^-2 , the preferred moderate area is 2.5E-3cm ^-2 to 2.5E-1cm ^-2 , and the shape of the oxidation window includes but not limited to circular, square or polygonal geometric structures.

It should be noted that, in the above method, forming the front electrode and the back electrode includes but is not limited to aluminum electrodes or doped polysilicon electrodes or other metal electrodes.

Therefore, it can be seen from the above description that the preparation method firstly forms a passivation layer on the surface of the silicon wafer substrate, and opens the oxidation window, forms a test oxide layer at the bottom of the oxidation window, and the thickness of the test oxide layer is smaller than the thickness of the passivation layer. , That is to say, there is an oxide layer step between the test oxide layer and the passivation layer, then the front electrode is formed, and the front electrode is etched to reach the passivation layer. In the process of etching the front electrode, when the passivation layer is etched, it is inevitable that the passivation layer will also be etched, but because the thickness of the passivation layer is greater than the thickness of the test oxide layer, when the front electrode is etched After the etching is completed and the passivation layer appears, it will not cause etching of the test oxide layer, thereby solving the problem of etching the side wall of the MOS structure, and making the test oxide layer reliable and complete, making the C-V test technology More accurate monitoring of the reliability and integrity of the test oxide layer.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. a kind of preparation method of the MOS structure for oxide layer full performance test, it is characterised in that the preparation method bag Include：

One silicon chip substrate is provided；

Passivation layer is formed in the silicon chip substrate front, and layer open oxide windows mouth is passivated by described；

Test oxide layer is formed in the bottom of the oxidation window, the thickness of the test oxide layer is less than the thickness of the passivation layer Degree；

Front electrode is formed in the silicon chip substrate front；

The front electrode is performed etching process up to the passivation layer, and the thickness of the passivation layer is more than the test oxygen Change the thickness of layer；

Backplate is formed at the silicon chip substrate back side.

2. preparation method according to claim 1, it is characterised in that described form passivation in the silicon chip substrate front Layer, and the passivation layer open oxide windows mouth is included：

The silicon chip substrate is carried out oxidation processes, passivation layer is formed in the silicon chip substrate front and the back side, is removed the silicon The passivation layer of piece substrate back；

By photoetching and etching technics, the oxidation window of the passivation layer is opened.

3. preparation method according to claim 2, the bottom in the oxidation window form test oxide layer, described The thickness of test oxide layer includes less than the thickness of the passivation layer：

To the silicon chip substrate to be carried out oxidation processes again, test oxide layer is formed in the bottom of the oxidation window, described Thickness of the thickness of test oxide layer less than the passivation layer, and remove the oxide layer at the silicon chip substrate back side.

4. the preparation method according to any one of claim 2-3, it is characterised in that the silicon chip substrate carries out oxidation processes Mode of oxidizing be wet-oxygen oxidation or dry-oxygen oxidation or to mix oxychloride.

5. preparation method according to claim 1, it is characterised in that the shape of the oxidation window and size with just The corresponding setting of face test contact electrode.

6. preparation method according to claim 1, it is characterised in that the area of the oxidation window is not less than 1E-4cm^-2.

7. preparation method according to claim 1, it is characterised in that the oxidation window generally circular in shape or square or Polygon.

8. preparation method according to claim 1, it is characterised in that the front electrode is doped polycrystalline silicon electrode or aluminum Electrode.

9. preparation method according to claim 1, it is characterised in that the backplate is doped polycrystalline silicon electrode or aluminum Electrode.