CN106409840A - Thin film transistor array substrate, manufacturing method thereof and display panel - Google Patents

Abstract

The invention provides a thin film transistor array substrate, a manufacturing method thereof and a display panel. The thin film transistor array substrate comprises thin film transistors, wherein each thin film transistor is internally provided with an active layer composed of a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer, and the non-doped amorphous silicon layer is arranged between the corresponding carbon nanotube semiconductor layer and a source as well as a drain. Therefore, when the thin film transistor is turned on, electricity is mainly conducted by means of the carbon nanotube semiconductor layer in the active layer, and the carbon nanotube semiconductor layer has high electron mobility and forms a high ON-state current; and when the thin film transistor is turned off, a leakage current is mainly released by means of the non-doped amorphous silicon layer in the active layer, and the leakage current is small, thus the thin film transistor has a high switching current ratio.

Description

A kind of thin film transistor array substrate, its manufacturing method and display panel

technical field

The invention relates to the field of display technology, in particular to a thin film transistor array substrate, a manufacturing method thereof and a display panel.

Background technique

The demand for various display devices has increased with the rise of the global information society. Therefore, much effort has been devoted to the research and development of various flat display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminescent displays (ELDs), and vacuum fluorescent displays (VFDs).

Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology, and has been widely used in fields such as flat panel displays. In practical applications, the requirement for thin film transistors is to obtain a larger switching current ratio. Factors Affecting the On-Off Current Ratio The carrier mobility of the semiconductor material in the active layer of the thin-film transistor is one of the most important factors affecting the on-off current ratio in addition to the manufacturing process of the thin film transistor.

In the prior art, the material for forming the active layer in the thin film transistor is amorphous silicon or polysilicon. The preparation technology of amorphous silicon thin film transistors with amorphous silicon as the active layer is relatively mature, but in amorphous silicon thin film transistors, because the active layer usually contains a large number of dangling bonds, the mobility of carriers is very low. , resulting in a slower response speed of the thin film transistor. TFTs with polysilicon as the active layer have higher carrier mobility than TFTs with amorphous silicon as the active layer. The off-state current of the transistor is high.

Contents of the invention

In view of this, it is necessary to provide a thin film transistor array substrate, its manufacturing method and display panel to solve the problem that in the existing thin film transistors, the mobility of carriers in the active layer is low, resulting in a slow response speed of the thin film transistors. Slow, or the preparation cost is higher, the method is more complicated, and the off-state current is larger.

In order to achieve the above object, an embodiment of the present invention provides a thin film transistor array substrate, the thin film transistor array substrate includes a base substrate and a plurality of thin film transistors located on the base substrate, the thin film transistors include a substrate located on the base substrate Gate, gate insulating layer, source, drain and active layer on the top, the source and the drain are respectively in contact with the active layer, the active layer includes a carbon nanotube semiconductor layer and A non-doped amorphous silicon layer, the non-doped amorphous silicon layer is located between the carbon nanotube semiconductor layer and the source and drain.

The present invention also provides a display panel, the display panel includes a thin film transistor array substrate, the thin film transistor array substrate includes a base substrate and a plurality of thin film transistors located on the base substrate, the thin film transistors include A gate, a gate insulating layer, a source, a drain and an active layer on the base substrate, the source and the drain are respectively in contact with the active layer, and the active layer includes carbon nanotubes A semiconductor layer and a non-doped amorphous silicon layer, the non-doped amorphous silicon layer is located between the carbon nanotube semiconductor layer and the source and the drain.

The present invention also provides a method for manufacturing a thin film transistor array substrate, the method comprising:

providing a base substrate;

A plurality of thin film transistors are formed on the base substrate, and the thin film transistors include a gate and a gate insulating layer, a source, a drain and an active layer, and the source and the drain are connected to the active layer respectively. source layer contact, the active layer includes a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer, the non-doped amorphous silicon layer is located between the carbon nanotube semiconductor layer and the source and the drain between poles.

In the thin film transistor array substrate, its manufacturing method, and display panel provided by the embodiments of the present invention, an active layer composed of a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer is arranged in the thin film transistor, and the non-doped amorphous The silicon layer is disposed between the carbon nanotube semiconductor layer and the source and drain. In this way, when the thin film transistor is turned on, it mainly conducts electricity through the carbon nanotube semiconductor layer in the active layer. The carbon nanotube semiconductor layer has a higher electron mobility and forms a larger on-state current. When the thin film transistor is turned off, The leakage current is mainly released through the non-doped amorphous silicon layer in the active layer, which has a small leakage current, so that the thin film transistor has a high switching current ratio.

Description of drawings

FIG. 1 is a perspective view of a display device provided by a preferred embodiment of the present invention;

Fig. 2 is a partial sectional view shown at II-II place among Fig. 1;

3 to 6 are cross-sectional views during the manufacturing process of the thin film transistor array substrate provided by a preferred embodiment of the present invention.

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

As shown in FIG. 1 , FIG. 1 is a perspective view of a display device provided by a preferred embodiment of the present invention. The display device 100 includes a first substrate 10 , a second substrate 20 opposite to the first substrate 10 , and a liquid crystal layer 30 between the first substrate 10 and the second substrate 20 . The display device 100 further includes a display area 101 and a peripheral area 102 surrounding the display area 101 , the display area 101 is used to realize the display function of the display device.

In this embodiment, the first substrate is a thin film transistor array substrate, and the second substrate is a color filter substrate, but they are not limited thereto. In other embodiments, the first substrate can also be a color filter substrate. The optical filter substrate, the second substrate may also be a thin film transistor array substrate. Hereinafter, the first substrate is referred to as a thin film transistor array substrate.

Please refer to FIG. 2 at the same time. FIG. 2 is a partial cross-sectional view shown at II-II in FIG. 1 . The thin film transistor array substrate 10 includes a plurality of thin film transistors 11 , a base substrate 12 , a passivation layer 13 and a pixel electrode 14 . A plurality of thin film transistors 11 are located on the base substrate 12, the passivation layer 13 covers the thin film transistors 11 and the base substrate 12, and the pixel electrode 14 is arranged on the passivation layer 13 and is in contact with The thin film transistors 11 are electrically connected.

The thin film transistor 11 includes a gate 111, a gate insulating layer 112, a source 113, a drain 114 and an active layer 115, the gate 111 is arranged on the substrate 12, and the gate insulating layer 112 covers the gate 111 and the base substrate 12, the active layer 115 is located on the gate insulating layer 112 and correspondingly arranged above the gate 111, the source 113 and the The drain 114 is located on and in contact with the active layer 115 , and the source 113 and the drain 114 are respectively disposed at opposite ends of the active layer 115 .

The passivation layer 13 includes a contact hole 131, the contact hole 131 is located above the drain 114 and is arranged corresponding to the drain 114, and the pixel electrode 14 is connected to the drain through the contact hole 131. 114 is electrically connected. The TFT array substrate 10 further includes a common electrode layer (not shown) that is insulated from the pixel electrodes 14 .

The display device can be any product or component with display function such as LCD TV, liquid crystal display, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

In this embodiment, the base substrate 12 can be a rigid inorganic material that is transparent (such as glass, quartz, or the like) or opaque (such as a chip, ceramics, or the like), or can be made of plastic, rubber, polyester, etc. Flexible organic materials such as ester or polycarbonate.

In this embodiment, the material of the pixel electrode 14 is preferably a transparent conductive material, such as indium tin oxide, indium zinc oxide or the like.

The active layer 115 includes a carbon nanotube semiconductor layer 1151 and a non-doped amorphous silicon layer 1152, and the carbon nanotube semiconductor layer 1151 is located between the non-doped amorphous silicon layer 1152 and the gate insulating layer 112. Between, the non-doped amorphous silicon layer 1152 is located between the carbon nanotube semiconductor layer 1151 and the source 113 and the drain 114 . The projection of the carbon nanotube semiconductor layer 1151 on the base substrate 12 coincides with the projection of the non-doped amorphous silicon layer 1152 on the base substrate 12 .

The projections of the source 113 and the drain 114 on the base substrate 12 are located within the projection of the non-doped amorphous silicon layer 1152 on the base substrate, and at the same time, due to the carbon nano The projection of the tube semiconductor layer 1151 on the base substrate 12 coincides with the projection of the non-doped amorphous silicon layer 1152 on the base substrate 12, so the source 113 and the drain 114 are in The projection on the base substrate 12 is also located within the projection of the carbon nanotube semiconductor layer 1151 on the base substrate 12 .

The active layer 115 also includes a first doped amorphous silicon layer 1153 and a second doped amorphous silicon layer 1154, the first doped amorphous silicon layer 1153 is located between the source 113 and the non-doped between the hetero-doped amorphous silicon layer 1152, the second doped amorphous silicon layer 1154 is located between the drain electrode 114 and the non-doped amorphous silicon layer 1152, and the first doped amorphous silicon layer 1153 and the second doped amorphous silicon layer 1154 are respectively located at both ends of the non-doped amorphous silicon layer 1152, the first doped amorphous silicon layer 1153 and the second doped amorphous silicon layer Layers 1154 are spaced apart.

Preferably, the projection of the first doped amorphous silicon layer 1153 on the base substrate 12 coincides with the projection of the source 113 on the base substrate 12; The projection of the silicon layer 1154 on the base substrate 12 coincides with the projection of the drain electrode 114 on the base substrate.

Please refer to FIG. 3 to FIG. 6 at the same time, which is a method for manufacturing a thin film transistor array substrate provided in a preferred embodiment of the present invention. The method includes the following steps:

Step 101 , providing a base substrate 22 .

Wherein, the base substrate 22 can be a rigid inorganic material that is transparent (such as glass, quartz or the like) or opaque (such as a chip, ceramics or the like), or can be made of plastic, rubber, polyester or polyester. Flexible organic materials such as carbonate.

Step 102 , forming a plurality of thin film transistors 21 on the base substrate 22 . The thin film transistor 21 includes a gate 211 and a gate insulating layer 212, a source 213, a drain 214, and an active layer 215, and the source 213 and the drain 214 are respectively in contact with the active layer 215, The active layer 215 includes a carbon nanotube semiconductor layer 2151 and a non-doped amorphous silicon layer 2152, and the non-doped amorphous silicon layer 2152 is located between the carbon nanotube semiconductor layer 2151 and the source electrode 213 and the between the drain electrodes 214.

The gate 211 is located on the base substrate 22, the gate insulating layer 212 covers the gate 211 and the base substrate 22, and the active layer 215 is located on the gate insulating layer 212 And correspondingly arranged above the gate 211 , the source 213 and the drain 214 are located on the active layer 215 and are respectively arranged at two opposite ends of the active layer 215 .

The steps of forming the thin film transistor 21 are as follows:

Step 1021 , referring to FIG. 3 , first forming the gate 211 and the gate insulating layer 212 covering the gate 211 and the base substrate 22 on the base substrate 22 . Specifically, a first metal layer and a first photoresist layer may be formed on the base substrate 22, and the first metal layer is patterned through a mask to obtain the gate 211, and then A gate insulating layer 212 is laid on the gate 211 so that the gate insulating layer 212 covers the gate 211 and the substrate 22 .

Step 1022 , please refer to FIG. 4 , forming the carbon nanotube semiconductor layer 2151 on the gate insulating layer 212 . Specifically, the carbon nanotube semiconductor layer 2151 may be formed on the gate insulating layer 212 at the channel position of the TFT by self-assembly technology, catalytic cracking method, laser evaporation method and other methods.

Step 1023 , please refer to FIG. 5 , forming a non-doped amorphous silicon layer 2152 , a first doped amorphous silicon layer 2153 and a second doped amorphous silicon layer 2154 on the carbon nanotube semiconductor layer 2151 . Specifically, non-doped amorphous silicon and doped amorphous silicon may be respectively formed on the base substrate 22, and then exposed and etched to obtain the non-doped amorphous silicon layer 2152, the The first doped amorphous silicon layer 2153 and the second doped amorphous silicon layer 2154. The first doped amorphous silicon layer 2153 and the second doped amorphous silicon layer 2154 are respectively located at both ends of the non-doped amorphous silicon layer 2152, and the first doped amorphous silicon layer 2153 It is set at a certain distance from the second doped amorphous silicon layer 2154 .

The carbon nanotube semiconductor layer 2151, the non-doped amorphous silicon layer 2152, the first doped amorphous silicon layer 2153, and the second doped amorphous silicon layer 2154 constitute the active layer 215.

The projection of the carbon nanotube semiconductor layer 2151 on the base substrate 22 coincides with the projection of the non-doped amorphous silicon layer 2152 on the base substrate 22 .

Step 1024 , referring to FIG. 6 , forming a source 213 and a drain 214 on the first doped amorphous silicon layer 2153 and the second doped amorphous silicon layer 2154 respectively. Specifically, a second metal layer may be laid on the base substrate, and then the second metal layer is patterned through a mask to obtain the source 213 and the drain 214 .

The first doped amorphous silicon layer 1153 is located between the source 113 and the non-doped amorphous silicon layer 1152, and the second doped amorphous silicon layer 1154 is located between the drain 114 and the non-doped amorphous silicon layer 1152. Between the non-doped amorphous silicon layer 1152.

The projections of the source 213 and the drain 214 on the base substrate 22 are located within the projection of the non-doped amorphous silicon layer 2152 on the base substrate, and at the same time, due to the carbon nano The projection of the tube semiconductor layer 2151 on the substrate 22 coincides with the projection of the non-doped amorphous silicon layer 2152 on the substrate 22, so the source 213 and the drain 214 are The projection on the base substrate 22 is also located within the projection of the carbon nanotube semiconductor layer 2151 on the base substrate 22 .

The projection of the first doped amorphous silicon layer 1153 on the base substrate 12 coincides with the projection of the source 113 on the base substrate 12; the second doped amorphous silicon layer 1154 The projection on the base substrate 12 coincides with the projection of the drain electrode 114 on the base substrate.

In the thin film transistor array substrate, its manufacturing method, and display panel provided by the embodiments of the present invention, an active layer composed of a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer is arranged in the thin film transistor, and the non-doped amorphous The silicon layer is disposed between the carbon nanotube semiconductor layer and the source and drain. In this way, when the thin film transistor is turned on, it mainly conducts electricity through the carbon nanotube semiconductor layer in the active layer. The carbon nanotube semiconductor layer has a higher electron mobility and forms a larger on-state current. When the thin film transistor is turned off, The leakage current is mainly released through the non-doped amorphous silicon layer in the active layer, which has a small leakage current, so that the thin film transistor has a high switching current ratio.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (9)

1. A thin film transistor array substrate, the thin film transistor array substrate includes a base substrate and a plurality of thin film transistors positioned on the base substrate, the thin film transistors include a grid located on the base substrate, a gate insulation layer, a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are in contact with the active layer respectively, and it is characterized in that the active layer includes a carbon nanotube semiconductor layer and an undoped non- A crystalline silicon layer, the non-doped amorphous silicon layer is located between the carbon nanotube semiconductor layer and the source and drain. 2. The thin film transistor array substrate according to claim 1, wherein the projection of the carbon nanotube semiconductor layer on the base substrate is the same as that of the non-doped amorphous silicon layer on the base substrate. The projections on the substrate coincide, and the projections of the source and the drain on the substrate are located within the projection of the non-doped amorphous silicon layer on the substrate. 3. The thin film transistor array substrate according to claim 1, wherein the active layer further comprises a first doped amorphous silicon layer and a second doped amorphous silicon layer, the first doped amorphous silicon layer the crystalline silicon layer is located between the source and the non-doped amorphous silicon layer, the second doped amorphous silicon layer is located between the drain and the non-doped amorphous silicon layer, and The first doped amorphous silicon layer and the second doped amorphous silicon layer are arranged at intervals. 4. The thin film transistor array substrate according to claim 3, wherein the projection of the first doped amorphous silicon layer on the base substrate is the same as the projection of the source on the base substrate. The projections overlap; the projection of the second doped amorphous silicon layer on the base substrate coincides with the projection of the drain on the base substrate. 5. A display device, comprising the array substrate according to claims 1-4. 6. A method for manufacturing a thin film transistor array substrate, characterized in that the method comprises: providing a base substrate; A plurality of thin film transistors are formed on the base substrate, and the thin film transistors include a gate and a gate insulating layer, a source, a drain and an active layer, and the source and the drain are connected to the active layer respectively. source layer contact, the active layer includes a carbon nanotube semiconductor layer and a non-doped amorphous silicon layer, the non-doped amorphous silicon layer is located between the carbon nanotube semiconductor layer and the source and the drain between poles. 7. The manufacturing method according to claim 6, wherein the projection of the carbon nanotube semiconductor layer on the base substrate is the same as the projection of the non-doped amorphous silicon layer on the base substrate. The projections coincide, and the projections of the source and the drain on the base substrate are within the projection of the non-doped amorphous silicon layer on the base substrate. 8. The manufacturing method according to claim 6, wherein forming the active layer further comprises: A first doped amorphous silicon layer is formed between the source and the non-doped amorphous silicon layer, and a second doped amorphous silicon layer is formed between the drain and the non-doped amorphous silicon layer. a crystalline silicon layer, and the first doped amorphous silicon layer and the second doped amorphous silicon layer are arranged at intervals. 9. The manufacturing method according to claim 8, wherein the projection of the first doped amorphous silicon layer on the base substrate coincides with the projection of the source electrode on the base substrate ; The projection of the second doped amorphous silicon layer on the base substrate coincides with the projection of the drain electrode on the base substrate.