CN106409824A - Transistor integration method - Google Patents

Abstract

The invention is a method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor, comprising the following steps: (1) cleaning the indium phosphide heterojunction bipolar transistor wafer and the silicon metal oxide semiconductor field effect transistor with hydrochloric acid Temporary loading; (2) Bonding through temporary bonding materials; (3) Removing the indium phosphide substrate; (4) Bonding the silicon metal oxide semiconductor field effect transistor wafer with the indium phosphide heterojunction bipolar The transistor wafer is aligned and bonded by BCB; (5) remove the temporary carrier and temporary bonding material; (6) spin-coat the photoresist on the integrated wafer to lithography the etching pattern; (7) use the photoresist Etch the BCB through hole for the mask; (8) Connect the interconnection metal by electroplating. Advantages: use the epitaxial layer lift-off transfer method to realize the integration of indium phosphide heterojunction bipolar transistors and silicon metal oxide semiconductor field effect transistors on the same wafer, breaking the inherent limitations of semiconductor materials and improving integration .

Description

A method of transistor integration

technical field

The invention relates to a method for integrating transistors, in particular to a method for integrating indium phosphide heterojunction bipolar transistors and silicon metal oxide semiconductor field effect transistors, and belongs to the technical field of semiconductor technology.

Background technique

The indium phosphide heterojunction bipolar transistor has the advantages of ultra-high speed and high breakdown, but it has a low integration level and high power consumption. If the indium phosphide heterojunction bipolar transistor device and the mature silicon metal oxide semiconductor field effect transistor can be integrated on the same wafer, the respective performance advantages of the two can be fully utilized, and the performance and performance that cannot be achieved by any single technology can be achieved. function is of great significance.

At present, the technical approaches adopted to achieve transistor-level integration mainly include "micron-scale micro-assembly technology" and "monolithic heteroepitaxy technology", among which "micron-scale micro-assembly technology" is the combination of "indium phosphide heterojunction dual Pole type transistor chip unit" is bonded to the top of the silicon metal oxide semiconductor field effect transistor in a form similar to "upside down welding". Since the object of this technology integration is "chip unit" (Chiplet) rather than "transistor", so The flexibility of integration is greatly limited; for "monolithic heteroepitaxial technology", if the indium phosphide epitaxial layer is grown directly on the silicon substrate, since silicon and indium phosphide belong to different materials system, the existence of both, problems such as lattice mismatch and thermal mismatch, so the quality of the indium phosphide epitaxial material on the silicon substrate is poor, and the semiconductor material grown by heteroepitaxial growth contains a high dislocation density, which makes the material properties occur. Changes, which affect the performance of indium phosphide devices, resulting in considerable restrictions on the development and application of this technology.

For this problem, researchers do not have a good solution at present. They can only grow heteroepitaxially on semiconductor materials with small lattice mismatch, which severely limits the development of integration technology.

Contents of the invention

The present invention proposes a method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor, and its purpose is to solve the problem of the indium phosphide heterojunction bipolar transistor and silicon metal oxide Problems such as lattice mismatch and thermal mismatch exist in the integration between semiconductor field effect transistors. The epitaxial layer lift-off transfer method is used to realize the integration of the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor on the same wafer.

The technical solution of the present invention is a method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor, comprising the following steps:

(1) Clean the indium phosphide heterojunction bipolar transistor wafer and temporary carrier with diluted hydrochloric acid;

(2) The front side of the indium phosphide heterojunction bipolar transistor wafer is bonded to the temporary carrier through a temporary bonding material;

(3) removing the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer;

(4) Align and bond the silicon metal oxide semiconductor field effect transistor wafer and the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier through BCB;

(5) Remove temporary slides and temporary adhesive materials;

(6) Spin-coat photoresist on a wafer integrated with a silicon metal oxide semiconductor field effect transistor and an indium phosphide heterojunction bipolar transistor;

(7) Etch BCB through holes using photoresist as a mask;

(8) Connecting the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor through electroplating interconnection metal.

The present invention has the following advantages:

1) Breaking the inherent limitation of lattice mismatch, integrating indium phosphide heterojunction bipolar transistors and silicon metal oxide semiconductor field effect transistors on the same wafer;

2) The integration between different transistors is more miniaturized and integrated for the overall integrated chip;

3) The biggest feature of the present invention is to use the epitaxial layer peeling transfer method to realize the integration of indium phosphide heterojunction bipolar transistors and silicon metal oxide semiconductor field effect transistors on the same wafer, and conventional heteroepitaxial growth Compared with the method and the upside-down welding method, it breaks the inherent limitation of semiconductor materials and can improve the integration degree at the same time.

Description of drawings

Figure 1 is a schematic diagram of a temporary slide sample.

Fig. 2 is a schematic diagram of a wafer sample of an indium phosphide heterojunction bipolar transistor.

Fig. 3 is a schematic diagram of bonding an indium phosphide heterojunction bipolar transistor wafer and a temporary carrier through a temporary adhesive material.

Fig. 4 is a schematic diagram of removing the indium phosphide substrate from the indium phosphide heterojunction bipolar transistor wafer.

Fig. 5 is a schematic diagram of a silicon metal oxide semiconductor field effect transistor wafer sample.

Fig. 6 is a schematic diagram of aligning and bonding a silicon metal oxide semiconductor field effect transistor wafer and an indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier through BCB.

Fig. 7 is a schematic diagram of removing the temporary carrier and the temporary adhesive material.

FIG. 8 is a schematic diagram of photoetching patterns on a wafer integrated with silicon metal oxide semiconductor field effect transistors and indium phosphide heterojunction bipolar transistors.

FIG. 9 is a schematic diagram of connecting an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor through electroplating interconnection metal.

detailed description

A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor, comprising the following steps:

(1) Clean the indium phosphide heterojunction bipolar transistor wafer and the temporary carrier with diluted hydrochloric acid: clean the surface of the indium phosphide heterojunction bipolar transistor wafer and the temporary carrier with diluted hydrochloric acid, and then use Rinse with ionized water, and then put it into a spin dryer for drying. Temporary slides include glass slides, sapphire, and aluminum nitride;

(2) The front side of the indium phosphide heterojunction bipolar transistor wafer is bonded to the temporary carrier through a temporary adhesive material: spin-coat the temporary adhesive material on the front side of the indium phosphide heterojunction bipolar transistor wafer;

(3) Remove the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer: the front of the indium phosphide heterojunction bipolar transistor wafer and the temporary carrier face each other at a temperature of 180-200°C Bonding under the condition:

1) Remove the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer, and obtain the indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier;

2) Clean the surface of the silicon metal oxide semiconductor field effect transistor wafer with diluted hydrochloric acid, rinse it with deionized water, and then put it in a dryer for drying;

(4) Align and bond the silicon metal oxide semiconductor field effect transistor wafer with the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier through BCB:

1) Spin-coat BCB on the front side of the indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier at a speed of 1000rpm-5000rpm for 30-60 seconds;

2) Put the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier face up on the hot plate and bake for 2-5 minutes, the temperature of the hot plate is 100-110 ℃;

3) After the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier is cooled naturally at room temperature, the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier and the The wafers of silicon metal oxide semiconductor field effect transistors face each other, and are aligned through the respective alignment marks on the two wafers, and bonded at a temperature of 250-300°C;

(5) Remove the temporary carrier and temporary bonding material: remove the temporary carrier and temporary bonding material on the bonded wafer;

(6) Spin-coating photoresist on a wafer integrated with silicon metal oxide semiconductor field effect transistors and indium phosphide heterojunction bipolar transistors to produce etching patterns: in silicon metal oxide semiconductor field effect transistors and phosphorus Spin-coat photoresist on wafers integrated with indium heterojunction bipolar transistors and photoetch etching patterns;

(7) Etch BCB via holes with photoresist as a mask: use photoresist as a mask to etch on a wafer integrating silicon metal oxide semiconductor field effect transistor and indium phosphide heterojunction bipolar transistor Exit the BCB via hole until the top layer metal of the silicon metal oxide semiconductor field effect transistor is etched;

(8) The indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor are connected by electroplating interconnection metal, and the interconnection metal is electroplated in the etched BCB via hole, and the indium phosphide heterojunction bipolar The polar transistor is connected to the silicon metal oxide semiconductor field effect transistor through interconnection metal.

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings.

①Preparation of samples: Clean the indium phosphide heterojunction bipolar transistor wafers and temporary slides with diluted hydrochloric acid (HCl) and deionized water, and put them in a dryer for drying. Figure 1, as shown in Figure 2.

②Temporary bonding: Spin-coat temporary bonding material on the front side of the indium phosphide heterojunction bipolar transistor wafer, and put the indium phosphide heterojunction bipolar transistor wafer coated with the temporary bonding material face up Put it on a hot plate for pre-baking, the temperature of the hot plate is 90-120°C, and the time is 2-5 minutes. Then stack the indium phosphide heterojunction bipolar transistor wafer and the front side of the temporary carrier relative to each other, and use a bonding machine to perform wafer bonding. The bonding temperature is 180-200°C and the bonding time is 30-60°C. minutes, as shown in Figure 3.

③Backside process: After the bonding is completed, the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer is ground to 50-100um, and then the remaining indium phosphide substrate is etched away with a chemical etching solution ,As shown in Figure 4.

④Preparation of samples: Clean the silicon metal oxide semiconductor field effect transistor wafer with diluted hydrochloric acid (HCl) and deionized water, and put it in a dryer for drying, as shown in Figure 5.

⑤ Bonding: Drop an appropriate amount of BCB on the front of the indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier, and spin-coat at a rate of 1000-5000rpm according to different thicknesses, and the spin-coating time should not be less than For 30 seconds, place the indium phosphide heterojunction bipolar transistor wafer coated with BCB and supported by a temporary carrier face up on the hot plate for pre-baking. The temperature of the hot plate is 100-110°C. Time 2-5 minutes. Then, the front faces of the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier and the silicon metal oxide semiconductor field effect transistor wafer are aligned using the alignment machine through their respective alignment marks, and then Wafer bonding is performed using a bonder. The bonding temperature is 250-300°C, and the bonding time is 1-2 hours, as shown in Figure 6.

⑥ De-bonding: Soak the bonded wafer in the temporary adhesive material remover, the liquid surface should be completely immersed in the wafer, and after the temporary adhesive material is completely dissolved, it will be automatically separated from the temporary slide, and its Carefully hold it up and rinse it with deionized water to obtain a wafer integrating silicon metal oxide semiconductor field effect transistors and indium phosphide heterojunction bipolar transistors, as shown in FIG. 7 .

⑦ Photolithography and etching pattern: Spin-coat photoresist on the wafer integrated with silicon metal oxide semiconductor field effect transistor and indium phosphide heterojunction bipolar transistor, and form an etching pattern through exposure and development, as shown in Figure 8 .

⑧Etching the BCB through hole: use the photoresist as a mask, and use a plasma etching machine to etch the BCB until the top layer metal of the silicon metal oxide semiconductor field effect transistor is etched.

⑨ Electroplating interconnection metal: electroplating interconnection metal in the etched BCB through hole, and connecting the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor through the interconnection metal, as shown in Figure 9.

Example

① Soak the indium phosphide heterojunction bipolar transistor wafer and the glass slide in diluted hydrochloric acid (HCl) for 60 seconds, then rinse with deionized water, and put them in a spin dryer for drying.

② Spin-coat high-temperature wax on the front surface of the InP heterojunction bipolar transistor wafer, the speed is 2000 rpm, and the spin-coating time is 90 seconds, and the InP heterojunction bipolar transistor coated with high-temperature wax Put the disc face up on the hot plate, the temperature of the hot plate is 110° C., and the drying time is 5 minutes.

③Take out the indium phosphide heterojunction bipolar transistor disc from the hot plate and stack it with the front of the glass slide, fix it with a clamp and put it into the bonding machine for bonding. The bonding temperature is 200 ° C. Combined time is 60 minutes.

④ After bonding, thin the back of the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer to about 100 microns, and then use a mixed solution of H ₂ SO ₄ and H ₂ O ₂ to thin the back of the indium phosphide substrate. Thin substrates are etched away.

⑤ Spin-coat BCB on the front surface of the indium phosphide heterojunction bipolar transistor wafer supported by a glass slide at a rotation speed of 5000 rpm and a spin-coating time of 90 seconds. The indium heterojunction bipolar transistor wafer faces upwards on a heating plate, the temperature of the hot plate is 110°C, and the baking time is 2-5 minutes.

⑥Take out the InP heterojunction bipolar transistor wafer supported by the glass slide from the hot plate and face the front side of the silicon metal oxide semiconductor field effect transistor wafer using the alignment machine through their respective alignment marks. Align, fix with a jig and put it into a bonding machine for bonding. The bonding temperature is 300°C and the bonding time is 2 hours.

⑦ Soak the bonded wafer in the high-temperature wax remover. The liquid surface should be completely immersed in the wafer. After the high-temperature wax is completely dissolved, it will be automatically separated from the temporary slide. Carefully hold it up and rinse it with deionized water. That is, a wafer integrated with a silicon metal oxide semiconductor field effect transistor and an indium phosphide heterojunction bipolar transistor can be obtained.

⑧ Spin-coat photoresist on the wafer integrated with silicon metal oxide semiconductor field effect transistor and indium phosphide heterojunction bipolar transistor, the rotation speed is 3000 rpm, and the spin coating time is 60 seconds. The integrated wafer faces upwards on a hot plate, the temperature of the hot plate is 110°C, and the drying time is 2 minutes. The photoresist was exposed with a photolithography machine for 70 seconds, and then developed with a developer for 120 seconds to obtain an etched pattern.

⑨Using the photoresist as a mask, use a plasma etching machine to etch the BCB, using the etching gas SF6, until the top layer metal of the silicon metal oxide semiconductor field effect transistor is etched.

⑩ Electroplate the interconnection metal in the etched BCB through hole, the electroplating metal is gold, and connect the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor through the interconnection metal.

Through the above steps, the integration of the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor is realized.

Claims (9)

1. A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor, characterized in that the method may further comprise the steps: (1) Clean the indium phosphide heterojunction bipolar transistor wafer and temporary carrier with diluted hydrochloric acid; (2) The front side of the indium phosphide heterojunction bipolar transistor wafer is bonded to the temporary carrier through a temporary bonding material; (3) removing the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer; (4) Align and bond the silicon metal oxide semiconductor field effect transistor wafer and the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier through BCB; (5) Remove temporary slides and temporary adhesive materials; (6) Spin-coat photoresist on a wafer integrated with a silicon metal oxide semiconductor field effect transistor and an indium phosphide heterojunction bipolar transistor; (7) Etch BCB through holes using photoresist as a mask; (8) Connecting the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor field effect transistor through electroplating interconnection metal. 2. A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that the steps are described; (1) dilute hydrochloric acid cleaning phosphorus Indium Phosphide Heterojunction Bipolar Transistor Wafer and Temporary Carrier: Clean the surface of the Indium Phosphide Heterojunction Bipolar Transistor wafer and the temporary carrier with diluted hydrochloric acid, rinse with deionized water, and then put The drying machine is used for drying, and the temporary slides include glass slides, sapphire, and aluminum nitride. 3. A method for integrating an indium phosphide heterojunction bipolar transistor with a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that the step (2) of the indium phosphide heterojunction The front side of the bipolar transistor wafer is bonded to the temporary carrier through a temporary bonding material: the temporary bonding material is spin-coated on the front side of the indium phosphide heterojunction bipolar transistor wafer. 4. A method for integrating an indium phosphide heterojunction bipolar transistor with a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that in the step (3) the indium phosphide heterojunction Removal of the indium phosphide substrate of the junction bipolar transistor wafer: bond the front side of the indium phosphide heterojunction bipolar transistor wafer and the temporary carrier at a temperature of 180-200°C: 1) Remove the indium phosphide substrate of the indium phosphide heterojunction bipolar transistor wafer, and obtain the indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier; 2) Wash the surface of the silicon metal oxide semiconductor field effect transistor wafer with diluted hydrochloric acid, rinse it with deionized water, and then put it into a dryer for drying. 5. A method for integrating an indium phosphide heterojunction bipolar transistor with a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that in the step (4) the silicon metal oxide semiconductor The field effect transistor wafer and the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier are aligned and bonded by BCB: 1) Spin-coat BCB on the front side of the indium phosphide heterojunction bipolar transistor wafer supported by a temporary carrier at a speed of 1000rpm-5000rpm for 30-60 seconds; 2) Put the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier face up on the hot plate and bake for 2-5 minutes, the temperature of the hot plate is 100-110 ℃; 3) After the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier is cooled naturally at room temperature, the indium phosphide heterojunction bipolar transistor wafer supported by the temporary carrier and the The wafers of silicon metal oxide semiconductor field effect transistors face each other face to face, and are aligned through the respective alignment marks on the two wafers, and bonded at a temperature of 250-300°C. 6. A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that the step (5) removes the temporary carrier and the temporary Adhesive material: Remove the temporary carrier and temporary adhesive material on the bonded wafer. 7. A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that the step (6) is performed in the silicon metal oxide semiconductor field effect transistor Spin-coating photoresist lithography on wafers integrating field-effect transistors and indium phosphide heterojunction bipolar transistors: etching patterns in silicon metal oxide semiconductor field-effect transistors and indium phosphide heterojunction bipolar transistors The photoresist is spin-coated on the integrated wafer and the etched pattern is photoetched. 8. A method for integrating an indium phosphide heterojunction bipolar transistor and a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that the step (7) uses photoresist as a mask Etch BCB via holes: use photoresist as a mask to etch BCB via holes on the wafer integrated with silicon metal oxide semiconductor field effect transistors and indium phosphide heterojunction bipolar transistors until etched to The top metal of silicon metal oxide semiconductor field effect transistors. 9. A method for integrating an indium phosphide heterojunction bipolar transistor with a silicon metal oxide semiconductor field effect transistor according to claim 1, characterized in that in the step (8) the indium phosphide heterojunction The junction bipolar transistor and the silicon metal oxide semiconductor field effect transistor are connected by electroplating interconnection metal, and the interconnection metal is electroplated in the etched BCB through hole, and the indium phosphide heterojunction bipolar transistor and the silicon metal oxide semiconductor Field effect transistors are connected by interconnect metals.