CN106407138A - LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit - Google Patents
LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit Download PDFInfo
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- CN106407138A CN106407138A CN201510466134.7A CN201510466134A CN106407138A CN 106407138 A CN106407138 A CN 106407138A CN 201510466134 A CN201510466134 A CN 201510466134A CN 106407138 A CN106407138 A CN 106407138A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F2213/3852—Converter between protocols
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Abstract
The invention discloses a LVDS (Low Voltage Differential Signaling) interface and DSI (Display Serial Interface) multiplexing circuit, and is used for solving the problem of interface resource waste caused in a way that the LVDS interface and the DSI can not be multiplexed. The circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit, wherein the data clock selection circuit selects a current interface mode, receives a data signal and a clock signal input from outside, and provides the data signal and the clock signal to the data clock synchronization circuit; the data clock synchronization circuit carries out synchronization on the data signal and the clock signal, provided the synchronized data signal and clock signal for the data conversion circuit; the data conversion circuit converts the synchronized data signal to be serial from parallel, and outputs a differential data signal to the driving circuit; and the driving circuit utilizes the differential data signal to control the range of the output signal so as to realize the multiplexing of the LVDS interface and the DSI and reduce resource waste.
Description
Technical Field
The invention relates to the field of display interfaces, in particular to a method and a circuit for multiplexing an LVDS interface and a DSI interface.
Background
Low Voltage Differential Signaling (LVDS) transmission is a mature signal transmission technology and is widely applied to the field of display interfaces, especially liquid crystal display screens. However, with the rapid development of mobile terminals, higher requirements are made on the bandwidth of the display interface. Therefore, the MIPI (mobile industry Processor Interface) alliance proposes a Display Serial Interface (DSI) specification to meet the requirement of a higher resolution Display screen. For mobile consumer electronic terminals, in order to meet the wider market demand, two display interface technologies are present in the mobile processor interface to meet different customer requirements, and the customer can choose to use only one interface according to the actual scheme.
Fig. 1 is a typical implementation of LVDS and DSI interfaces in a mobile processor. This method has some disadvantages: firstly, the area is large, the interface circuits of LVDS and DSI are mutually independent and need respective circuit modules to realize; secondly, the power consumption is large, and two circuits need to be supplied with power independently; thirdly, the packaging cost is high, the LVDS and DSI modules are independent, a pin (pin) needs to be separately output during packaging, and the LVDS and the DSI generally have 5 channels (lane), so that 10 pins need to be respectively packaged, and in practical application, only one of the pins can be selected according to a development scheme, which inevitably results in wasting resources of 10 pins.
Therefore, because the LVDS interface and the DSI interface in the prior art are designed independently, that is, they are not multiplexed, certain interface resources are inevitably wasted, and the cost of the mobile processor is increased.
Disclosure of Invention
The invention aims to provide a LVDS interface and DSI interface multiplexing circuit to solve the problem of interface resource waste caused by the fact that the LVDS interface and the DSI interface cannot be multiplexed.
The purpose of the invention is realized by the following technical scheme:
a low-voltage differential signaling LVDS interface and display differential DSI interface multiplexing circuit comprises: the data clock synchronization circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit; wherein,
the data clock selection circuit is connected with the mode control circuit and the data clock synchronization circuit, and is used for selecting a current interface mode under the mode control of the mode control circuit, receiving an externally input data signal and a clock signal and providing the externally input data signal and the clock signal to the data clock synchronization circuit;
the data clock synchronization circuit is connected with the mode control circuit and the data conversion circuit, and is used for synchronizing the data signal and the clock signal under the mode control of the mode control circuit and providing the synchronized data signal and clock signal to the data conversion circuit;
the data conversion circuit is connected with the mode control circuit and the drive circuit and is used for converting the synchronized data signals from parallel to serial under the mode control of the mode control circuit and outputting differential data signals to the drive circuit;
and the driving circuit is connected with the mode control circuit and is used for controlling the amplitude range and the common mode range of the output signal by using the differential data signal under the mode control of the mode control circuit.
Therefore, multiplexing of the LVDS interface and the DSI interface is achieved, the number of packaging pins can be reduced, packaging cost is reduced, and interface resource waste is reduced.
Optionally, the driving circuit includes a first circuit, an impedance control circuit, a first switch group, and a second circuit;
the first circuit is connected with the mode control circuit and the first switch group and is used for outputting current of a corresponding mode to the first switch group under the mode control of the mode control circuit;
the first switch group is connected with the data conversion circuit and used for receiving the current output by the first circuit under the control of the differential data signal and outputting the current to the second circuit;
the second circuit is connected with the first switch group and the impedance control circuit and used for receiving the current output by the first circuit and shunting the current under the control of the impedance control circuit so as to output corresponding differential signals.
Optionally, the second circuit includes a first variable resistor, a second variable resistor, and a first resistor, and the first switch group includes a first switch and a second switch;
a first end of the first resistor is connected with a first end of the first variable resistor and the first switch to serve as a negative output end of the differential signal, a second end of the first resistor is connected with a first end of the second variable resistor and the second switch to serve as a positive output end of the differential signal, and the second end of the first variable resistor and the second end of the second variable resistor are both connected with a source electrode ground power supply;
the impedance control circuit is respectively connected with the third end of the first variable resistor and the third end of the second variable resistor and is used for controlling the resistance values of the first variable resistor and the second variable resistor to enable the second circuit to output corresponding differential signals.
Optionally, the LVDS interface and DSI interface multiplexing circuit further includes:
the grid electrode of the first switch is connected with the negative output end of the differential data signal output by the data conversion circuit, the source electrode of the first switch is connected with the output end of the first circuit, the drain electrode of the first switch is connected with the first end of the first resistor, the grid electrode of the second switch is connected with the positive output end of the differential data signal output by the data conversion circuit, the source electrode of the second switch is connected with the output end of the first circuit, and the drain electrode of the second switch is connected with the second end of the first resistor;
the first switch and the second switch are turned on under the control of a differential data signal output by the data conversion circuit.
Wherein the first switch and the second switch are both P-type transistors.
Optionally, the LVDS interface and DSI interface multiplexing circuit further includes:
the grid electrode of the first switch is connected with the positive output end of the differential data signal output by the data conversion circuit, the source electrode of the first switch is connected with the output end of the first circuit, the drain electrode of the first switch is connected with the first end of the first resistor, the grid electrode of the second switch is connected with the negative output end of the differential data signal output by the data conversion circuit, the source electrode of the second switch is connected with the output end of the first circuit, and the drain electrode of the second switch is connected with the second end of the first resistor;
the first switch and the second switch are turned on under the control of a differential data signal output by the data conversion circuit;
wherein the first switch and the second switch are both N-type transistors.
Optionally, the first variable resistor includes a second resistor and a first N-type transistor, the second variable resistor includes a third resistor and a second N-type transistor, where the resistance values of the second resistor and the third resistor are the same and greater than 0, the first end of the second resistor is connected to the first end of the first resistor, the source of the first N-type transistor is connected to the second end of the second resistor, the first end of the third resistor is connected to the second end of the first resistor, the source of the second N-type transistor is connected to the second end of the third resistor, the drains of the first N-type transistor and the second N-type transistor are both connected to the source ground power supply, and the gates of the first N-type transistor and the second N-type transistor are both connected to the impedance control circuit;
the impedance control circuit comprises a common-mode feedback unit and an operational amplifier, wherein the positive input end of the common-mode feedback unit is connected with the second end of the first resistor, the negative input end of the common-mode feedback unit is connected with the first end of the first resistor, the output end of the common-mode feedback unit is connected with the positive input end of the operational amplifier, reference voltages in different modes are input into the negative input end of the operational amplifier, the output end of the operational amplifier is respectively connected with the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor, and the reference voltages are common-mode voltages of standard differential signals output by the interface circuit in different modes;
the common mode feedback unit and the operational amplifier clamp the differential signal output by the second circuit and output a bias voltage to bias the first N-type transistor and the second N-type transistor so as to control the resistance values of the first variable resistor and the second variable resistor, so that the second circuit outputs a corresponding differential signal.
Optionally, the first variable resistor is a third N-type transistor, the second variable resistor is a fourth N-type transistor, a source of the fourth N-type transistor is connected to the first end of the first resistor, a source of the second N-type transistor is connected to the second end of the first resistor, drains of the first N-type transistor and the second N-type transistor are both connected to a source ground power supply, and gates of the first N-type transistor and the second N-type transistor are both connected to the impedance control circuit;
the impedance control circuit comprises a common-mode feedback unit and an operational amplifier, wherein the positive input end of the common-mode feedback unit is connected with the second end of the first resistor, the negative input end of the common-mode feedback unit is connected with the first end of the first resistor, the output end of the common-mode feedback unit is connected with the positive input end of the operational amplifier, reference voltages in different modes are input into the negative input end of the operational amplifier, the output end of the operational amplifier is respectively connected with the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor, and the reference voltages are common-mode voltages of standard differential signals output by the interface circuit in different modes;
the common mode feedback unit and the operational amplifier clamp the differential signal output by the second circuit and output a bias voltage to bias the first N-type transistor and the second N-type transistor so as to control the resistance values of the first variable resistor and the second variable resistor, so that the second circuit outputs a corresponding differential signal.
Optionally, the impedance control circuit comprises a calibration current source, a calibration variable resistor, a comparator, an adder-subtractor and a calibration controller,
the calibration current source is used for generating calibration current and outputting the calibration current to the calibration variable resistor;
the positive input end of the comparator is connected with the output end of the calibration current source and the first end of the calibration variable resistor, the negative input end of the comparator inputs calibration voltages in different modes, the calibration voltages are used for comparing the magnitude of the input voltage values and outputting a comparison result to the adder-subtractor, and the calibration voltages are the products of standard variable resistance values and calibration current values in different modes;
the input end of the adder-subtractor is connected with the output end of the comparator and used for generating a corresponding addition-subtraction instruction according to an input comparison result and outputting the addition-subtraction instruction to the calibration controller;
the input end of the calibration controller is connected with the output end of the adder-subtractor, the output end of the calibration controller is connected with the third end of the calibration variable resistor, the third end of the first variable resistor and the third end of the second variable resistor, and the calibration controller is used for controlling the resistance values of the calibration variable resistor, the first variable resistor and the second variable resistor according to an input addition and subtraction instruction to enable the second circuit to output corresponding differential signals, wherein the second end of the standard variable resistor is connected with a source ground power supply.
Optionally, the calibration variable resistor is formed by connecting M unit resistors in parallel, each unit resistor is an NMOS transistor with a set resistance value, and M is a set positive integer.
Drawings
FIG. 1 is a schematic diagram of a conventional LVDS interface and a DSI interface in a mobile processor;
FIG. 2 is a schematic diagram of conventional DSI and LVDS channels;
fig. 3A is a schematic diagram of an exemplary structure of an LVDS interface driving circuit;
FIG. 3B is a diagram illustrating an exemplary structure of a DSI driver circuit;
FIG. 4 is a schematic diagram of a multiplexing circuit structure of an LVDS interface and a DSI interface according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a driving circuit in a multiplexing circuit of an LVDS interface and a DSI interface according to an embodiment of the present invention;
fig. 6 is a specific example diagram of a driving circuit in an LVDS interface and DSI interface multiplexing circuit according to an embodiment of the present invention;
FIG. 7A is a schematic diagram of a connection of the first switch of FIG. 5;
FIG. 7B is a schematic diagram of a connection of the second switch of FIG. 5;
FIG. 8 is a schematic diagram of the variable resistor of FIG. 5;
fig. 9 is a diagram illustrating another specific example of a driving circuit in the LVDS interface and DSI interface multiplexing circuit according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For both DSI and LVDS channels, the architecture shown in fig. 2 is typically used. The system mainly comprises two modules, namely a data processing circuit and a driving circuit, wherein:
the data processing circuit mainly realizes the parallel-serial processing of input data, converts n +1bit parallel data into 1bit serial data, and usually the serial data is differential. For channels of LVDS, Data [ n: 0] is 7bit, i.e. the parallel data of 7bit is converted into serial data of 1 bit; for the DSI channel, Data [ n: 0 is 8 bits, i.e., 8 bits of parallel data are converted into 1bit of serial data.
The driving circuit mainly realizes the swing control of serial differential data and the enhancement of driving capability. For LVDS, the amplitude range of the output differential signal is 250-450 mv, and the common mode range is 1.125-1.375 v; for DSI, the amplitude range of the DSI output differential signal is 140-270 mv, and the common mode range is 150-250 mv.
Because the data processing circuits are all logic circuits, the design difficulty is low generally, and the data processing circuits are realized by adopting low-voltage devices, so that the occupied area is small. The driving circuit may involve some analog signals and electrostatic discharge (ESD) processing, and is usually implemented by using a high-voltage device, which is difficult to design and occupies a large area, and thus becomes a key point and a key point of interface design.
Specifically, fig. 3A is a typical structure of an LVDS interface driving circuit, according to the specification requirement of LVDS, an amplitude range of an output signal of the LVDS is 250 to 450mv, and a common mode range is 1.125 to 1.375 v. Typically, the output swing is 350mv, the common mode voltage is 1.25v, and then two current sources of 3.5mA are used, and NM1, NM2, PM1 and PM2 total 4 MOS switches are used to switch the current paths, so that 3.5mA current flows through 100 Ω resistor at the receiving end to obtain a differential signal with a swing of 350mv, where NM1 and NM2 are N-type MOS transistors, and PM1 and PM2 are P-type MOS transistors.
FIG. 3B shows a typical structure of a DSI interface driving circuit, according to the specification of DSI, in a high-speed mode, the amplitude range of the DSI output signal is 140-270 mv, and the common mode range is 150-250 mv. Typically, the output swing is 200mv, the common mode voltage is 200mv, and at this time, the DSI uses accurate load resistors R1 and R2 to shunt together with an external 100 Ω to achieve the purpose of generating a differential signal, and in order to obtain the common mode voltage of 200mv, Ib is 8mA and the resistances of R1 and R2 are both accurate 50 Ω.
Based on the structures of the existing LVDS interface driving circuit and DSI interface driving circuit, an embodiment of the present invention provides a circuit for multiplexing an LVDS interface and a DSI interface, and the specific structure is shown in fig. 4, and includes a data clock selecting circuit 40, a data clock synchronizing circuit 41, a mode control circuit 42, a data converting circuit 43, and a driving circuit 44; wherein,
and a data clock selection circuit 40, connected to the mode control circuit 42 and the data clock synchronization circuit 41, for selecting a current interface mode under mode control of the mode control circuit 42, receiving an externally input data signal and clock signal, and providing the data signal and clock signal to the data clock synchronization circuit 41.
And a data clock synchronizing circuit 41 connected to the mode control circuit 42 and the data converting circuit 43, for synchronizing the input data signal and the clock signal under the mode control of the mode control circuit 42, and providing the synchronized data signal and clock signal to the data converting circuit 43.
And a data conversion circuit 43, connected to the mode control circuit 42 and the driving circuit 44, for converting the synchronized data signals from parallel to serial under the mode control of the mode control circuit 42, and outputting differential data signals to the driving circuit 44.
And a driving circuit 44 connected to the mode control circuit 42 for controlling the amplitude range and the common mode range of the output signal by using the input differential data signal under the mode control of the mode control circuit 42.
Specifically, referring to fig. 5, the embodiment of the present invention provides a schematic diagram of a driving circuit 44, where the driving circuit 44 includes a first circuit 50, an impedance control circuit 51, a first switch group 52, and a second circuit 53, where;
and a first circuit 50 connected to the mode control circuit 42 and the first switch group 52 for outputting a current corresponding to the mode to the first switch group 52 under the mode control of the mode control circuit 42.
And a first switch group 52 connected to the data conversion circuit 43, for receiving the current output by the first circuit 50 and outputting the current to the second circuit 53 under the control of the differential data signal output by the data conversion circuit 43.
And a second circuit 53, connected to the first switch group 52 and the impedance control circuit 51, for receiving the current output by the first circuit 50, and shunting the input current under the control of the impedance control circuit 51 to output a corresponding differential signal.
Specifically, the second circuit 53 includes a first variable resistor RX1, a second variable resistor RX2, and a first resistor R1, and the first switch group 52 includes a first switch S1 and a second switch S2, where:
a first end of the first resistor R1 is connected to a first end of the first variable resistor RX1 and the first switch S1 as a negative output terminal of the differential signal, a second end of the first resistor R1 is connected to a first end of the second variable resistor RX2 and the second switch S2 as a positive output terminal of the differential signal, and a second end of the first variable resistor RX1 and a second end of the second variable resistor RX2 are both connected to the source ground power supply.
The impedance control circuit 51 is respectively connected to the third terminal of the first variable resistor RX1 and the third terminal of the second variable resistor RX2, and is configured to control the resistance values of the first variable resistor RX1 and the second variable resistor RX2 so that the second circuit 53 outputs a corresponding differential signal.
As can be seen, fig. 5 is a structural diagram of one implementation of the driving circuit 44 in fig. 4. The switches S1 and S2 are controlled by the input differential signal, and only one of them is turned on. Rx1 and Rx2 are variable resistors and the resistance values are kept the same at any time, Rx1 is Rx2 is Rx, the resistance values are controlled by the impedance control circuit, and the resistance values are determined according to the working mode. The current source Ib is also required to determine the current value according to the operation mode.
Taking S1 as an example, assuming that the common mode voltage of the output differential signal is Vcom and the swing of the differential signal is Vdiff, the following result can be easily derived:
Vp+Vn＝Rx·I＝2Vcom
for LVDS mode, the requirement Vcom is typically 1.25v and the signal swing is 0.35v, which yields:
Rx＝2050/7≈293Ω，I＝7/820≈0.0085A
for DSI operation mode, typically, Vcom is required to be 0.2v, and the signal swing is 0.2v, which yields:
Rx＝50Ω，I＝0.008A
through the analysis, the LVDS and DSI working modes can be realized only by selecting different Rx and Ib values. And the reference current Ib of the two is very close, and only the Ib needs to be finely adjusted. For example, in order to satisfy the requirement that the swing of the output differential signal can be adjusted in a wide range, the adjustable range of Ib can be set to 8mA ± 3.5mA, i.e., 4.5mA to 11.5mA, and the step size is 0.5 mA.
Further, in fig. 5, the first switch S1 and the second switch S2 may be implemented by using transistors, and if the first switch S1 and the second switch S2 are both P-type transistors, the first switch S1 is denoted by PM1, and the second switch S2 is denoted by PM2, the structure of the driving circuit may be as shown in fig. 6, where a gate of the first switch S1 is connected to a negative output terminal of the differential data signal output by the data conversion circuit 43, a source of the first switch S1 is connected to an output terminal of the first circuit 50, a drain of the first switch S1 is connected to a first end of the first resistor R1, a gate of the second switch S2 is connected to a positive output terminal of the differential data signal output by the data conversion circuit 43, a source of the second switch S2 is connected to an output terminal of the first circuit 50, and a drain of the second switch S2 is connected to a second end of the first resistor R1.
The first switch S1 and the second switch S2 turn on one of them under the control of the differential data signal output from the data conversion circuit 43.
For another example, if the first switch S1 and the second switch S2 in fig. 5 are both N-type transistors, at this time, the same function can be achieved by merely controlling to swap the differential data signals output by the data conversion circuit 43 in fig. 6, wherein a gate of the first switch S1 is connected to a positive output terminal of the differential data signal output by the data conversion circuit 43, a source of the first switch S1 is connected to an output terminal of the first circuit 50, a drain of the first switch S1 is connected to a first end of the first resistor R1, a gate of the second switch S2 is connected to a negative output terminal of the differential data signal output by the data conversion circuit 43, a source of the second switch S2 is connected to an output terminal of the first circuit 50, and a drain of the second switch S2 is connected to a second end of the first resistor R1.
The first switch S1 and the second switch S2 are turned on under the control of the differential data signal output by the data conversion circuit 43, and specifically, the connection schematic diagram of the first switch and the second switch can be seen in fig. 7A and 7B.
Further, in fig. 5, the first variable resistor RX1 and the second variable resistor RX2 may achieve their functions by using a fixed resistor in series with an N-type transistor, and the structure of the driving circuit may be as shown in fig. 6, where the first variable resistor RX1 includes a second resistor R2 and a first N-type transistor NM1, the second variable resistor RX2 includes a third resistor R3 and a second N-type transistor NM2, where the resistances of the second resistor R2 and the third resistor R3 are the same and greater than 0, a first end of the second resistor R2 is connected to a first end of the first resistor R1, a source of the first N-type transistor NM1 is connected to a second end of the second resistor R2, a first end of the third resistor R3 is connected to a second end of the first resistor R1, a source of the second N-type transistor NM2 is connected to a second end of the third resistor R3, and the sources of the first N-type transistor NM1 and the second N-type transistor NM2 are both electrically connected to the source, the gates of the first N-type transistor NM1 and the second N-type transistor NM2 are all connected to the impedance control circuit 51;
the impedance control circuit 51 includes a common mode feedback unit 610 and an operational amplifier 611, a positive input terminal of the common mode feedback unit 610 is connected to a second terminal of the first resistor R1, a negative input terminal of the common mode feedback unit 610 is connected to a first terminal of the first resistor R1, an output terminal of the common mode feedback unit 610 is connected to a positive input terminal of the operational amplifier 611, reference voltages in different modes are input to the negative input terminal of the operational amplifier 611, an output terminal of the operational amplifier 611 is connected to a gate of the first N-type transistor NM1 and a gate of the second N-type transistor NM2, the reference voltages are common mode voltages of standard differential signals output by the interface circuit in different modes, and the common mode feedback unit 610 outputs the common mode voltage output by the second circuit 53 to the operational amplifier 611.
The common mode feedback unit 610 and the operational amplifier 611 clamp the differential signal output by the second circuit 53, and output a bias voltage to bias the first N-type transistor NM1 and the second N-type transistor NM2, so as to control the resistance values of the first variable resistor RX1 and the second variable resistor RX2, and enable the second circuit 53 to output the corresponding differential signal.
It can be seen that fig. 6 is an example of a specific circuit implementation of fig. 5, where PM1 and PM2 are two PMOS switches, respectively controlled by the full swing differential signal DIN/DIP to select the current path and turn on one of them; the variable resistors Rx1 and Rx2 are realized by the series connection of a fixed resistor and an NMOS; clamping the common mode voltage of the differential signal output by the second circuit by using a common mode feedback unit and an operational amplifier (OP), and then respectively biasing NM1 and NM2 by outputting a bias voltage Vb to obtain a required impedance Rx, which is a negative feedback process, wherein if the differential common mode voltage Vcom output by the second circuit is greater than Vref, the bias voltage Vb output by the operational amplifier is increased, so that the resistance values of the variable resistors Rx1 and Rx2 are reduced, the differential common mode voltage Vcom output by the second circuit is reduced, and the process is repeated until the operational amplifier outputs a stable bias voltage Vb, which meets the requirement. From the analysis in FIG. 5, in LVDS mode, I _ LVDS is selected to be 8.5mA, Vref _ LVDS is selected to be 1.25 v; in the DSI mode, I _ DSI is selected to be 8mA and Vref _ DSI is selected to be 0.2 v. Specifically, when the fixed resistance value of the variable resistor is 0, the variable resistors Rx1 and Rx2 are implemented by using NMOS alone, as shown in fig. 8.
The impedance control circuit 51 in fig. 6 controls the variable resistors Rx1 and Rx2 by using analog signals, and the impedance control circuit 51 may also be implemented by using a digital calibration method, as shown in fig. 9, the impedance control circuit 51 includes a calibration current source 90, a calibration variable resistor Rx0, a comparator 91, an adder-subtractor 92 and a calibration controller 93, where:
the calibration current source 90 is configured to generate a calibration current Ic and output the calibration current Ic to the calibration variable resistor RX0, where RX0 has the same resistance as RX1 and RX2 in fig. 5, and the implementation manner is also completely the same, and preferably, RX0, RX1, and RX2 may all be implemented by using the same M NMOS transistors in parallel, where M is specifically determined according to the actual situation.
The positive input end of the comparator 91 is connected to the output end of the calibration current source 90 and the first end of the calibration variable resistor RX0, the negative input end of the comparator 91 inputs calibration voltages in different modes for comparing the input voltage values and outputting the comparison result to the adder-subtractor 92, and the calibration voltage is the product of the standard variable resistance value and the calibration current value in different modes.
The input end of the adder-subtractor 92 is connected to the output end of the comparator 91, and is configured to generate a corresponding add-subtract command according to the input comparison result, and output the add-subtract command to the calibration controller 93.
The input end of the calibration controller 93 is connected with the output end of the adder-subtractor 92, the output end of the calibration controller 93 is connected with the third end of the standard variable resistor RX0, the third end of the first variable resistor RX1 and the third end of the second variable resistor RX2, and the calibration controller is used for controlling the resistance values of the standard variable resistor RX0, the first variable resistor RX1 and the second variable resistor RX2 according to the input addition and subtraction instructions to enable the second circuit to output corresponding differential signals, wherein the second end of the standard variable resistor RX0 is connected with a source ground power supply.
As can be seen from fig. 9, Ic is a calibration current, flowing through Rx0 generates a reference voltage Va, Va varies with the variation of Rx0, a calibration voltage Vc is selected according to different operation modes and compared with Va, the comparison result is sent to the adder-subtractor 92, the adder-subtractor 92 generates a corresponding addition-subtraction command according to the input comparison result and outputs the addition-subtraction command to the calibration controller 93, and the calibration controller 93 generates and outputs a calibration code Cal _ code. Rx0, Rx1 and Rx2 are realized by M unit resistors R0 in parallel, preferably, the unit resistor R0 can be realized by an NMOS tube, and the value of M is controlled by the calibration output code Cal _ code. According to the output result of the comparator 91, the calibration output code Cal _ code is subjected to the operation of adding 1 or subtracting 1 at each rising edge of the calibration clock Cal _ clock, and the calibration controller 93 finally obtains the calibration code closest to the target resistance value by judgment. The number of bits of the calibration code Cal code may be chosen according to an acceptable calibration accuracy. For example, when the number M of cell resistors is 31, the Cal _ code may be selected to be 5 bits, each bit and all resistor cells may be controlled in a ratio of 1:2:4:8:16, respectively. If Ic is 20mA, in the DSI mode, typically, Rx1 is Rx2 is Rx 50 Ω, and Vc is Rx Ic 50mV 20 is 1000mV, if Va is greater than Vc, the comparator 91 outputs the comparison result to the adder-subtractor 92, the comparator 91 outputs the addition and subtraction command of +1 according to the comparison result, otherwise, the addition and subtraction command of-1 is output, the calibration controller 93 executes the operation of +1 on the calibration code corresponding to the current resistance of the variable resistor Rx0 according to the current addition and subtraction command of +1, so as to change the resistance of the calibration resistor Rx0, increase the number of parallel units of the variable resistor, decrease the resistance of Rx0, decrease the value of the reference voltage Va, and so forth, when the calibration code Cal _ code is frequently between two values, it is assumed that when Cal _ code jumps 2 times between 10000 and 10001, the selected resistance of Cal _ code is 10001, and then the calibration code R5916 is large as the calibration code Rx 4617, further, the resistance values of the first variable resistor RX1 and the second variable resistor RX2 are determined, and RX0 is equal to RX1 and RX2, that is, the first variable resistor RX1 and the second variable resistor RX2 are implemented by a parallel connection of 17 unit resistors R0.
To sum up, the embodiment of the present invention provides a low voltage differential signaling LVDS interface and display differential DSI interface multiplexing circuit, including: the data clock synchronization circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit; the data clock selection circuit is connected with the mode control circuit and the data clock synchronization circuit, and is used for selecting a current interface mode under the mode control of the mode control circuit, receiving an externally input data signal and a clock signal and supplying the data signal and the clock signal to the data clock synchronization circuit; the data clock synchronization circuit is connected with the mode control circuit and the data conversion circuit and is used for synchronizing the data signal and the clock signal under the mode control of the mode control circuit and providing the synchronized data signal and the synchronized clock signal to the data conversion circuit; the data conversion circuit is connected with the mode control circuit and the driving circuit and used for converting the synchronized data signals from parallel to serial under the mode control of the mode control circuit and outputting differential data signals to the driving circuit; the driving circuit is connected with the mode control circuit and used for controlling the amplitude range and the common mode range of the output signal by using the differential data signal under the mode control of the mode control circuit, so that the multiplexing of the LVDS interface and the DSI interface is realized, the number of packaging pins can be reduced, the packaging cost is reduced, and the interface resource waste is reduced.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (9)
1. A low-voltage differential signaling (LVDS) interface and display Differential Signaling (DSI) interface multiplexing circuit, comprising: the data clock synchronization circuit comprises a data clock selection circuit, a data clock synchronization circuit, a mode control circuit, a data conversion circuit and a driving circuit; wherein,
the data clock selection circuit is connected with the mode control circuit and the data clock synchronization circuit, and is used for selecting a current interface mode under the mode control of the mode control circuit, receiving an externally input data signal and a clock signal and providing the externally input data signal and the clock signal to the data clock synchronization circuit;
the data clock synchronization circuit is connected with the mode control circuit and the data conversion circuit, and is used for synchronizing the data signal and the clock signal under the mode control of the mode control circuit and providing the synchronized data signal and clock signal to the data conversion circuit;
the data conversion circuit is connected with the mode control circuit and the drive circuit and is used for converting the synchronized data signals from parallel to serial under the mode control of the mode control circuit and outputting differential data signals to the drive circuit;
and the driving circuit is connected with the mode control circuit and is used for controlling the amplitude range and the common mode range of the output signal by using the differential data signal under the mode control of the mode control circuit.
2. The multiplexing circuit of claim 1 wherein the drive circuit comprises a first circuit, an impedance control circuit, a first switch set, and a second circuit;
the first circuit is connected with the mode control circuit and the first switch group and is used for outputting current of a corresponding mode to the first switch group under the mode control of the mode control circuit;
the first switch group is connected with the data conversion circuit and used for receiving the current output by the first circuit under the control of the differential data signal and outputting the current to the second circuit;
the second circuit is connected with the first switch group and the impedance control circuit and used for receiving the current output by the first circuit and shunting the current under the control of the impedance control circuit so as to output corresponding differential signals.
3. The multiplexing circuit of claim 2 wherein the second circuit comprises a first variable resistor, a second variable resistor, and a first resistor, the first switch set comprising a first switch and a second switch;
a first end of the first resistor is connected with a first end of the first variable resistor and the first switch to serve as a negative output end of the differential signal, a second end of the first resistor is connected with a first end of the second variable resistor and the second switch to serve as a positive output end of the differential signal, and the second end of the first variable resistor and the second end of the second variable resistor are both connected with a source electrode ground power supply;
the impedance control circuit is respectively connected with the third end of the first variable resistor and the third end of the second variable resistor and is used for controlling the resistance values of the first variable resistor and the second variable resistor to enable the second circuit to output corresponding differential signals.
4. The multiplexing circuit of claim 3, further comprising:
the grid electrode of the first switch is connected with the negative output end of the differential data signal output by the data conversion circuit, the source electrode of the first switch is connected with the output end of the first circuit, the drain electrode of the first switch is connected with the first end of the first resistor, the grid electrode of the second switch is connected with the positive output end of the differential data signal output by the data conversion circuit, the source electrode of the second switch is connected with the output end of the first circuit, and the drain electrode of the second switch is connected with the second end of the first resistor;
the first switch and the second switch are turned on under the control of a differential data signal output by the data conversion circuit;
wherein the first switch and the second switch are both P-type transistors.
5. The multiplexing circuit of claim 3, further comprising:
the grid electrode of the first switch is connected with the positive output end of the differential data signal output by the data conversion circuit, the source electrode of the first switch is connected with the output end of the first circuit, the drain electrode of the first switch is connected with the first end of the first resistor, the grid electrode of the second switch is connected with the negative output end of the differential data signal output by the data conversion circuit, the source electrode of the second switch is connected with the output end of the first circuit, and the drain electrode of the second switch is connected with the second end of the first resistor;
the first switch and the second switch are turned on under the control of a differential data signal output by the data conversion circuit;
wherein the first switch and the second switch are both N-type transistors.
6. The multiplexing circuit of claim 3, 4 or 5 wherein the first variable resistance comprises a second resistance and a first N-type transistor, the second variable resistance comprises a third resistance and a second N-type transistor, wherein the second resistor and the third resistor have the same resistance value and are larger than 0, the first end of the second resistor is connected with the first end of the first resistor, the source of the first N-type transistor is connected with the second end of the second resistor, the first end of the third resistor is connected with the second end of the first resistor, the source electrode of the second N-type transistor is connected with the second end of the third resistor, the drain electrodes of the first N-type transistor and the second N-type transistor are both connected with the source electrode ground power supply, the gates of the first N-type transistor and the second N-type transistor are connected with the impedance control circuit;
the impedance control circuit comprises a common-mode feedback unit and an operational amplifier, wherein the positive input end of the common-mode feedback unit is connected with the second end of the first resistor, the negative input end of the common-mode feedback unit is connected with the first end of the first resistor, the output end of the common-mode feedback unit is connected with the positive input end of the operational amplifier, reference voltages in different modes are input into the negative input end of the operational amplifier, the output end of the operational amplifier is respectively connected with the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor, and the reference voltages are common-mode voltages of standard differential signals output by the interface circuit in different modes;
the common mode feedback unit and the operational amplifier clamp the differential signal output by the second circuit and output a bias voltage to bias the first N-type transistor and the second N-type transistor so as to control the resistance values of the first variable resistor and the second variable resistor, so that the second circuit outputs a corresponding differential signal.
7. The multiplexing circuit of claim 3, 4 or 5 wherein the first variable resistor is a third N-type transistor, the second variable resistor is a fourth N-type transistor, a source of the fourth N-type transistor is connected to the first terminal of the first resistor, a source of the second N-type transistor is connected to the second terminal of the first resistor, drains of the first N-type transistor and the second N-type transistor are both connected to a source ground supply, and gates of the first N-type transistor and the second N-type transistor are both connected to the impedance control circuit;
the impedance control circuit comprises a common-mode feedback unit and an operational amplifier, wherein the positive input end of the common-mode feedback unit is connected with the second end of the first resistor, the negative input end of the common-mode feedback unit is connected with the first end of the first resistor, the output end of the common-mode feedback unit is connected with the positive input end of the operational amplifier, reference voltages in different modes are input into the negative input end of the operational amplifier, the output end of the operational amplifier is respectively connected with the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor, and the reference voltages are common-mode voltages of standard differential signals output by the interface circuit in different modes;
the common mode feedback unit and the operational amplifier clamp the differential signal output by the second circuit and output a bias voltage to bias the first N-type transistor and the second N-type transistor so as to control the resistance values of the first variable resistor and the second variable resistor, so that the second circuit outputs a corresponding differential signal.
8. The multiplexing circuit of claim 3, 4 or 5 wherein the impedance control circuit comprises a calibration current source, a calibration variable resistor, a comparator, an adder-subtractor and a calibration controller,
the calibration current source is used for generating calibration current and outputting the calibration current to the calibration variable resistor;
the positive input end of the comparator is connected with the output end of the calibration current source and the first end of the calibration variable resistor, the negative input end of the comparator inputs calibration voltages in different modes, the calibration voltages are used for comparing the magnitude of the input voltage values and outputting a comparison result to the adder-subtractor, and the calibration voltages are the products of standard variable resistance values and calibration current values in different modes;
the input end of the adder-subtractor is connected with the output end of the comparator and used for generating a corresponding addition-subtraction instruction according to an input comparison result and outputting the addition-subtraction instruction to the calibration controller;
the input end of the calibration controller is connected with the output end of the adder-subtractor, the output end of the calibration controller is connected with the third end of the calibration variable resistor, the third end of the first variable resistor and the third end of the second variable resistor, and the calibration controller is used for controlling the resistance values of the calibration variable resistor, the first variable resistor and the second variable resistor according to an input addition and subtraction instruction to enable the second circuit to output corresponding differential signals, wherein the second end of the standard variable resistor is connected with a source ground power supply.
9. The multiplexing circuit of claim 8 wherein the calibration variable resistor is a parallel connection of M unit resistors, the unit resistors are NMOS transistors with a set resistance, and M is a set positive integer.
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| CN108924459A (en) * | 2018-08-06 | 2018-11-30 | 上海顺久电子科技有限公司 | A kind of output interface circuit and device |
| CN108924459B (en) * | 2018-08-06 | 2021-04-13 | 上海顺久电子科技有限公司 | Output interface circuit and device |
| CN109683836B (en) * | 2018-12-04 | 2022-04-19 | 珠海妙存科技有限公司 | Driving device compatible with hardware interfaces of various display protocols |
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| CN113225064A (en) * | 2020-01-21 | 2021-08-06 | 炬芯科技股份有限公司 | Pin control circuit and integrated chip |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN116561035B (en) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| WO2025139469A1 (en) * | 2023-12-27 | 2025-07-03 | 上海复旦微电子集团股份有限公司 | Buffer circuit for high-speed clock and data multiplexing |
| CN117978934A (en) * | 2024-04-02 | 2024-05-03 | 杭州方千科技有限公司 | Light supplementing synchronous signal circuit and electronic equipment thereof |
| CN117978934B (en) * | 2024-04-02 | 2024-05-31 | 杭州方千科技有限公司 | Light supplementing synchronous signal circuit and electronic equipment thereof |
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