CN106406974B - High-performance timer implementation method for virtual machine and virtual machine - Google Patents

Abstract

The invention provides a high-performance timer implementation method for a virtual machine and the virtual machine, wherein the method comprises the following steps: the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380; the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing; the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue; and the high-precision timer module acquires a timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core register. Through the implementation of the invention, in the process of generating the timer configuration message and writing the timer configuration message into the timer, the hardware can decode the instruction and directly transmit the offset address and the written value of the register to the Hypervisor for processing, thereby essentially eliminating the time bottleneck generated by decoding the software instruction.

Description

A high-performance timer implementation method for virtual machine, virtual machine

technical field

The invention relates to the field of high-performance timing of virtual machines, in particular to a method for realizing high-performance timers for virtual machines and a virtual machine.

Background technique

At present, in the application of virtualization field, virtual machine performance is a key indicator that everyone pays attention to. Whether a virtual machine can have the same performance as a physical machine has been a difficult problem to solve in the field of virtualization for a long time. Due to the high real-time requirements of the services it carries, virtualization has more stringent requirements on various performance indicators after virtualization, and the most critical factor affecting the performance of virtual machines is the accuracy of virtual machine timers.

The existing embedded virtualized high-precision timer processing flow is: GuestOS configures the TimerInitial Count register timing value with an offset of 0x380; the hardware writes the 0x380 register to generate VM_Exit to the Hypervisor for instruction decoding and then writes to the real hardware register; the system is returned by the Hypervisor to GuestOS continues to run; the high-precision timer is timed to the hardware generation interrupt and VM_Exit occurs to the Hypervisor to process the interrupt, and the interrupt is converted into a virtual interrupt and injected into the IDT interrupt processing flow of the GuestOS.

There are two key factors affecting the performance of the embedded virtual machine's high-precision timer in this method: the first is that every time the timing value is written to the 0x380 register, a VM_Exit will be generated to the Hypervisor to process and generate an instruction decoding operation to form a performance bottleneck; the second is that When the timing is up, the high-precision timer will issue an interrupt to generate VM_Exit to be processed by the Hypervisor, and then inject the interrupt into the GuestOS IDT interrupt processing routine. This process increases the overhead of VM_Exit to Hypervisor switching and hardware interrupt processing, which is more accurate for the virtual machine timer. big performance impact.

Therefore, how to provide a high-performance timer implementation method with higher timer precision is a technical problem to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

The present invention provides a high-performance timer implementation method and a virtual machine for a virtual machine, so as to solve the problem of poor timer precision of the virtual machine.

The present invention provides a high-performance timer implementation method for a virtual machine, which includes: partitioning GuestOS to generate timing requirements, and writing the timing value to high-precision timer register 0x380; partitioning CPU capturing and writing 0x380 register privilege instruction operation to generate VM_Exit to the Hypervisor for processing; the embedded Hypervisor obtains the write register offset and the write value through the CPU, adds it to the timer configuration message, and sends it to the high-speed communication queue; the high-precision timer module obtains the timer configuration message from the high-speed communication queue, and Write to hardware core registers.

Further, when there are multiple partitions, the method further includes: the embedded hypervisor integrates the core id where the partition VCPU that initiates the register write operation is located, and the address of the corresponding hardware Posted Interrupt descriptor, and adds it to the timer configuration message.

Further, after sending the timer configuration message to the high-speed communication queue, it also includes: informing the high-precision timer module that the register write operation is completed; the high-precision timer module obtains the timer from the high-speed communication queue after receiving the notification. Configuration messages.

Further, the high-precision timer module writes the timer configuration message into the hardware core register, including: the high-precision timer module parses the timer configuration message, obtains the write register offset and write value, and determines the timer offset and timing. Value, written to the hardware Core timer.

Further, when there are multiple partitions, it also includes: the high-precision timer module parses the timer configuration message, obtains the write register offset and write value, the core id where the partition VCPU that initiates the register write operation is located, and the corresponding hardware Posted Interrupt descriptor address, the timer offset and timing value are the core id where the VCPU is located, and the hardware Posted Interrupt descriptor address is stored in the virtual machine timer model; the minimum timing value found is written to the hardware Core timer.

Further, it also includes: judging whether the hardware Core timer is in an untimed state; if the hardware Core timer is in an untimed state, the high-precision timer module searches for the virtual machine timer data model, and writes the found minimum timing value into Hardware core timer; if the hardware core timer is in the timing state, the write operation of the hardware core timer is not performed.

Further, it also includes: disabling the high-precision timer through the hypervisor for the core of the deployed partition virtual machine.

Further, it also includes: selecting a core, and running the embedded Hypervisor high-precision timer module in the core.

Further, it also includes: constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module in the embedded Hypervisor software layer.

Further, it also includes: when the hardware core timer arrives at the timing, sending an interrupt notification to the high-precision timer module, the high-precision timer module writes the high-precision timer interrupt flag to the partition PI descriptor, and sends the PI physical interrupt to the partition core. .

Further, when there are multiple partitions, it also includes: the high-precision timer module obtains the core id of the VCPU of the virtual machine and the PI descriptor address information of the virtual machine that are timed from the virtual machine timer model, according to the obtained virtual machine. The PI descriptor address writes the high-precision timer interrupt flag to the corresponding PI descriptor, and sends the PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.

Further, it also includes: the high-precision timer module deletes the partition timer data that has completed timing interrupt injection from the virtual machine timer model, and reads the next minimum timing value from the virtual machine timer data model. The next minimum timing value of the virtual machine is written to the hardware Core timer.

The present invention provides a virtual machine, which includes: a partitioned GuestOS, which is used to generate timing requirements and write timing values to a high-precision timer register 0x380; a partitioned CPU, which is used to capture and write a privileged instruction operation of the 0x380 register, and generate VM_Exit to be processed by the Hypervisor ; Embedded Hypervisor, used to obtain the write register offset and write value through the CPU, add it to the timer configuration message, and send it to the high-speed communication queue; High-precision timer module, used to obtain the timer configuration report from the high-speed communication queue. text, and write to the hardware core register.

Further, when there are multiple partitions, the embedded hypervisor is also used to integrate the core id where the partition VCPU that initiates the register write operation is located, and the corresponding hardware Posted Interrupt descriptor address, and add it to the timer configuration message.

Further, after the embedded hypervisor sends the timer configuration message to the high-speed communication queue, it is also used to notify the high-precision timer module that the write register operation is completed; The timer configuration message is obtained from the communication queue.

Further, the high-precision timer module is used to parse the timer configuration message, obtain the write register offset and write value, determine the timer offset and timing value, and write the hardware Core timer.

Further, when there are multiple partitions, the high-precision timer module is also used to parse the timer configuration message, obtain the write register offset and write value, the core id of the partition VCPU that initiates the register write operation, and the corresponding hardware PostedInterrupt The descriptor address is stored in the virtual machine timer model with the timer offset and timing value as the core id where the VCPU is located, and the hardware PostedInterrupt descriptor address; the minimum timing value found is written into the hardware Core timer.

Further, the high-precision timer module is also used to determine whether the hardware core timer is in an untimed state; if the hardware core timer is in an untimed state, look up the virtual machine timer data model, and write the found minimum timing value into Hardware core timer; if the hardware core timer is in the timing state, the write operation of the hardware core timer is not performed.

Further, the core of the deployed partition virtual machine is also used to turn off the high-precision timer through the hypervisor.

Further, the embedded hypervisor is also used to select a core, and the embedded hypervisor high-precision timer module should be run in the core.

Further, the embedded Hypervisor is also used to construct a high-speed communication channel between each partition virtual machine and the high-precision timer module at the software layer.

Further, the hardware core timer is also used to send an interrupt notification to the high-precision timer module when the hardware core timer arrives at the timing; the high-precision timer module is also used to write the high-precision timer interrupt flag to the partition PI descriptor, Send a PI physical interrupt to the partition core.

Further, when there are multiple partitions, the high-precision timer module is also used to obtain the core id of the VCPU of the virtual machine and the PI descriptor address information of the virtual machine from the virtual machine timer model. The PI descriptor address writes the high-precision timer interrupt flag to the corresponding PI descriptor, and sends the PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.

Further, the high-precision timer module is also used to delete the partition timer data that has completed timing interrupt injection from the virtual machine timer model, and read the next minimum timing value from the virtual machine timer data model. The next minimum timing value of the virtual machine is written to the hardware Core timer.

Beneficial effects of the present invention:

The present invention provides a new high-performance timer implementation method. In the process of generating a timer configuration message and writing it to the timer, it is not necessary to write the 0x380 register in hardware as in the prior art to generate VM_Exit to the Hypervisor for instruction decoding. Write the real hardware register, so that GuestOS does not need software to decode the instruction when writing the 0x380 register. The hardware will decode the instruction and directly pass the register offset address and write value to the Hypervisor in the VM_Exit event, which essentially eliminates the need for software. The time bottleneck caused by instruction decoding; further, after the timer arrives, the high-precision timer module first writes the high-precision timer interrupt flag to the Posted Interrupt descriptor, and then sends the Posted Interrupt inter-core interrupt to the corresponding core id, Intel Posted The Interrupt hardware virtualization mechanism will automatically complete the interrupt injection into the high-precision timers of different partitioned virtual machines according to the above configuration. No VM_Exit will be generated during this process, nor will the Hypervisor intervene in interrupt processing, so the performance can reach the same level as the physical machine. .

Description of drawings

FIG. 1 is a schematic structural diagram of a virtual machine provided by a first embodiment of the present invention;

2 is a flowchart of a method for implementing a high-performance timer provided by a second embodiment of the present invention;

FIG. 3 is a flowchart of a method for implementing a high-performance timer provided by a third embodiment of the present invention.

Detailed ways

The present invention will now be further explained by means of specific embodiments in conjunction with the accompanying drawings.

First embodiment:

FIG. 1 is a schematic structural diagram of a virtual machine provided by the first embodiment of the present invention. It can be seen from FIG. 1 that, in this embodiment, the virtual machine 1 provided by the present invention includes:

Partition GuestOS11, which is used to generate timing requirements and write timing values to high-precision timer register 0x380;

Partition CPU12, used to capture the write 0x380 register privileged instruction operation, and generate VM_Exit to the Hypervisor for processing;

Embedded Hypervisor13, used to obtain the write register offset and write value through the CPU, add it to the timer configuration message, and send it to the high-speed communication queue;

The high-precision timer module 14 is used to obtain the timer configuration message from the high-speed communication queue and write it into the hardware core timer 15;

The hardware core timer 15 is used to execute the timer.

In some embodiments, when there are multiple partitions, the embedded Hypervisor 13 in the above embodiment is also used to integrate the core id where the partition VCPU that initiates the register write operation is located, and the corresponding hardware Posted Interrupt descriptor address, and add it to the timing server configuration message.

In some embodiments, after the embedded Hypervisor 13 in the above-mentioned embodiment sends the timer configuration message to the high-speed communication queue, it is further used to notify the high-precision timer module that the register write operation is completed; the high-precision timer module is also used to After receiving the notification, obtain the timer configuration message from the high-speed communication queue.

In some embodiments, the high-precision timer module 14 in the above embodiment is used to parse the timer configuration message, obtain the write register offset and write value, determine the timer offset and timing value, and write the hardware Core timing. device.

In some embodiments, when there are multiple partitions, the high-precision timer module 14 in the above embodiment is also used to parse the timer configuration message, obtain the offset and write value of the write register, and initiate the partition of the register write operation. The core id where the VCPU is located and the address of the corresponding hardware Posted Interrupt descriptor are stored in the virtual machine timer model with the timer offset and timing value as the core id where the VCPU is located and the hardware Posted Interrupt descriptor address; the minimum timing value found is written Enter hardware Core timer 15.

In some embodiments, the high-precision timer module 14 in the above embodiment is also used to determine whether the hardware core timer 15 is in an untimed state; if the hardware core timer is in an untimed state, look up the virtual machine timer data model , and write the found minimum timing value into the hardware Core timer; if the hardware Core timer is in the timing state, the writing operation of the hardware Core timer is not performed.

In some embodiments, the core of the deployment partition virtual machine in the above embodiment is also used to disable the high-precision timer through the Hypervisor 13 .

In some embodiments, the embedded hypervisor 13 in the above-mentioned embodiment is further used to select a core, and the embedded hypervisor high-precision timer module 14 is run on the core.

In some embodiments, the embedded Hypervisor 13 in the above-mentioned embodiment is also used to construct a high-speed communication channel between each partition virtual machine and the high-precision timer module 14 at the software layer.

In some embodiments, the hardware core timer 15 in the above-mentioned embodiment is also used to send an interrupt notification to the high-precision timer module 14 when the hardware core timer arrives at the timing; the high-precision timer module 14 is also used to send an interrupt notification to the partition PI The descriptor writes the high-precision timer interrupt flag and sends a PI physical interrupt to the partition core.

In some embodiments, when there are multiple partitions, the high-precision timer module 14 in the above embodiment is further configured to obtain the core id of the VCPU of the virtual machine and the description of the virtual machine PI from the virtual machine timer model. address information, write the high-precision timer interrupt flag to the corresponding PI descriptor according to the obtained virtual machine PI descriptor address, and send the PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.

In some embodiments, the high-precision timer module 14 in the above-mentioned embodiment is further configured to delete the partition timer data that has completed the timing interrupt injection from the virtual machine timer model, and read the following data from the virtual machine timer data model. A minimum timing value, write the next minimum timing value of the virtual machine read to the hardware Core timer.

Second embodiment:

FIG. 2 is a flowchart of a method for implementing a high-performance timer provided by a second embodiment of the present invention. As can be seen from FIG. 2, in this embodiment, the method for implementing a high-performance timer provided by the present invention includes the following steps:

S201: The partitioned GuestOS generates a timing request, and writes the timing value to the high-precision timer register 0x380;

S202: The partition CPU captures the write 0x380 register privileged instruction operation, and generates VM_Exit to the Hypervisor for processing;

S203: The embedded hypervisor obtains the write register offset and write value through the CPU, adds it to the timer configuration message, and sends it to the high-speed communication queue;

S204: The high-precision timer module obtains the timer configuration message from the high-speed communication queue, and writes it into the hardware core register.

In some embodiments, when there are multiple partitions, the method in the above embodiment further includes: the embedded hypervisor integrates the core id where the partition VCPU that initiates the register write operation is located, and the address of the corresponding hardware Posted Interrupt descriptor, and adds it to Timer configuration message.

In some embodiments, after the method in the above-mentioned embodiment sends the timer configuration message to the high-speed communication queue, the method further includes: notifying the high-precision timer module that the register write operation is completed; after the high-precision timer module receives the notification , and obtain the timer configuration message from the high-speed communication queue.

In some embodiments, the high-precision timer module in the above embodiment writes the timer configuration message into the hardware core register, including: the high-precision timer module parses the timer configuration message, and obtains the write register offset and write value. , determine the timer offset and timing value, and write to the hardware Core timer.

In some embodiments, when there are multiple partitions, the method in the above embodiment further includes: the high-precision timer module parses the timer configuration message, obtains the write register offset and write value, and initiates the partition of the register write operation. The core id where the VCPU is located and the address of the corresponding hardware Posted Interrupt descriptor are stored in the virtual machine timer model with the timer offset and timing value as the core id where the VCPU is located and the hardware Posted Interrupt descriptor address; the minimum timing value found is written Enter the hardware Core timer.

In some embodiments, the method in the above embodiment further includes: judging whether the hardware core timer is in an untimed state; if the hardware core timer is in an untimed state, the high-precision timer module searches for the virtual machine timer data model, Write the found minimum timing value to the hardware core timer; if the hardware core timer is in the timing state, the writing operation of the hardware core timer is not performed.

In some embodiments, the method in the above embodiment further includes: disabling the high-precision timer through the hypervisor for the core of the deployed partition virtual machine.

In some embodiments, the method in the above embodiment further includes: selecting a core, and running the embedded hypervisor high-precision timer module on the core.

In some embodiments, the method in the above embodiment further includes: constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module in the embedded hypervisor software layer.

In some embodiments, the method in the above embodiment further includes: when the hardware core timer arrives at the timing, sending an interrupt notification to the high-precision timer module, and the high-precision timer module writes the high-precision timer interrupt to the partition PI descriptor Flag to send PI physical interrupt to partition core.

In some embodiments, when there are multiple partitions, the method in the above embodiment further includes: the high-precision timer module obtains the core id of the VCPU of the virtual machine and the PI description of the virtual machine to be timed from the virtual machine timer model. address information, write the high-precision timer interrupt flag to the corresponding PI descriptor according to the obtained virtual machine PI descriptor address, and send the PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.

In some embodiments, the method in the above-mentioned embodiment further includes: the high-precision timer module deletes the partition timer data that has completed the timing interrupt injection from the virtual machine timer model, and reads the following data from the virtual machine timer data model. A minimum timing value, write the next minimum timing value of the virtual machine read to the hardware Core timer.

The present invention will now be further explained in conjunction with specific application scenarios.

Third embodiment:

FIG. 3 is a flowchart of a method for implementing a high-performance timer provided by a third embodiment of the present invention. As can be seen from FIG. 3, in this embodiment, the method for implementing a high-performance timer provided by the present invention includes the following steps:

S301: The virtual machine is initialized.

Initialization includes the following steps:

The core of the deployed partition virtual machine closes the high-precision timer through the hypervisor to prevent unnecessary external interruptions;

Separate a core to run the embedded Hypervisor high-precision timer module, start the core high-precision timer hardware function, and this module provides clock sources for different partition high-precision timers;

Build a high-speed communication channel between each partition virtual machine and the high-precision timer module in the embedded Hypervisor software layer, and provide a mechanism for writing the timing values of the 0x380 registers of different partitions to the high-precision timer module;

The embedded Hypervisor configures the partition virtual machine hardware APIC Register Virtualization function. The purpose is to allow the GuestOS to write the 0x380 register without software decoding the instruction. The hardware will perform the instruction decoding and directly pass the register offset address and write value to the Hypervisor in the VM_Exit event. processing, which essentially eliminates the time bottleneck caused by software instruction decoding;

S302: The partition generates a timer configuration message.

The embedded Hypervisor captures the write processing operation of the 0x380 register by the GuestOS and does not directly write the hardware register of the current core, but writes the timing value, the current core id and the corresponding PostedInterrupt descriptor address into the high-precision timer module through the high-speed communication channel.

Specifically, this step includes:

The high-precision GuestOS generates timing requirements to write the timing value to the high-precision timer register 0x380;

The CPU hardware captures the write 0x380 register privileged instruction operation to generate VM_Exit to the Hypervisor for processing;

The embedded hypervisor obtains the write register offset and write value through the CPU hardware, and integrates the core id of the partition VCPU that initiates the register write operation with the corresponding hardware Posted Interrupt descriptor address, and then packages the timer configuration message and sends it to the high-speed communication queue;

The embedded Hypervisor sends an event to notify the high-precision timer module that the register write operation is completed;

The high-precision timer module obtains the timer configuration message from the high-speed communication queue.

S303: Write the timing value into the hardware core timer.

The high-precision timer module receives high-precision timer messages from the high-speed communication channel from the virtual machine configuration of each partition, updates the internal data model, and performs calculation and analysis. Finally, the configuration of the high-precision timer of the core hardware where the high-precision timer module is located is completed. .

Specifically, this step includes:

The high-precision timer module receives the Hypervisor message event channel notification, which proves that a virtual machine partition has written the high-precision timer regular message at this time, and is ready to read the content of the regular message from the communication queue;

The high-precision timer module parses the message event information to obtain the high-speed communication queue number, and reads the high-precision timer regular message written by the virtual machine partition from the queue;

The high-precision timer module analyzes the read virtual machine configuration timer message, and stores the VCPU running coreid and hardware Posted Interrupt descriptor address in the message to the virtual machine timer data with the timer offset and timing as the index. Model;

If the current hardware Core timer is in an untimed state, the high-precision timer module searches the virtual machine timer data model, and writes the found minimum timing value into the hardware Core timer; if the current hardware Core timer is in a timed state, no Write operation of the hardware core timer.

S304: The hardware core timer arrives regularly, and an interrupt is generated.

After the high-precision timer of the core hardware where the high-precision timer module is located, trigger the high-precision timer module to run, and find the Posted Interruptdescriptor address and core id of the partition virtual machine that needs to be processed regularly through the internal data model. After finding the data, send the Posted Interrupt first. The descriptor writes the high-precision timer interrupt flag, and then sends the Posted Interrupt inter-core interrupt to the corresponding core id. The Intel PostedInterrupt hardware virtualization mechanism will automatically complete the interrupt injection to the high-precision timers of different partition virtual machines according to the above configuration. This process There will be no VM_Exit and no Hypervisor intervention in interrupt processing, so the performance can reach the same level as the physical machine.

Specifically, this step includes:

The hardware Core timer is scheduled to send an interrupt to notify the high-precision timer module;

The high-precision timer module obtains the timed related virtual machine coreid and PI descriptor address information from the virtual machine timer data model;

Write the high-precision timer interrupt flag to the corresponding PI descriptor according to the virtual machine PI descriptor address obtained from the data model;

Send a PI physical interrupt to the core according to the coreid of the VCPU obtained from the data model;

When the software hypervisor completes this step, the hardware will automatically read the high-precision timer interrupt flag from the PI descriptor and automatically generate a high-precision timer interrupt and jump to the GuestOS interrupt processing routine for execution. VM_Exit will not be generated in the whole process. So the performance is exactly the same as the physical machine.

S305: Write the next timing information in the hardware core timer.

The high-precision timer module deletes the partition timer data that has completed timing interrupt injection from the virtual machine timer model, and reads the next minimum timing value from the virtual machine timer data model; the high-precision timer module will read the virtual The next minimum timing value of the machine is written into the hardware Core high-precision timer.

To sum up, through the implementation of the present invention, there are at least the following beneficial effects:

In the process of generating the timer configuration message and writing it to the timer, it is not necessary to write the 0x380 register by hardware as in the prior art to generate VM_Exit to the hypervisor for instruction decoding and then write to the real hardware register. In this way, the GuestOS does not require software to write the 0x380 register. For instruction decoding, the hardware will perform instruction decoding and directly pass the register offset address and write value to the Hypervisor for processing in the VM_Exit event, which essentially eliminates the time bottleneck caused by software instruction decoding;

Further, after the timer arrives, the high-precision timer module first writes the high-precision timer interrupt flag to the Posted Interruptdescriptor, and then sends the Posted Interrupt inter-core interrupt to the corresponding core id. The Intel Posted Interrupt hardware virtualization mechanism will automatically The above configuration completes the interrupt injection to the high-precision timers of different partition virtual machines. In this process, no VM_Exit is generated and no Hypervisor is required to intervene in interrupt processing, so the performance can reach the same level as the physical machine;

Further, the core of the deployed partition virtual machine closes the high-precision timer through the hypervisor to prevent unnecessary external interruptions;

Further, separate a core to run the embedded Hypervisor high-precision timer module, start the core high-precision timer hardware function, and this module provides clock sources for different partition high-precision timers;

Further, a high-speed communication channel between each partition virtual machine and the high-precision timer module is constructed in the embedded hypervisor software layer, and a mechanism for writing the timing values of the 0x380 registers of different partitions to the high-precision timer module is provided.

The above are only specific embodiments of the present invention, and do not limit the present invention in any form. Any simple modifications, equivalent changes, combinations or modifications made to the above embodiments according to the technical essence of the present invention still belong to the present invention. The protection scope of the technical solution of the invention.

Claims (24)

1. A high-performance timer implementation method for a virtual machine is characterized by comprising the following steps:

the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380;

the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing;

the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue;

and the high-precision timer module acquires the timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core timer.

2. The high performance timer implementing method of claim 1, when there are multiple partitions, further comprising: the embedded Hypervisor integrates the core id where the partition VCPU initiating the register write operation is located and the corresponding hardware PostedInterrupt descriptor address, and adds the core id and the corresponding hardware PostedInterrupt descriptor address to the timer configuration message.

3. The method for implementing high-performance timer according to claim 1, wherein after sending the timer configuration message to the high-speed communication queue, further comprising notifying the high-precision timer module that the register write operation is completed; and after receiving the notification, the high-precision timer module acquires the timer configuration message from the high-speed communication queue.

4. The method of claim 1, wherein the high-precision timer module writing the timer configuration packet to a hardware core timer comprises: and the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of the write register, determines the offset and the timing value of the timer, and writes the offset and the timing value into the hardware Core timer.

5. The high performance timer implementation method of claim 4, further comprising, when there are multiple partitions: the high-precision timer module analyzes the timer configuration message, acquires the write register offset and the write value, the core id of a partition VCPU initiating the register write operation and the corresponding hardware-position Interrupt descriptor address, and stores the core id and the hardware-position Interrupt descriptor address of the VCPU in a virtual machine timer model by using the timer offset and the timing value as the core id and the hardware-position Interrupt descriptor address of the VCPU; the found minimum timer value is written to the hardware Core timer.

6. The high performance timer implementing method of claim 5, further comprising: judging whether the hardware Core timer is in a non-timing state or not; if the hardware Core timer is in a non-timing state, the high-precision timer module searches a virtual machine timer data model and writes the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.

7. The high performance timer implementing method of claim 1, further comprising: and the core deploying the partition virtual machine closes the high-precision timer through the Hypervisor.

8. The high performance timer implementing method of claim 1, further comprising: a core is selected, and the embedded Hypervisor high-precision timer module is operated on the core.

9. The high performance timer implementing method of claim 1, further comprising: and constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module on an embedded Hypervisor software layer.

10. The high-performance timer implementing method of any one of claims 1 to 9, further comprising: and when the timing of the hardware Core timer is reached, sending an interrupt notification to the high-precision timer module, writing a high-precision timer interrupt mark into the partition PI descriptor by the high-precision timer module, and sending PI physical interrupt to the partition Core.

11. The high performance timer implementing method of claim 10, when there are a plurality of partitions, further comprising: the high-precision timer module acquires the core id of the VCPU of the timed virtual machine and the address information of the PI descriptor of the virtual machine from the virtual machine timer model, writes a high-precision timer interrupt mark into the corresponding PI descriptor according to the acquired PI descriptor address of the virtual machine, and sends PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.

12. The high performance timer implementing method of claim 11, further comprising: and the high-precision timer module deletes the partition timer data which completes the timed interrupt injection from the virtual machine timer model, reads the next minimum timer value from the virtual machine timer data model, and writes the read next minimum timer value of the virtual machine into the hardware Core timer.

13. A virtual machine, comprising:

the partition GuestOS is used for generating timing requirements and writing timing values into the high-precision timer register 0x 380;

the partition CPU is used for capturing the operation of writing the privileged instruction of the 0x380 register and generating VM _ Exit to Hypervisor processing;

the embedded Hypervisor is used for acquiring the write register offset and the write value through the CPU, adding the write register offset and the write value to the timer configuration message, and sending the write register offset and the write value to the high-speed communication queue;

and the high-precision timer module is used for acquiring the timer configuration message from the high-speed communication queue and writing the timer configuration message into the hardware core timer.

14. The virtual machine according to claim 13, wherein when there are multiple partitions, the embedded Hypervisor is further configured to integrate and add a core id where a partition VCPU initiating a register write operation is located, and a corresponding hardware posternertupt descriptor address to the timer configuration packet.

15. The virtual machine according to claim 13, wherein the embedded Hypervisor is further configured to notify the high-precision timer module that the register writing operation is completed after sending the timer configuration packet to the high-speed communication queue; and the high-precision timer module is also used for acquiring the timer configuration message from the high-speed communication queue after receiving the notification.

16. The virtual machine according to claim 13, wherein the high-precision timer module is configured to parse the timer configuration packet, obtain the write register offset and the write value, determine a timer offset and a timer value, and write the timer offset and the timer value into the hardware Core timer.

17. The virtual machine according to claim 16, wherein when there are multiple partitions, the high precision timer module is further configured to parse the timer configuration packet, obtain the write register offset and the write value, a core id where a partition VCPU initiating a register write operation is located, and a corresponding hardware post Interrupt descriptor address, and store the core id and the hardware post Interrupt descriptor address where the VCPU is located in a virtual machine timer model with the timer offset and the timer value; the found minimum timer value is written to the hardware Core timer.

18. The virtual machine of claim 17, wherein the high-precision timer module is further to determine whether the hardware Core timer is in an untimed state; if the hardware Core timer is in a non-timing state, searching a virtual machine timer data model, and writing the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.

19. The virtual machine of claim 13, wherein the core deploying the partitioned virtual machine is further configured to turn off a high precision timer via Hypervisor.

20. The virtual machine of claim 13 wherein the embedded Hypervisor is further configured to select a core at which to run the embedded Hypervisor high precision timer module.

21. The virtual machine according to claim 13, wherein the embedded Hypervisor is further configured to build a high-speed communication channel between each partitioned virtual machine and the high-precision timer module at a software layer.

22. The virtual machine according to any of the claims 13 to 21, wherein the hardware Core timer is further configured to send an interrupt notification to the high precision timer module when the timing arrives; and the high-precision timer module is also used for writing a high-precision timer interrupt mark into the partition PI descriptor and sending PI physical interrupt to the partition core.

23. The virtual machine according to claim 22, wherein when there are multiple partitions, the high-precision timer module is further configured to obtain, from the virtual machine timer model, the core id and the virtual machine PI descriptor address information of the VCPU of the timed virtual machine, write a high-precision timer interrupt flag into the corresponding PI descriptor according to the obtained virtual machine PI descriptor address, and send a PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.

24. The virtual machine of claim 23, wherein the high precision timer module is further to delete partition timer data from the virtual machine timer model that has completed timed interrupt injection and read a next minimum timer value from the virtual machine timer data model and write the read virtual machine next minimum timer value to the hardware Core timer.

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