CN106324926A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN106324926A CN106324926A CN201610974075.9A CN201610974075A CN106324926A CN 106324926 A CN106324926 A CN 106324926A CN 201610974075 A CN201610974075 A CN 201610974075A CN 106324926 A CN106324926 A CN 106324926A
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- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 27
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 19
- 230000005611 electricity Effects 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000000750 progressive effect Effects 0.000 claims description 5
- 238000013499 data model Methods 0.000 claims description 2
- 208000034699 Vitreous floaters Diseases 0.000 claims 3
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a first pixel unit line, ..., an N<th> pixel unit line and connecting units, the pixel unit lines are scanned line by line, each pixel unit line comprises a plurality of pixel units, each pixel unit comprises a pixel electrode, N is an integer which is not less than 2, pixel electrodes corresponding to all the pixel units in the i+1<th> pixel unit line are electrically connected to form a plurality of pixel electrode groups by the connecting units when the i<th> pixel unit is scanned, each pixel electrode group comprises pixel electrodes with inverse voltage polarity, the number of the pixel electrodes of one pixel electrode group is as same as that of another pixel electrode group, and i is a positive integer which is smaller than N. When the previous pixel unit is scanned, all the pixel electrodes in a next pixel unit line are divided into a plurality of pixel electrode groups, all the pixel electrodes in the pixel electrode groups are electrically connected, the number of the pixel electrodes with inverse voltage polarity of one pixel electrode group is as same as that of another pixel electrode group, so that electric charge of the pixel electrodes in the pixel electrode groups is neutralized, charging time of the pixel electrodes is shortened, and power consumption of the pixel electrodes is reduced.
Description
Technical field
The present invention relates to Display Technique field, more specifically, relate to a kind of array base palte, display floater and display dress
Put.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) has that driving voltage is low, power consumption is little, reliability
High, display contains much information, flicker free, the advantage such as with low cost, is that one preferably shows equipment, has been widely used
In the middle of people's daily life and work.Liquid crystal indicator includes multiple pixel cell, and each pixel cell includes
One pixel electrode, wherein, by being charged each pixel electrode, to drive liquid crystal molecule deflection to reach to make each pixel
Unit corresponding region goes out the purpose of light, and then makes liquid crystal indicator carry out the display of picture.Pixel electrode is being charged
During, owing to needing charging polarity is inverted when every frame picture, thus, when showing next frame picture, in pixel
When electrode needs neutralize previous frame picture after residual charge, this pixel electrode effectively could be charged, this is made
The power consumption of display device is relatively big, and the charging interval to pixel electrode is extended, and reduces the picture refreshing rate of display device.
Summary of the invention
In view of this, the invention provides a kind of array base palte, display floater and display device, to previous pixel cell
When row is scanned, all pixel electrodes in a rear pixel cell row are divided into multiple pixel electrode group, each pixel electrode group
In electrically connect between all pixel electrodes, and in each pixel electrode group, the quantity of the pixel electrode that polarity of voltage is contrary is identical,
So that pixel electrode group realizes charging neutrality between multiple pixel electrodes, with electric to pixel during reduction this pixel cell row of scanning
The charging interval of pole and power consumption, it is ensured that the picture refreshing rate of display device is high.
For achieving the above object, the technical scheme that the present invention provides is as follows:
A kind of array base palte, including:
First pixel cell of progressive scan walks to N pixel cell row, and each described pixel cell row all includes multiple
Pixel cell, described pixel cell includes a pixel electrode, and N is the integer not less than 2,
And, connecting unit, described connection unit is for when scanning ith pixel cell row, by i+1 pixel cell row
In electrically connect as multiple pixel electrode group, and each described pixel electrode group bag between pixel electrode corresponding to all pixel cells
The quantity of the pixel electrode that the polarity of voltage that includes is contrary is identical, and i is the positive integer less than N.
Optionally, described array base palte includes:
First order gate line is to N level gate line and drive element of the grid, and described first order gate line is to N level gate line
Walk to N pixel cell row with described first pixel cell successively corresponding, described drive element of the grid include an input port and
First order output port is to N level output port, and wherein, i-stage gate line is connected with i-stage output port, and described grid drives
Moving cell is after accessing scanning signal at described input port, and described first order output port to N level output port is step by step
Export described scanning signal, to scan described first order gate line step by step to N level gate line；
Wherein, described connection unit include the first sub-link block to N-1 link block, and described first son connect
Module walks to the corresponding electrical connection of N pixel cell row successively to N-1 link block with described second pixel cell, and described the
One sub-link block to N-1 link block for successively according to described first order output port to N-1 level output port
The control of the described scanning signal of output, when scanning described ith pixel cell row, by institute in described i+1 pixel cell row
Have between the pixel electrode that pixel cell is corresponding and electrically connect as multiple described pixel electrode group.
Optionally, the first sub-link block all includes to N-1 link block:
Multiple the first transistors, and the corresponding output port of the grid of described the first transistor and described drive element of the grid
Connection, and, by the first electricity of the first transistor described between any two pixel electrodes of same described pixel electrode group
Pole is connected with the second electrode.
Optionally, described second pixel cell walks to each described pixel cell in N pixel cell row and includes one second
Transistor, and the grid connection corresponding stage gate line of described transistor seconds, the first electrode of described transistor seconds accesses number
The number of it is believed that, and the second electrode described pixel electrode of connection of described transistor seconds；
Wherein, the first electrode of described the first transistor and the second electrode connect the pixel electricity of adjacent two pixel cells respectively
Pole, semiconductor layer corresponding to the second electrode side of the transistor seconds of described adjacent two pixel cells respectively with described first crystal
The semiconductor layer two ends of pipe connect, and the second electrode of the transistor seconds of described adjacent two pixel cells is multiplexed with described respectively
First electrode of the first transistor and the second electrode.
Optionally, each described pixel electrode group includes two pixel electrodes, and said two pixel electrode is adjacent
Two pixel electrodes.
Optionally, the grid of the first transistor of the sub-link block of jth is connected to j-th stage gate line by connecting lead wire,
Electrically connect with the jth output port with described drive element of the grid；Wherein, described connecting lead wire be positioned at adjacent two pixel cells it
Between, j is the positive integer less than N.
Optionally, described array base palte includes a plurality of with what described first order gate line to the N different layer of level gate line was arranged
Data wire；
Wherein, described connecting lead wire and described first order gate line to N level gate line are positioned at same conductive layer, described company
Connect lead-in wire identical with the bearing of trend of described data wire, and between described connecting lead wire and described data wire, there is overlapping region.
Optionally, described array base palte includes:
Substrate；
Being positioned at the gate metal layer of substrate side, described gate metal layer includes described the first transistor and transistor seconds
Grid, and, including described first order gate line to N level gate line；
It is positioned at described grid layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the semiconductor structure of described substrate side, described semiconductor structure includes described
One transistor and the semiconductor layer of transistor seconds；
And, it being positioned at described semiconductor layer and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes
Described the first transistor and the first electrode of transistor seconds and the second electrode；
Or, described array base palte includes:
Substrate；
Being positioned at the semiconductor structure of substrate side, described semiconductor structure includes and described the first transistor and the second crystal
The semiconductor layer of pipe；
It is positioned at described semiconductor layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the gate metal layer of described substrate side, described gate metal layer includes described
One transistor and the grid of transistor seconds, and, including described first order gate line to N level gate line；
It is positioned at described gate metal layer and deviates from the insulating barrier of described substrate side；
And, it being positioned at described insulating barrier and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes institute
State the first transistor and the first electrode of transistor seconds and the second electrode.
Optionally, described connecting lead wire and described semiconductor layer do not have overlapping region.
Optionally, described array base palte also includes:
Virtual subnet link block, the electrical connection corresponding with described first pixel cell row of described virtual subnet link block, and,
The control of the described virtual subnet link block described scanning signal for accessing according to described input port, by described first pixel
Multiple described pixel electrode group is electrically connected as between the pixel electrode that in cell row, all pixel cells are corresponding.
Optionally, described array base palte also includes:
Virtual subnet link block, the electrical connection corresponding with described first pixel cell row of described virtual subnet link block；
And, described drive element of the grid also includes a vitual stage output port, and described vitual stage output port is described
After input port accesses described scanning signal, export described scanning signal prior to described first order output port；
Wherein, described virtual subnet link block is for the described scanning signal according to the output of described vitual stage output port
Control, between pixel electrode corresponding for all pixel cells in described first pixel cell row, electrically connect as multiple described pixel
Electrode group.
Accordingly, present invention also offers a kind of display floater, described display floater includes above-mentioned array base palte.
Finally, present invention also offers a kind of display device, described display device includes above-mentioned display floater.
Compared to prior art, the technical scheme that the present invention provides at least has the advantage that
The invention provides a kind of array base palte, display floater and display device, including: the first pixel list of progressive scan
Unit walks to N pixel cell row, and each described pixel cell row all includes that multiple pixel cell, described pixel cell include a picture
Element electrode, N is the integer not less than 2, and, connecting unit, described connection unit is used for when scanning ith pixel cell row,
Multiple pixel electrode group will be electrically connected as between pixel electrode corresponding for all pixel cells in i+1 pixel cell row, and often
The quantity of the pixel electrode that polarity of voltage that pixel electrode group described in includes is contrary is identical, and i is the positive integer less than N.By upper
Stating content to understand, the technical scheme that the present invention provides, when being scanned previous pixel cell row, by a rear pixel cell row
In all pixel electrodes be divided into multiple pixel electrode group, each pixel electrode group electrically connects between all pixel electrodes, and often
In individual pixel electrode group, the quantity of the pixel electrode that polarity of voltage is contrary is identical so that in pixel electrode group multiple pixel electrodes it
Between realize charging neutrality, with reduce scan this pixel cell row time to charging interval of pixel electrode and power consumption, it is ensured that display dress
The picture refreshing rate put is high.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to according to
The accompanying drawing provided obtains other accompanying drawing.
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present application；
The structural representation of the another kind of array base palte that Fig. 2 provides for the embodiment of the present application；
The structural representation of another array base palte that Fig. 3 provides for the embodiment of the present application；
A kind of the first transistor that Fig. 4 provides for the embodiment of the present application and the structural representation of transistor seconds；
The structural representation of another array base palte that Fig. 5 provides for the embodiment of the present application；
The structural representation of another array base palte that Fig. 6 provides for the embodiment of the present application.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
As described in background, liquid crystal indicator includes multiple pixel cell, and each pixel cell includes
One pixel electrode, wherein, by being charged each pixel electrode, to drive liquid crystal molecule deflection to reach to make each pixel
Unit corresponding region goes out the purpose of light, and then makes liquid crystal indicator carry out the display of picture.Pixel electrode is being charged
During, owing to needing charging polarity is inverted when every frame picture, thus, when showing next frame picture, in pixel
When electrode needs neutralize previous frame picture after residual charge, this pixel electrode effectively could be charged, this is made
The power consumption of display device is relatively big, and the charging interval to pixel electrode is extended, and reduces the picture refreshing rate of display device.
Based on this, the embodiment of the present application provides a kind of array base palte, display floater and display device, to previous pixel
When cell row is scanned, all pixel electrodes in a rear pixel cell row are divided into multiple pixel electrode group, each pixel electricity
Pole group electrically connects between all pixel electrodes, and the quantity phase of the pixel electrode that polarity of voltage is contrary in each pixel electrode group
With so that pixel electrode group realizes charging neutrality between multiple pixel electrodes, with reduce scan this pixel cell row time to picture
The charging interval of element electrode and power consumption, it is ensured that the picture refreshing rate of display device is high.For achieving the above object, the embodiment of the present application
The technical scheme provided is as follows, specifically combines shown in Fig. 1 to Fig. 6, and the technical scheme providing the embodiment of the present application is carried out in detail
Explanation.
With reference to shown in Fig. 1, for the structural representation of a kind of array base palte that the embodiment of the present application provides, wherein, array base
Plate includes:
First pixel cell row P1 to N pixel cell row Pn of progressive scan, each described pixel cell row all includes
Multiple pixel cells, described pixel cell includes that a pixel electrode PI, N are the integer not less than 2,
And, connecting unit 100, described connection unit 100 is for when scanning ith pixel cell row, by i+1 pixel
Multiple pixel electrode group, and each described pixel is electrically connected as between the pixel electrode PI that in cell row, all pixel cells are corresponding
The quantity of the pixel electrode PI that polarity of voltage that electrode group includes is contrary is identical, and i is the positive integer less than N.
The array base palte that the embodiment of the present application provides, it includes a plurality of gate lines G along column direction arrangement, and includes
Having a plurality of data wire 10 arranged in the row direction, wherein, a plurality of gate lines G and a plurality of data lines 10 intersection limit this first pixel
The pixel unit array that cell row P1 is formed to N pixel cell row Pn.Wherein, a plurality of gate lines G is along multiple pixel cell row
Orientation be divided into first order gate line to N level gate line, and corresponding first pixel cell row P1 to N pixel cell row
Pn, with by the scanning step by step of every grade of gate line, and realizes progressively scanning the first pixel cell row P1 to N pixel cell row
Pn。
Wherein, each pixel cell that the embodiment of the present application provides, all include a pixel electrode PI, and pixel electrode PI leads to
Cross a transistor seconds M2 and be connected to corresponding stage gate lines G and data wire 10, i.e. the grid of transistor seconds M2 is connected to accordingly
Level gate lines G, first end of transistor seconds M2 is connected to pixel electrode PI, and second end of transistor seconds M2 is connected to number
According to line 10.Wherein, opened the transistor seconds M2 being connected by gate lines G, and provided for pixel electrode PI by data wire 10
Respective electrode data signal.
The technical scheme that the embodiment of the present application provides, when being scanned previous pixel cell row, by a rear pixel list
In unit's row, all pixel electrodes are divided into multiple pixel electrode group, electrically connect in each pixel electrode group between all pixel electrodes,
And the quantity of the pixel electrode that polarity of voltage is contrary is identical in each pixel electrode group, so that multiple pixels electricity in pixel electrode group
Realize charging neutrality between pole, with reduce scan this pixel cell row time to charging interval of pixel electrode and power consumption, it is ensured that aobvious
The picture refreshing rate of showing device is high.
Further, with reference to shown in Fig. 2, for the structural representation of the another kind of array base palte that the embodiment of the present application provides,
Wherein, described array base palte includes:
First order gate lines G 1 is to N level gate lines G n and drive element of the grid 200, described first order gate lines G 1 to
N level gate lines G n is corresponding with described first pixel cell row P1 to N pixel cell row Pn successively, described drive element of the grid
200 include an input port In and first order output port OUT1 to N level output port OUTn, wherein, i-stage gate lines G i
Being connected with i-stage output port OUTi, described drive element of the grid 200 is for accessing scanning signal at described input port In
After, described first order output port OUT1 to N level output port OUTn exports described scanning signal, step by step to scan institute step by step
State first order gate lines G 1 to N level gate lines G n；
Wherein, described connection unit includes that the first sub-link block 101 is to N-1 link block 10 (n-1) and described
First sub-link block 101 to N-1 link block 10 (n-1) successively with described second pixel cell row P2 to N pixel
Cell row Pn correspondence electrically connects, and described first sub-link block 101 to N-1 link block 10 (n-1) is for basis successively
The control of the described scanning signal that described first order output port OUT1 to N-1 level output port OUT (n-1) exports, is sweeping
When retouching described ith pixel cell row PI, by pixel electricity corresponding for all pixel cells in described i+1 pixel cell row P (i+1)
Multiple described pixel electrode group is electrically connected as between the PI of pole.
Wherein, in scanning process, drive element of the grid 200 progressively scans first order gate lines G 1 to N level gate line
Gn, to progressively scan the first pixel cell row P1 to N pixel cell row Pn；(i.e. sweep during scanning the i-th gate lines G i
During retouching ith pixel cell row PI), the i-th output port OUTi can export scanning signal, then the i-th sub-link block 10i
Can be according to the scanning signal of the i-th output port OUTi output, all pixel electrodes corresponding by i+1 pixel cell row P (i+1)
PI is divided into multiple pixel electrode group, and will electrically connect between pixel electrode PI all in each pixel electrode group, and each pixel
The pixel electrode PI of the forward voltage polarity in electrode group is identical with the quantity of the pixel electrode PI of negative voltage polarity, so that often
Realize charging neutrality between all pixel electrode PI in individual pixel electrode group, and then reduce when scanning this pixel cell row picture
The charging interval of element electrode PI and power consumption, it is ensured that the picture refreshing rate of display device is high.
The concrete structure of the application sub-link block for providing does not limits, and needs to carry out according to reality application to this
Specific design, wherein, simple for production in order to ensure sub-link block, the embodiment of the present application provides a concrete sub-link block
Structure.With reference to shown in Fig. 3, for the structural representation of another array base palte that the embodiment of the present application provides, wherein, the application
The first sub-link block 101 that embodiment provides all includes to N-1 link block 10 (n-1) block:
Multiple the first transistor M1, and the grid of described the first transistor M1 is corresponding to described drive element of the grid 300
Output port connects, and, by first crystal described between any two pixel electrode PI of same described pixel electrode group
First electrode of pipe M1 and the second electrode are connected.
In order to easy to make, the array base palte that the embodiment of the present application provides, can be by transistor seconds and pixel electrode phase
The second electrode even is multiplexed with the first electrode or second electrode of the first transistor.Specifically combining shown in Fig. 3 and Fig. 4, Fig. 4 is this
A kind of the first transistor of application embodiment offer and the structural representation of transistor seconds, wherein, described second pixel cell
P2 walks to each described pixel cell in N pixel cell row Pn and includes a transistor seconds M2, and described transistor seconds M2
Grid connect corresponding stage gate line, the first electrode incoming data signal (that is, transistor seconds M2 of described transistor seconds M2
The first electrode be connected with data wire 10), and described transistor seconds M2 second electrode connect described pixel electrode PI；
Wherein, first electrode of described the first transistor M1 and the second electrode connect the pixel of adjacent two pixel cells respectively
Semiconductor layer Poly1 corresponding to the second electrode side of electrode PI, the transistor seconds M2 of described adjacent two pixel cells respectively with
The semiconductor layer Poly2 two ends connection of described the first transistor M1, and the transistor seconds M2 of described adjacent two pixel cells
Second electrode is multiplexed with the first electrode and second electrode of described the first transistor M1 respectively.
In other optional embodiments of the application, it is also possible to the pixel electrode PI of adjacent two pixel cells is passed through respectively
Via connects with the semiconductor layer Poly2 two ends of the first transistor M1, so that the second crystal of described adjacent two pixel cells
The pixel electrode PI of pipe M2 is multiplexed with the first electrode and second electrode of described the first transistor M1 respectively, and this is not done by the application
Limit.
Optionally, each described pixel electrode group that the embodiment of the present application provides includes two pixel electrode PI, and described
Two pixel electrode PI are adjacent two pixel electrode PI.With reference to shown in Fig. 4, it is preferred that the jth that the embodiment of the present application provides
The grid of the first transistor M1 of sub-link block is connected to j-th stage gate line by connecting lead wire 20, with raster data model list
The jth output port electrical connection of unit 200；Wherein, described connecting lead wire 20 is preferably placed between adjacent two pixel cells, and j is little
Positive integer in N.That is, two the pixel electrode PI included due to pixel electrode group are adjacent, so, the first of the first transistor M1
Two transistor seconds M2 of electrode and the second electrode multiplexing are adjacent two transistor seconds M2, due to adjacent two second
Transistor M2 is close together, can be easy to this by semiconductor layer Ploy2 by the second of adjacent two transistor seconds M2
The semiconductor layer Poly1 of electrode side is connected, it is simple to technique makes.
Preferably, make to not increase film layer, with reference to shown in Fig. 4, the described array base palte that the embodiment of the present application provides
Including a plurality of data lines 10 arranged with described first order gate lines G 1 to the N different layer of level gate lines G n；
Wherein, described connecting lead wire 20 is positioned at same conductive layer with described first order gate lines G 1 to N level gate lines G n,
Described connecting lead wire 20 is identical with the bearing of trend of described data wire 10, and between described connecting lead wire 20 and described data wire 10
There is overlapping region.
In any one embodiment of the application, the first transistor in the array base palte that the application provides and transistor seconds
Can be top gate-type transistors, it is also possible to for bottom-gate-type transistor, this application is not particularly limited.That is, the application implements
The array base palte that example provides may include that
Substrate；
Being positioned at the gate metal layer of substrate side, described gate metal layer includes described the first transistor and transistor seconds
Grid, and, including described first order gate line to N level gate line；
It is positioned at described grid layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the semiconductor structure of described substrate side, described semiconductor structure includes described
One transistor and the semiconductor layer of transistor seconds；
And, it being positioned at described semiconductor layer and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes
Described the first transistor and the first electrode of transistor seconds and the second electrode；
Or, the described array base palte that the embodiment of the present application provides may include that
Substrate；
Being positioned at the semiconductor structure of substrate side, described semiconductor structure includes and described the first transistor and the second crystal
The semiconductor layer of pipe；
It is positioned at described semiconductor layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the gate metal layer of described substrate side, described gate metal layer includes described
One transistor and the grid of transistor seconds, and, including described first order gate line to N level gate line；
It is positioned at described gate metal layer and deviates from the insulating barrier of described substrate side；
And, it being positioned at described insulating barrier and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes institute
State the first transistor and the first electrode of transistor seconds and the second electrode.
It should be noted that the described connecting lead wire 20 that the embodiment of the present application provides does not has overlapping with described semiconductor layer
Region.That is, affecting the state of other transistors in order to avoid the voltage signal of connecting lead wire 20, connecting lead wire 20 is except coupled
The first transistor M1 grid be connected outside, connecting lead wire 20 does not has overlapping region with any semiconductor layer.
Further, in order to ensure all pixel electrodes of the first pixel cell row the most before scanning by charging neutrality,
And then reducing power consumption further, the embodiment of the present application can also include virtual subnet link block, with at scanning the first pixel cell
During row, by the charging neutrality on all pixel electrodes of the first pixel cell row.Specifically combine shown in Fig. 5, implement for the application
The structural representation of another array base palte that example provides, wherein, the described array base palte that the embodiment of the present application provides also includes:
Virtual subnet link block 301, described virtual subnet link block 301 is corresponding with described first pixel cell row P1 to be electrically connected
Connect, and, the control of the described virtual subnet link block 301 described scanning signal for accessing according to described input port In,
Multiple described pixel is electrically connected as between pixel electrode PI corresponding for all pixel cells in described first pixel cell row P1
Electrode group.
That is, the array base palte that the embodiment of the present application provides, its virtual subnet link block can be connected to drive element of the grid
The input port In of 200, the control of the scanning signal to input according to this input port In, the institute to the first pixel cell row P1
There is pixel electrode PI to be divided into multiple pixel electrode group, and all pixel electrode PI in each pixel electrode group are connected, and
Normal polarity pixel electrode in each pixel electrode group is identical with the quantity of negative sense polarity pixel electrode, to reach to neutralize pixel
The purpose of electric charge in electrode.
Additionally, the virtual subnet link block that the embodiment of the present application provides is in addition to can controlling by input port In, also may be used
To arrange a vitual stage output port in drive element of the grid 200, and vitual stage output port accesses scanning at input port
After signal, export this scanning signal prior to first order output port.That is, with reference to shown in Fig. 6, provide again for the embodiment of the present application
A kind of structural representation of array base palte, wherein, the described array base palte that the embodiment of the present application provides also includes:
Virtual subnet link block 301, described virtual subnet link block 301 is corresponding with described first pixel cell row P1 to be electrically connected
Connect；
And, described drive element of the grid 200 also includes a vitual stage output port OUT ', described vitual stage output port
OUT ', after described input port In accesses described scanning signal, exports described scanning prior to described first order output port OUT1
Signal；
Wherein, described virtual subnet link block 301 is swept described in exporting according to described vitual stage output port OUT '
Retouch the control of signal, electrically connect as between pixel electrode PI corresponding for all pixel cells in described first pixel cell row P1
Multiple described pixel electrode groups.
That is, the array base palte that the embodiment of the present application provides, its virtual subnet link block can be connected to drive element of the grid
The vitual stage output port OUT ' of 200, the control of the scanning signal to export according to this vitual stage input port OUT ', to first
All pixel electrode PI of pixel cell row P1 are divided into multiple pixel electrode group, and by all pixels in each pixel electrode group
Electrode PI is connected, and the normal polarity pixel electrode in each pixel electrode group and the quantity phase of negative sense polarity pixel electrode
With, to reach to neutralize the purpose of electric charge in pixel electrode.
In the virtual subnet link block that the above embodiments of the present application provide, this virtual subnet link block is equally by many
Individual the first transistor forms, and the first electrode of the first transistor and the second electrode can preferred corresponding two the second crystal of multiplexing
Second electrode of pipe, is not particularly limited this application, needs to carry out specific design according to reality application.
Accordingly, the embodiment of the present application additionally provides a kind of display floater, and described display floater includes above-mentioned any one reality
Execute the array base palte that example provides, and display floater also includes the color membrane substrates that is oppositely arranged with array base palte, and, it is positioned at array
Liquid crystal layer between substrate and color membrane substrates, same as the prior art to this, the application does not do unnecessary repeating.
Finally, the embodiment of the present application additionally provides a kind of display device, and described display device includes above-mentioned any one enforcement
The display floater that example provides, and, the backlight source module of backlight is provided for display floater, same, to this and prior art
Identical, the application does not do unnecessary repeating.
The embodiment of the present application provides a kind of array base palte, display floater and display device, including: the first of progressive scan
Pixel cell walks to N pixel cell row, and each described pixel cell row all includes multiple pixel cell, described pixel cell bag
Including a pixel electrode, N is the integer not less than 2, and, connecting unit, described connection unit is at scanning ith pixel unit
During row, electrically connect as multiple pixel electrode group by between pixel electrode corresponding for all pixel cells in i+1 pixel cell row,
And the quantity of the contrary pixel electrode of the polarity of voltage that includes of each described pixel electrode group is identical, i is the positive integer less than N.
As shown in the above, the technical scheme that the embodiment of the present application provides, when being scanned previous pixel cell row, by rear one
In pixel cell row, all pixel electrodes are divided into multiple pixel electrode group, electricity between all pixel electrodes in each pixel electrode group
Connect, and in each pixel electrode group, the quantity of the pixel electrode that polarity of voltage is contrary is identical, so that multiple in pixel electrode group
Realize charging neutrality between pixel electrode, with reduce scan this pixel cell row time to charging interval of pixel electrode and power consumption,
Ensure that the picture refreshing rate of display device is high.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.
Multiple amendment to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can realize without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein and features of novelty phase one
The widest scope caused.
Claims (13)
1. an array base palte, it is characterised in that including:
First pixel cell of progressive scan walks to N pixel cell row, and each described pixel cell row all includes multiple pixel
Unit, described pixel cell includes a pixel electrode, and N is the integer not less than 2,
And, connecting unit, described connection unit is for when scanning ith pixel cell row, by institute in i+1 pixel cell row
Have between the pixel electrode that pixel cell is corresponding and electrically connect as multiple pixel electrode group, and each described pixel electrode group includes
The quantity of the pixel electrode that polarity of voltage is contrary is identical, and i is the positive integer less than N.
Array base palte the most according to claim 1, it is characterised in that described array base palte includes:
First order gate line is to N level gate line and drive element of the grid, and described first order gate line to N level gate line is successively
Walking to N pixel cell row with described first pixel cell corresponding, described drive element of the grid includes an input port and first
Level output port is to N level output port, and wherein, i-stage gate line is connected with i-stage output port, described raster data model list
Unit is after accessing scanning signal at described input port, and described first order output port exports step by step to N level output port
Described scanning signal, to scan described first order gate line step by step to N level gate line；
Wherein, described connection unit include the first sub-link block to N-1 link block, and described first sub-link block
Walk to the corresponding electrical connection of N pixel cell row, described first son successively with described second pixel cell to N-1 link block
Link block to N-1 link block is used for exporting according to described first order output port to N-1 level output port successively
The control of described scanning signal, when scanning described ith pixel cell row, by all pictures in described i+1 pixel cell row
Multiple described pixel electrode group is electrically connected as between the pixel electrode that element unit is corresponding.
Array base palte the most according to claim 2, it is characterised in that the first sub-link block is to N-1 link block
All include:
Multiple the first transistors, and the corresponding output port of the grid of described the first transistor and described drive element of the grid is even
Logical, and, by the first electrode of the first transistor described between any two pixel electrodes of same described pixel electrode group
It is connected with the second electrode.
Array base palte the most according to claim 3, it is characterised in that described second pixel cell walks to N pixel cell
In row, each described pixel cell includes a transistor seconds, and the grid of described transistor seconds connects corresponding stage gate line,
First electrode incoming data signal of described transistor seconds, and the second electrode connection described pixel electricity of described transistor seconds
Pole；
Wherein, the first electrode of described the first transistor and the second electrode connect the pixel electrode of adjacent two pixel cells respectively,
Semiconductor layer corresponding to the second electrode side of the transistor seconds of described adjacent two pixel cells respectively with described the first transistor
The connection of semiconductor layer two ends, and the second electrode of the transistor seconds of described adjacent two pixel cells is multiplexed with described the respectively
First electrode of one transistor and the second electrode.
Array base palte the most according to claim 4, it is characterised in that each described pixel electrode group includes two pixel electricity
Pole, and said two pixel electrode is two adjacent pixel electrodes.
Array base palte the most according to claim 5, it is characterised in that
The grid of the first transistor of the sub-link block of jth is connected to j-th stage gate line by connecting lead wire, with described grid
The jth output port electrical connection of driver element；Wherein, described connecting lead wire is between adjacent two pixel cells, and j is less than N
Positive integer.
Array base palte the most according to claim 6, it is characterised in that described array base palte includes and described first order grid
The a plurality of data lines that line is arranged to the N different layer of level gate line；
Wherein, described connecting lead wire and described first order gate line to N level gate line are positioned at same conductive layer, and described connection is drawn
Line is identical with the bearing of trend of described data wire, and has overlapping region between described connecting lead wire and described data wire.
Array base palte the most according to claim 6, it is characterised in that described array base palte includes:
Substrate；
Being positioned at the gate metal layer of substrate side, described gate metal layer includes the grid of described the first transistor and transistor seconds
Pole, and, including described first order gate line to N level gate line；
It is positioned at described grid layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the semiconductor structure of described substrate side, described semiconductor structure includes that described first is brilliant
Body pipe and the semiconductor layer of transistor seconds；
And, it being positioned at described semiconductor layer and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes described
The first transistor and the first electrode of transistor seconds and the second electrode；
Or, described array base palte includes:
Substrate；
Being positioned at the semiconductor structure of substrate side, described semiconductor structure includes and described the first transistor and transistor seconds
Semiconductor layer；
It is positioned at described semiconductor layer and deviates from the gate dielectric layer of described substrate side；
Being positioned at described gate dielectric layer and deviate from the gate metal layer of described substrate side, described gate metal layer includes that described first is brilliant
Body pipe and the grid of transistor seconds, and, including described first order gate line to N level gate line；
It is positioned at described gate metal layer and deviates from the insulating barrier of described substrate side；
And, it being positioned at described insulating barrier and deviate from the source and drain metal level of described substrate side, described source and drain metal level includes described
One transistor and the first electrode of transistor seconds and the second electrode.
Array base palte the most according to claim 8, it is characterised in that described connecting lead wire does not has with described semiconductor layer
Overlapping region.
Array base palte the most according to claim 2, it is characterised in that described array base palte also includes:
Virtual subnet link block, the electrical connection corresponding with described first pixel cell row of described virtual subnet link block, and, described
The control of the virtual subnet link block described scanning signal for accessing according to described input port, by described first pixel cell
Multiple described pixel electrode group is electrically connected as between the pixel electrode that in row, all pixel cells are corresponding.
11. array base paltes according to claim 2, it is characterised in that described array base palte also includes:
Virtual subnet link block, the electrical connection corresponding with described first pixel cell row of described virtual subnet link block；
And, described drive element of the grid also includes a vitual stage output port, and described vitual stage output port is in described input
After port accesses described scanning signal, export described scanning signal prior to described first order output port；
Wherein, described virtual subnet link block is for the control of the described scanning signal according to the output of described vitual stage output port
System, will electrically connect as multiple described pixel electricity between pixel electrode corresponding for all pixel cells in described first pixel cell row
Pole group.
12. 1 kinds of display floaters, it is characterised in that described display floater includes the battle array described in claim 1～11 any one
Row substrate.
13. 1 kinds of display devices, it is characterised in that described display device includes the display floater described in claim 12.
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