CN106298814A - A kind of array base palte and display floater - Google Patents

Abstract

Embodiments of the present invention provide an array substrate and a display panel, which relate to the field of display technology and can simplify the process flow of the display panel. The array substrate includes: a substrate, a gate metal layer, a gate insulating layer, a semiconductor active layer, a source-drain metal layer, a barrier layer, and a light-shielding structure sequentially arranged on the substrate; the gate metal layer includes a bottom gate electrode and gate line; the source-drain metal layer includes a source electrode, a drain electrode and a data line; the light-shielding structure includes a conductive electrode, and the conductive electrode is electrically connected to the bottom gate electrode; wherein, the opaque The light blocking structure also functions as a black matrix.

Description

A kind of array substrate and display panel

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a display panel.

Background technique

Liquid Crystal Display (LCD for short) has the advantages of low radiation, small size and low energy consumption, and is widely used in electronic products such as tablet computers, TVs or mobile phones. At the same time, people are concerned about the display quality of display panels. requirements are also getting higher.

Generally, in LCD, the display quality of the display panel can be improved by reducing the shift of the threshold voltage of the thin film transistor (Thin Film Transistor, referred to as TFT). Compared with the common single-gate TFT, the double-gate TFT has better performance , Such as: better stability and uniformity of threshold voltage, higher electron mobility, larger on-state current, smaller sub-threshold swing, better grid bias and light stability, etc.

However, a display panel using double-gate TFTs will complicate the process flow.

Contents of the invention

Embodiments of the present invention provide an array substrate and a display panel, which can simplify the process flow of the display panel.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, an array substrate is provided, including: a substrate, a gate metal layer, a gate insulating layer, a semiconductor active layer, a source-drain metal layer, a barrier layer, and a light-shielding structure sequentially disposed on the substrate; The gate metal layer includes a bottom gate electrode and a gate line; the source-drain metal layer includes a source electrode, a drain electrode, and a data line; the light-shielding structure includes a conductive electrode, and the conductive electrode is electrically connected to the bottom gate electrode ; Wherein, the opaque light-shielding structure is also used as a black matrix.

Preferably, the width of the data line is 5-10 μm; the light blocking structure is arranged along the direction of the gate line.

Further preferably, the gate metal layer further includes a common electrode line, and the common electrode line is disposed close to the gate line; the bottom gate electrode is disposed on a side of the gate line close to the common electrode line; The light blocking structure is arranged between the gate lines and the common electrode lines.

Optionally, the material of the conductive electrode is an opaque conductive material.

Further preferably, the material of the conductive electrode includes a black conductive polymer.

Optionally, the material of the conductive electrode is a transparent conductive material; the light blocking structure further includes a black resin layer arranged on the side of the conductive electrode away from the substrate; the pattern of the black resin layer is consistent with the The pattern of the conductive electrodes is the same.

Preferably, the array substrate further includes a color filter layer.

Preferably, the semiconductor active layer is an oxide semiconductor active layer.

Further, the array substrate further includes an etching stopper layer disposed on a surface of the oxide semiconductor active layer away from the substrate.

In a second aspect, a display panel is provided, including the above-mentioned array substrate.

An embodiment of the present invention provides an array substrate and a display panel. By providing a light-shielding structure on the array substrate, on the one hand, the light-shielding structure can be used as a black matrix, and the preparation process of the black matrix in the display panel can be omitted. Therefore, when When the array substrate is applied to the display panel, the process can be simplified; on the other hand, the light-shielding structure includes a conductive electrode, and the conductive electrode is electrically connected to the bottom gate electrode, so that a double-gate thin film transistor structure can be formed on the array substrate, thereby enabling Improve the display quality of the display panel.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic top view of an array substrate provided by an embodiment of the present invention;

Fig. 2 (a) is A-A' among Fig. 1 to sectional schematic diagram one;

Fig. 2 (b) is B-B ' among Fig. 1 to sectional schematic diagram one;

FIG. 3 is a schematic top view II of an array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic top view III of an array substrate provided by an embodiment of the present invention;

Fig. 5 (a) is A-A' in Fig. 1 to cross-sectional schematic diagram two;

Fig. 5 (b) is B-B' among Fig. 1 to sectional schematic diagram two;

Fig. 6 is a schematic sectional view of C-C' in Fig. 4;

Fig. 7 is a schematic sectional view of C-C' in Fig. 4;

FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

FIG. 9 is a schematic flow chart of preparing an array substrate provided by an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present invention.

Reference signs:

10-substrate; 11-gate metal layer; 111-bottom gate electrode; 112-gate line; 113-common electrode line; 12-gate insulating layer; 13-semiconductor active layer; 14-source drain metal layer; 141- Source electrode; 142-drain electrode; 143-data line; 16-blocking layer; 17-etching barrier layer; 20-light blocking structure; 201-conductive electrode; 202-black resin layer; filter layer; 50-planar layer; 60-common electrode.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides an array substrate, as shown in FIG. 1, FIG. 2(a) and FIG. 2(b), comprising: a substrate 10, a gate metal layer 11 sequentially disposed on the substrate 10, and a gate insulating layer 12. Semiconductor active layer 13, source-drain metal layer 14, barrier layer 16, and light-shielding structure 20; gate metal layer 11 includes bottom gate electrode 111, gate line 112; source-drain metal layer 14 includes source electrode 141, drain electrode 142 and data lines 143; the light blocking structure 20 includes a conductive electrode 201, and the conductive electrode 201 is electrically connected to the bottom gate electrode 111; wherein, the opaque light blocking structure 20 also functions as a black matrix.

Of course, the array substrate further includes a pixel electrode 30 electrically connected to the drain electrode 142 .

It should be noted that, firstly, those skilled in the art should know that the function of the black matrix, on the one hand, needs to shield at least the part of the semiconductor active layer 13 corresponding to the gap between the source electrode 141 and the drain electrode 142 (ie, the channel). area) to prevent characteristic drift caused by external light exposure; of course, in order to avoid light reflection from metals such as the source electrode 141 , the drain electrode 142 , and the bottom gate electrode 111 , the entire TFT can also be blocked. On the other hand, it is necessary to prevent pixel light leakage, that is, it is necessary to block the area that is not controlled by the electric field or the area where light leakage may occur due to the complexity of the electric field, such as the area between the gate line 112 and the pixel electrode 30, or the area between the gate line 112 and the common electrode. the area between the lines.

In addition, the black matrix also has the function of preventing cross-color, that is, it is arranged between adjacent and different color sub-pixels. For example, when the sub-pixels on both sides of the data line 143 are sub-pixels of different colors, it can be A black matrix covering the data lines 143 is provided to prevent cross-color. Of course, it is not necessary to use a black matrix to prevent cross-color, and other methods can also be used to prevent cross-color.

Based on this, since the light blocking structure 20 of the embodiment of the present invention also functions as a black matrix, that is, the light blocking structure 20 can replace the black matrix, therefore, the shape of the light blocking structure 20 can refer to the shape of the black matrix. However, it should be noted that since the conductive electrodes 201 in the light-blocking structure 20 are conductive, when designing the shape of the light-blocking structure 20, it is necessary to avoid passing through the light-blocking structure 20 and adjacent sub-pixels along the direction of the data line 143 Bottom gate electrodes 111 in the are electrically connected.

Wherein, since the conductive electrode 201 in the light-shielding structure 20 is electrically connected to the bottom gate electrode 111, and through the description of the function of the black matrix above, it can be known that the light-shielding structure 20 is bound to block the source electrode 141 and the drain electrode of the semiconductor active layer 13 The part corresponding to the gap between 142, therefore, the conductive electrode 201 can be used as the top gate electrode of the TFT, that is, the TFT is a double-gate TFT.

Second, the layer structure of the light blocking structure 20 is not limited, it may only include the conductive electrode 201 as shown in FIG. 2(a) and FIG. Of course, in addition to the conductive electrode 201, other layers may also be included, as long as the light-shielding structure 20 as a whole can play a role of light-shielding, the conductive electrode 201 can be electrically connected to the bottom gate electrode 111 and will not cause complicated processes (it can be passed through once). A patterning process may be used to form the light blocking structure 20).

Thirdly, the conductive electrode 201 can be electrically connected to the bottom gate electrode 111 through the via hole disposed on the barrier layer 16 and the gate insulating layer 12 .

Fourth, the material of the semiconductor active layer 13 is not limited, it can be made of amorphous silicon, oxide, organic and other materials.

In addition, the type of the double-gate TFT is not limited, it may be a back channel type, or an etch barrier type, which may be based on the material of the semiconductor active layer 13 and the process for forming the source electrode 141 and the drain electrode 142. depends.

An embodiment of the present invention provides an array substrate. By providing a light blocking structure 20, on the one hand, the light blocking structure 20 can be used as a black matrix, and the preparation process of the black matrix can be omitted. Therefore, when the array substrate is applied to a display panel, The process can be simplified; on the other hand, the light-shielding structure 20 includes the conductive electrode 201, and the conductive electrode 201 is electrically connected to the bottom gate electrode 111, so that a double-gate thin film transistor structure can be formed on the array substrate, thereby improving the performance of the display panel. display quality.

Preferably, as shown in FIG. 3 , the width of the data line 143 is 5-10 μm; the light blocking structure 20 is arranged along the direction of the gate line 112 .

Here, when the data line 143 is widened, it is possible to avoid color crossing between adjacent sub-pixels of different colors located on both sides of the data line 143. Therefore, when the light blocking structure 20 is provided, it is not necessary to consider its need to prevent The role of cross-color.

On this basis, the light-shielding structure 20 only needs to consider shielding the channel region, even the TFT, and preventing pixel light leakage. However, due to the disorder of the electric field near the gate line 112, it is easy to cause pixel light leakage, and the TFT is also arranged close to the gate line 112, so , it only needs to arrange the light blocking structure 20 along the grid line 112 direction.

In the embodiment of the present invention, by widening the data line 143 on the existing basis, on the one hand, cross-color between sub-pixels can be avoided, and on the other hand, the light-shielding structure 20 can be simplified. Wherein, since the data line 143 is usually made of metal conductive material, and the metal conductive material is generally opaque, so it will not cause light leakage.

Further preferably, as shown in FIG. 4 , the gate metal layer 11 further includes a common electrode line 113, and the common electrode line 113 is disposed close to the gate line 112; the bottom gate electrode 111 is disposed on the side of the gate line 112 close to the common electrode line 113; The light blocking structure 20 is disposed between the gate line 112 and the common electrode line 113 .

Here, the common electrode line 113 is used to supply power to the common electrode. Since the common electrode is generally made of indium tin oxide (Indium Tin Oxide, ITO) material, its resistance is relatively large, and the resistance of the common electrode line 113 is relatively small. When the common electrode is connected to the common electrode line 113, the resistance of the common electrode can be reduced.

Wherein, the common electrode line 113, the bottom gate electrode 111, and the gate line 112 are prepared through the same patterning process.

It should be noted that, first, since the pixel electrode 30 needs to be electrically connected to the drain electrode 142, if the light blocking structure 20 is formed first and the pixel electrode 30 is formed later, the light blocking structure 20 can expose a part of the area above the corresponding drain electrode 142 In order to avoid a short circuit with the light blocking structure 20 when the pixel electrode 30 is electrically connected to the drain electrode 142 through the via hole.

Second, the light blocking structure 20 may cover the gate lines 112 and the common electrode lines 113 .

In the embodiment of the present invention, when the TFT is arranged between the gate line 112 and the common electrode line 113, the electric field in the area between the gate line 112 and the common electrode line 113 is relatively chaotic. Between the common electrode lines 113, light leakage of pixels can be avoided, and the TFT can be completely blocked to ensure the performance of the TFT.

Optionally, as shown in FIG. 2(a) and FIG. 2(b), the light blocking structure 20 may only include a conductive electrode 201, and the material of the conductive electrode 201 is an opaque conductive material.

In the embodiment of the present invention, since the conductive electrode 201 is made of an opaque conductive material, the conductive electrode 201 can also play a role of blocking light. However, the conductive electrode 201 can be formed through one patterning process, thereby simplifying the process flow.

Further preferably, the material of the conductive electrode 201 includes a black conductive polymer.

Here, the thickness of the conductive electrode 201 may be 1˜3 μm.

It should be noted that the material of the conductive electrode 201 is not limited to black conductive polymer, but can also be black metal or metal with blackened surface.

Wherein, the black conductive polymer can be, for example, taking the polymer as a matrix to dope nanometer metal materials; it is also possible to use a polymer as a matrix doping composite conductive material (conductive nanoparticle or conductive nanowire); wherein, the dopant composition accounts for 50%-70% of the mass of the polymer matrix; or directly use conductive polymer materials, such as polyaniline, polypyrrole, polythiophene and other conductive polymers and their derivatives.

Since the performance of the black conductive polymer is better, and it is easy to prepare a thicker conductive electrode 201 , the black conductive polymer can be used as the conductive electrode 201 .

Optionally, as shown in Figure 5(a) and Figure 5(b), the material of the conductive electrode 201 is a transparent conductive material; the light blocking structure 20 also includes a black resin layer arranged on the side of the conductive electrode 201 away from the substrate 10 202 ; the pattern of the black resin layer 202 is the same as that of the conductive electrode 201 .

Here, the thickness of the conductive electrode 201 may be 30-100 nm; the thickness of the black resin layer 202 may be 1-3 μm.

Specifically, the process of forming the conductive electrode 201 and the black resin layer 202 is as follows: sequentially forming a conductive film and a black resin film, exposing and developing the black resin film to form the black resin layer 202, and using the black resin layer 202 is a mask, and the conductive film is wet-etched to form the conductive electrode 201 with the same pattern as the black resin layer 202 .

In the embodiment of the present invention, the conductive electrode 201 plays the role of conducting electricity, and the black resin layer 22 plays the role of blocking light. The patterns of the two are the same, and can be prepared by the same patterning process, which simplifies the process flow.

Preferably, as shown in FIG. 6 and FIG. 7 , the array substrate further includes a color filter layer 40 .

Wherein, since the surface of the color filter layer 40 is not flat after being formed, a flat layer 50 may also be formed on the surface of the color filter layer 40 .

In the embodiment of the present invention, the color filter layer 40 is directly formed on the array substrate, which can increase the aperture ratio of the display panel and increase the brightness of the display panel.

Preferably, as shown in FIG. 6 and FIG. 7 , the semiconductor active layer 13 is an oxide semiconductor active layer.

Here, the material of the semiconductor active layer 13 may be, for example, amorphous indium gallium zinc oxide.

Wherein, when the semiconductor active layer 13 is an oxide semiconductor active layer, as shown in FIG. 6, a back channel type thin film transistor can be formed. At this time, the etchant when forming the source and drain electrodes can be controlled, such as hydrogen peroxide The etchant of the system is used to avoid the influence on the oxide semiconductor active layer.

As shown in FIG. 7, an etch-stop thin film transistor can also be formed, that is, an etch-stop layer 17 is formed on the surface of the oxide semiconductor active layer away from the substrate 10, so as to avoid damage to the oxide semiconductor when forming source and drain electrodes. In this case, any etching solution can be used when forming the source and drain electrodes.

Since oxide semiconductors have advantages such as high carrier mobility, low preparation temperature, excellent large-area uniformity, and high optical transmittance, oxide semiconductors are preferred as the material of the semiconductor active layer 13 in the embodiment of the present invention.

Preferably, as shown in FIG. 8 , the array substrate further includes a common electrode 60 .

A specific embodiment is provided below to illustrate the method for preparing the array substrate in detail.

As shown in FIG. 9, forming the array substrate may include the following steps:

S10 , referring to FIG. 4 and FIG. 7 , sequentially form a gate metal layer 11 , a gate insulating layer 12 , a semiconductor active layer 13 , an etching stopper layer 17 and a source-drain metal layer 14 on the substrate 10 .

Wherein, the gate metal layer 11 includes a bottom gate electrode 111 , a gate line 112 and a common electrode line 113 . The source-drain metal layer 14 includes a source electrode 141 , a drain electrode 142 and a data line 143 ; the width of the data line 143 is 5-10 μm. The semiconductor active layer 13 is an oxide semiconductor active layer.

Specifically, a layer of metal thin film can be prepared on the substrate 10 by magnetron sputtering. The metal material can usually be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. Combination structures of thin films of different materials. Then, a gate metal layer 11 is formed on the substrate 10 through patterning processes such as exposure, development, etching, and lift-off using a mask.

Further, an insulating film can be deposited on the substrate by using plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD). The material of the insulating film is usually silicon nitride, and silicon oxide and silicon oxynitride can also be used to form Gate insulating layer 12.

Further, through deposition, exposure, development, etching, stripping and other patterning processes, an oxide semiconductor active layer is formed on the substrate above the bottom gate electrode 111 , and then an etching stopper layer 17 and a source/drain metal layer 14 are formed.

S11 , referring to FIG. 7 , on the basis of S10 , forming a barrier layer 16 .

Specifically, through deposition, exposure, development, etching and other patterning processes, the barrier layer 16 is formed. The barrier layer 16 includes a via hole exposing the bottom gate electrode 111, and the via hole also cuts through the gate insulating layer 12. In addition A via hole exposing the drain electrode 142 is also included.

Wherein, the barrier layer 16 may have a thickness of 200-800 nm. The material may be silicon dioxide (SiO ₂ ) and/or silicon nitride (Si ₃ N ₄ ). It may be a one-layer structure, or may be a two-layer or more structure.

S12 , referring to FIG. 4 and FIG. 7 , on the basis of S11 , forming a light blocking structure 20 .

Wherein, the light blocking structure 20 only includes a conductive electrode 201, and its material is an opaque conductive material, for example, a polymer matrix doped with a nano-metal material is used, and the doping component accounts for 50% to 70% of the mass of the polymer matrix; The conductive electrode 201 may have a thickness of 2 μm.

The light blocking structure 20 is disposed between the gate line 112 and the common electrode line 113 . The light-shielding structure 20 can expose a part of the area above the corresponding drain electrode 142 , so as to avoid a short circuit with the light-shielding structure 20 when the pixel electrode 30 is electrically connected to the drain electrode 142 through a via hole.

Specifically, the conductive electrode 201 may be formed between the gate line 112 and the common electrode line 113 through patterning processes such as coating, exposure, and development.

S13 , referring to FIG. 7 , on the basis of S12 , sequentially form a color filter layer 40 , a flat layer 50 , and a pixel electrode 30 .

On this basis, as shown in FIG. 8 , a passivation layer and a common electrode 60 may also be formed.

The formation of the color filter layer 40 , the flat layer 50 , the pixel electrode 30 , the passivation layer, and the common electrode 60 all adopt conventional processes, which will not be repeated here.

An embodiment of the present invention further provides a display panel, as shown in FIG. 10 , including the above-mentioned array substrate.

Wherein, the displayed display panel may be a liquid crystal display panel.

In addition, an embodiment of the present invention also provides a display device, including the display panel.

Wherein, the display device may be, for example, a liquid crystal display, a liquid crystal TV, a digital photo frame, a mobile phone, a tablet computer, and other products or components with any display function.

The embodiment of the present invention provides a display panel. By disposing the light blocking structure 20 on the array substrate, on the one hand, the light blocking structure 20 can be used as a black matrix, and the preparation process of the black matrix can be omitted. Therefore, when the array substrate is applied to When displaying a panel, the process can be simplified; on the other hand, the light-shielding structure 20 includes a conductive electrode 201, and the conductive electrode 201 is electrically connected to the bottom gate electrode 111, so that a double-gate TFT structure can be formed on the array substrate, thereby improving the display performance. The display quality of the panel.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. An array substrate, characterized in that it comprises: a substrate, a gate metal layer, a gate insulating layer, a semiconductor active layer, a source-drain metal layer, a barrier layer, and a light-shielding structure sequentially arranged on the substrate ; The gate metal layer includes a bottom gate electrode and a gate line; the source-drain metal layer includes a source electrode, a drain electrode, and a data line; The light blocking structure includes a conductive electrode, and the conductive electrode is electrically connected to the bottom gate electrode; Wherein, the opaque light-shielding structure also functions as a black matrix. 2. The array substrate according to claim 1, wherein the width of the data line is 5-10 μm; The light blocking structure is arranged along the grid line direction. 3. The array substrate according to claim 2, wherein the gate metal layer further comprises a common electrode line, and the common electrode line is disposed close to the gate line; The bottom gate electrode is disposed on a side of the gate line close to the common electrode line; The light blocking structure is disposed between the gate lines and the common electrode lines. 4 . The array substrate according to claim 1 , wherein the material of the conductive electrode is an opaque conductive material. 5 . The array substrate according to claim 4 , wherein the material of the conductive electrode comprises a black conductive polymer. 6. The array substrate according to claim 1, wherein the material of the conductive electrode is a transparent conductive material; The light blocking structure further includes a black resin layer disposed on a side of the conductive electrode away from the substrate; the pattern of the black resin layer is the same as that of the conductive electrode. 7. The array substrate according to any one of claims 1-6, further comprising a color filter layer. 8 . The array substrate according to claim 1 , wherein the semiconductor active layer is an oxide semiconductor active layer. 9 . The array substrate according to claim 8 , further comprising an etching stopper layer disposed on a surface of the oxide semiconductor active layer away from the substrate. 10. A display panel, comprising the array substrate according to any one of claims 1-9.