CN106201973B - Method and system for single-wire serial communication interface - Google Patents
Method and system for single-wire serial communication interface Download PDFInfo
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- CN106201973B CN106201973B CN201610515190.XA CN201610515190A CN106201973B CN 106201973 B CN106201973 B CN 106201973B CN 201610515190 A CN201610515190 A CN 201610515190A CN 106201973 B CN106201973 B CN 106201973B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The invention discloses a method and a system of a single-wire serial communication interface, wherein the method is applied to a single-wire serial communication interface device, the single-wire serial communication interface device comprises a control module, a physical layer module, a receiving module and a sending module, a host computer communicates with a slave device through the single-wire serial communication interface, and the host computer sends signals to the physical layer module; the physical layer module synchronizes signals; the control module controls the receiving module to receive a read-write signal sent by the host, wherein the read-write signal comprises a slave device address, a read-write mode signal and a register address, and parity check is carried out on the read-write signal; the control module controls the sending module to send the read-write signal to the slave device. The single-wire interface device belongs to a one-wire interface, realizes the data exchange function between equipment simply and conveniently, provides a practical choice for circuit design engineers, greatly reduces the area of an interface chip and the number of pins, and reduces the interconnection cost.
Description
Technical Field
The invention relates to the technical field of serial communication, in particular to a method and a system of a single-wire serial communication interface.
Background
With the development of society, more and more electronic devices have come into the lives of people, the communication between the electronic devices is more and more frequent, and how to select the interface between the devices is particularly important. In the field of low speed serial communications, circuit design engineers typically use the I2C bus developed by Philips. The I2C bus belongs to a two-wire interface, and the I2C (Inter-integrated circuit) bus is a two-wire serial bus developed by PHILIPS corporation for connecting a microcontroller and its peripherals. Is a bus standard widely adopted in the field of microelectronic communication control. The I2C bus supports any IC manufacturing process (CMOS, bipolar). Information is transferred between devices connected to the bus through a Serial Data (SDA) line and a Serial Clock (SCL) line. Each device has a unique address identification (whether a microcontroller-MCU, LCD driver, memory or keyboard interface) and can act as a transmitter or receiver (determined by the function of the device). The LCD driver can only act as a receiver and the memory can both receive and transmit data. In addition to the transmitter and receiver, a device may also be considered a master or a slave when performing data transmission. The host is a device that initiates data transfers of the bus and generates a clock signal that allows the transfers. At this point, any addressed device is considered a slave.
Those skilled in the art are still striving to reduce the area of the interface chip and the number of pins.
Disclosure of Invention
In order to overcome the defects of the prior art, one of the purposes of the present invention is to provide a method for a single-wire serial communication interface, which can solve the problems of large chip area and large pin number of the interface.
The second purpose of the invention is to provide a system of single-wire serial communication interface, which can solve the problems of large chip area and large pin number of the interface.
One of the purposes of the invention is realized by adopting the following technical scheme:
a method of single-wire serial communication interface is applied to a single-wire serial communication interface device, the single-wire serial communication interface device comprises a control module, a physical layer module, a receiving module and a transmitting module, a host computer communicates with a slave device through the single-wire serial communication interface device, and the method comprises the following steps:
s1: the control module controls the receiving module to receive the read-write signal sent by the host, judges a read-write mode signal in the read-write signal, if the read-write mode is a read mode, executes step S2, and if the read-write mode is a write mode, executes step S4, wherein the read-write signal further comprises a slave device address and a register address of the slave device, and the register address of the slave device and a register of the corresponding slave device form a one-to-one correspondence relationship;
s2: the control module controls the receiving module to read the read data from the register of the corresponding slave device according to the register address of the slave device, and then step S3 is executed;
s3: the control module controls the sending module to receive a reply reading signal of the slave device;
s4: the control module controls the receiving module to write the write data from the register of the corresponding slave device according to the register address of the slave device, and step S5 is executed;
s5: the control module controls the sending module to receive a reply write signal of the slave device so as to inform the host that the write data is successfully written.
Preferably, step S1 is preceded by the steps of:
s00: the host sends a synchronous signal to the physical layer module;
s01: the physical layer module synchronizes the synchronization signal, and transmits a synchronization failure message to the host if the synchronization fails, and performs step S1 if the synchronization succeeds. The technical problem of synchronization of the physical layer modules can be further solved.
Preferably, in step S1, the read/write signal further includes a first parity signal, the receiving module checks the first parity signal, and if the first parity signal is correct, the receiving module transmits a parity result signal to the sending module, and if the first parity signal is incorrect, the receiving module uploads an error message to the host. The technical problem of parity check of read-write signals can be further solved.
Preferably, in step S3, the reply read signal includes a correctly received signal from the device address and the host read command. The problem of replying to a particular signal of the read signal can be further solved.
Preferably, in step S3, the reply read signal includes a second parity signal, the sending module checks the second parity signal, and if the second parity signal is correct, the sending module transmits a parity result signal to the host, and if the second parity signal is incorrect, the sending module uploads an error message to the host. The technical problem of parity checking of the reply read signal can be further solved.
Preferably, in step S5, the reply write signal includes a correct receipt signal from the device address and the host write command. The technical problem of parity checking in reply to the write signal can be further solved.
Preferably, in step S5, the reply write signal includes a third parity signal, the sending module checks the third parity signal, if correct, transmits a parity result signal to the host, and if wrong, uploads an error message to the host. The technical problem of replying to write good parity can be further solved.
The second purpose of the invention is realized by adopting the following technical scheme:
the system of the single-wire serial communication interface comprises a single-wire serial communication interface device, a host and a slave device, wherein the single-wire serial communication interface device applies the method, and the host and the slave device carry out data communication through the single-wire serial communication interface device.
Preferably, the number of the slave devices is plural. The technical problem of the number of slave devices can be further solved.
Compared with the prior art, the invention has the beneficial effects that:
the single-wire interface device belongs to a one-wire interface, realizes the data exchange function between equipment simply and conveniently, provides a practical choice for circuit design engineers, greatly reduces the area of an interface chip and the number of pins, and reduces the interconnection cost. The device has low design technology threshold and flexible and simple debugging, and is easy to integrate on a silicon chip, thereby having good market application value.
Drawings
FIG. 1 is a flow chart of a single-wire serial communication interface method of the present invention;
FIG. 2 is a state machine diagram of a control module according to the present invention;
FIG. 3 is a diagram of a physical layer module state machine according to the present invention;
FIG. 4 is a diagram of a state machine of a receiving module according to the present invention;
FIG. 5 is a diagram of a state machine of a sending module according to the present invention;
FIG. 6 is a schematic diagram of a communication structure according to the present invention;
FIG. 7 is a timing diagram of host write commands according to the present invention;
FIG. 8 is a timing diagram illustrating the response of a slave device to a write command in accordance with the present invention;
FIG. 9 is a timing diagram of host read commands according to the present invention;
FIG. 10 is a timing diagram illustrating the response of a slave device to a read command according to the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and the detailed description below:
as shown in fig. 1, the present invention provides a method of a single-wire serial communication interface, which is applied to a single-wire serial communication interface device, where the single-wire serial communication interface device includes a control module, a physical layer module, a receiving module, and a transmitting module, and a host communicates with a slave device through the single-wire serial communication interface device, and the method includes the following steps:
s00: the host sends a synchronous signal to the physical layer module;
s01: the physical layer module synchronizes the synchronization signal, if the synchronization fails, a synchronization failure message is sent to the host, and if the synchronization succeeds, step S1 is executed;
s1: the control module controls the receiving module to receive the read-write signal sent by the host, judges a read-write mode signal in the read-write signal, if the read-write mode is a read mode, executes step S2, and if the read-write mode is a write mode, executes step S4, wherein the read-write signal further comprises a slave device address and a register address of the slave device, and the register address of the slave device and a register of the corresponding slave device form a one-to-one correspondence relationship; the read-write signal also comprises a first parity check signal, the receiving module checks the first parity check signal, if the first parity check signal is correct, the parity check result signal is transmitted to the sending module, and if the first parity check signal is wrong, error information is uploaded to the host.
S2: the control module controls the receiving module to read the read data from the register of the corresponding slave device according to the register address of the slave device, and then step S3 is executed;
s3: the control module controls the sending module to receive a reply reading signal of the slave device; the reply read signal comprises a signal correctly received from the device address and the host read command; the reply reading signal comprises a second parity check signal, the sending module checks the second parity check signal, if the second parity check signal is correct, the parity check result signal is transmitted to the host, if the second parity check signal is incorrect, error information is uploaded to the host, and the host reads the command that the signal is correctly received to confirm the first parity check result.
S4: the control module controls the receiving module to write the write data from the register of the corresponding slave device according to the register address of the slave device, and step S5 is executed;
s5: the control module controls the sending module to receive a reply write signal of the slave device so as to inform the host that the write data is successfully written; the reply write signal includes a correctly received signal from the device address and the host write command. The reply write signal comprises a third parity check signal, the sending module checks the third parity check signal, if the third parity check signal is correct, the sending module transmits a parity check result signal to the host, and if the third parity check signal is incorrect, the sending module uploads error information to the host.
The specific working principle of each module state machine of the invention is as follows:
the sending module, the control module, the receiving module and the physical layer module are in parallel relation. The sending module state machine, the control module state machine, the receiving module state machine and the physical layer module state machine can perform state transition according to the preset state according to the control signal, so that the actions of related signals are coordinated, and specific operation is completed.
As shown in fig. 2, which is a schematic diagram of a control module state machine of the present invention, a RECP state (i.e., a receiving state) is defaulted, a SHFT state (i.e., a transfer state) is switched after receiving is completed, a TRAN state (i.e., a transmission state) is switched after waiting for 4 bit periods, an ENDP state (i.e., an end state) is switched after sending is completed, and at this time, a read-write flow is ended and a RECP state is returned. The control module performs overall control of signal transmission, signal reading, transmission and reception conversion, and process termination as a whole. Each state represents a trigger state and when this state is reached, what control is performed.
As shown in fig. 3, a schematic diagram of a state machine of a physical layer module according to the present invention is a state machine of a physical layer module, which defaults to an IDLE state (i.e., an IDLE state), and after detecting a falling edge of an input signal, the state machine transitions to a SYN0 state (i.e., a first synchronization state), and after a low level continues for a period of time, the state machine transitions to a SYN1 state (i.e., a second synchronization state), and after detecting a high level continues for a period of time, the state machine transitions to a SYN2 state (i.e., a third synchronization state), and after detecting a low level continues for a period of time, the state machine transitions to a SYN3 state (i.e., a fourth synchronization state), and the synchronization succeeds. If the time spent in the SYN1 state is too long, error is reported and the IDLE state is returned
As shown in fig. 4, a schematic diagram of a state machine of a receiving module of the present invention is shown, which defaults to SYNC state (i.e. synchronization state), when the state machine of the physical layer is SYN2 state (third synchronization state), the receiving module goes to SRCE state (receiving state), receives a formhost read/write signal, goes to DEVC state (receiving state) after 1 signal cycle, receives a slave address signal, goes to PARI state if it is our slave address signal after 2 signal cycles, goes to ENDP state if it is not, receives a parity check signal in PARI state (i.e. parity check state), goes to MODE state (i.e. MODE state) after 1 signal cycle, receives a read/write signal, goes to ANTI state (i.e. ANTI logic state) after 1 signal cycle, goes to ADDR state (i.e. address receiving state) after 1 signal cycle, receives 8bits register address, after 9 signal periods, if the read mode is changed to the ENDP state, if the read mode is changed to the WDAT state (namely, the data writing state), if the write mode is changed to the WDAT state, the WDAT state receives 8bits of write data, and after 9 signal periods, the WDAT state is changed to the ENDP state (ending state), at this moment, the receiving process is ended, and the SYNC state (synchronous state) is returned. This is a specific implementation of S3.
As shown in fig. 5, a schematic diagram of a state machine of a sending module of the present invention is default to IDLE state (IDLE state), when the state machine of the sending module is controlled to be turned to TRAN (transmission state), and when the sending module is turned to SYNC state (synchronous state) during preparation for sending, the sending module is turned to SRCE (extraction state) after sending 3bits of synchronization code, the sending module is turned to ADDR state (address state) after sending 1bits of from device, the sending module is turned to PARI state (parity state) after sending 2bits of device address, the sending module is turned to CHEK state (check state) after sending parity check result of 1bits of receiving module, the sending module is turned to ANTI state after sending 1bits of parity check, the sending module is turned to ENDP state after sending 1bits of ANTI-logic signal, if it is a response write command, the sending module is turned to RDAT state (read data state), the sending 8bits of ANTI-logic signal and 1bits of ANTI-logic signal, the module is turned to ENDP state (end state), the transmission flow ends, and the IDLE state (IDLE state) is returned. This is a specific implementation of S3 and S5.
As shown in fig. 6, which is a schematic diagram of a communication structure of the present invention, wherein sda is a data signal line, the present invention further provides a system of a single-wire serial communication interface, which includes a single-wire serial communication interface apparatus, a host (host) and a slave (device), wherein the host sends a signal to the single-wire serial communication interface apparatus, and the slave extracts a read/write signal from the single-wire serial communication interface apparatus. Wherein, the number of the slave devices is four.
The host write command and slave reply write command are described in detail in this embodiment with register address D8h and write data 75 h. The foregoing method is mainly based on a single-wire serial communication interface device, and the communication process thereof is described in detail, fig. 7 and 8 specifically illustrate the communication mechanism by a host write command and a slave device responding to a write command, and fig. 9 and 10 specifically illustrate the communication mechanism by a host read command and a slave device responding to a read command.
As shown in fig. 7, in the host write command timing diagram of the present invention, the first 3bits of the first phase are sync code010b, the 4 th bit is from host (0b) flag, the 5 th and 6 th bits are devicedaddress (slave device address) (00b, 01b, 10b, 11b), the 7 th bit is parity, which is calculated by 16 bits of register address and write data, the 8 th bit is write (0b) (write data) flag, and the 9 th bit is the reverse direction (1b) of the 8 th bit. second phase represents an 8-bit register address, where the 5 th bit is the inverse of the 4 th bit. third phase represents 8 bitwrite data (write data), where the 5 th bit is the reverse of the 4 th bit.
As shown in fig. 8, in the timing chart of the response of the slave device to the write command, the first 3bits of the first phase are sync code010b, the 4 th bit is from device (1b) (slave device) flag, the 5 th and 6 th bits are device address (i.e. slave device address) (00b, 01b, 10b, 11b), the 7 th bit is flag correctly received by the Host write command, the 8 th bit is parity bit set to 0b, and the 9 th bit is the reverse (1b) of the 8 th bit.
As shown in FIG. 9, in the timing diagram of the host read command of the present invention, the first 3bits of the first phase are sync code010b, the 4 th bit is from host (0b) flag, the 5 th and 6 th bits are device address (00b, 01b, 10b, 11b), the 7 th bit is parity, which is calculated by 8bits of the register address, the 8 th bit is read (1b) flag, and the 9 th bit is the reverse (0b) of the 8 th bit. second phase represents an 8bits register address, where the 5 th bit is the reverse of the 4 th bit.
As shown in fig. 10, in the timing chart of the slave device responding to the read command, the first 3bits of the first phase are sync 010b, the 4 th bit is a from device (1b) flag, the 5 th and 6 th bits are device addresses (00b, 01b, 10b, 11b), the 7 th bit is a flag correctly received by the Host read command, the 8 th bit is a parity bit, which is calculated by 8bits in total from readdata, and the 9 th bit is the reverse direction of the 8 th bit. second phase represents 8bits readdata, where the 5 th bit is the inverse of the 4 th bit.
Various other modifications and changes may be made by those skilled in the art based on the above-described technical solutions and concepts, and all such modifications and changes should fall within the scope of the claims of the present invention.
Claims (7)
1. A method of single-wire serial communication interface, applied to a single-wire serial communication interface device, the single-wire serial communication interface device comprising a control module, a physical layer module, a receiving module and a transmitting module, a host communicating with a slave device through the single-wire serial communication interface device, comprising the steps of:
s00: the host sends a synchronous signal to the physical layer module;
s01: the physical layer module synchronizes the synchronization signal, if the synchronization fails, a synchronization failure message is sent to the host, and if the synchronization succeeds, step S1 is executed;
s1: the control module controls the receiving module to receive the read-write signal sent by the host, judges a read-write mode signal in the read-write signal, if the read-write mode is a read mode, executes step S2, and if the read-write mode is a write mode, executes step S4, wherein the read-write signal further comprises a slave device address and a register address of the slave device, and the register address of the slave device and a register of the corresponding slave device form a one-to-one correspondence relationship; the read-write signal also comprises a first parity check signal, the receiving module checks the first parity check signal, if the first parity check signal is correct, the parity check result signal is transmitted to the sending module, and if the first parity check signal is wrong, error information is uploaded to the host;
s2: the control module controls the receiving module to read the read data from the register of the corresponding slave device according to the register address of the slave device, and then step S3 is executed;
s3: the control module controls the sending module to receive a reply reading signal of the slave device; the state machine of the receiving module is defaulted to be in a synchronous state, when the state machine of the physical layer is in a third synchronous state, the receiving module is switched to an SRCE receiving state, a read-write signal from a host is received, the state machine of the receiving module is switched to an DEVC receiving state after 1 signal period, a slave device address signal is received, after 2 signal periods, the slave device address signal is confirmed to be correct, the receiving module is switched to a parity check state, if the slave device address signal is incorrect, the receiving module is switched to an end state, the parity check state receives the parity check signal, after 1 signal period, the receiving module is switched to a mode state, the receiving module is switched to a read/write signal, after 1 signal period, the receiving module is switched to an inverted logic state after 1 signal period, the receiving module is switched to an address receiving state after 1 signal period, the receiving module receives an 8-bits register address, after 9 signal periods, the receiving module is switched to, at this moment, the receiving process is finished, and the synchronous state is returned;
s4: the control module controls the receiving module to write the write data from the register of the corresponding slave device according to the register address of the slave device, and step S5 is executed;
s5: the control module controls the sending module to receive a reply write signal of the slave device so as to inform the host that the write data is successfully written.
2. The method of single-wire serial communication interface of claim 1, wherein in step S3, said reply read signal includes a correctly received signal from a device address and a host read command.
3. The method of claim 1, wherein the reply read signal includes a second parity signal, the sending module checks the second parity signal, if correct, transmits a parity result signal to the host, and if incorrect, uploads an error message to the host in step S3.
4. The method for a single-wire serial communication interface of claim 1, wherein in step S5, said reply write signal includes a correctly received signal from a device address and a host write command.
5. The method of claim 1, wherein the reply write signal includes a third parity signal, the sending module checks the third parity signal, if correct, transmits a parity result signal to the host, and if incorrect, uploads an error message to the host in step S5.
6. A system of single-wire serial communication interface, comprising a single-wire serial communication interface apparatus applied to the method of claims 1 to 5, a host and a slave, wherein the host performs data communication with the slave through the single-wire serial communication interface apparatus.
7. The system of single-wire serial communication interface of claim 6, wherein said slave device is plural in number.
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| CN107748805B (en) * | 2017-09-06 | 2022-05-06 | 合肥市芯海电子科技有限公司 | Single-wire interface method for on-chip debugging |
| CN109902046B (en) * | 2019-02-01 | 2020-03-20 | 福瑞泰克智能系统有限公司 | Communication method for serial peripheral bus system, related equipment and system |
| CN110737622B (en) * | 2019-10-15 | 2021-05-07 | 上海智汇电器有限公司 | Single-wire bidirectional communication charging method |
| CN112564882B (en) * | 2020-11-26 | 2023-06-20 | 北京工业大学 | A single-wire digital communication interface based on AHB bus |
| CN120448323B (en) * | 2025-07-10 | 2025-09-30 | 安徽大学 | A method and system for improving I2C bus read and write efficiency and reliability |
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| TWI459207B (en) * | 2006-10-17 | 2014-11-01 | Monolithic Power Systems Inc | System and method for implementing a single-wire serial protocol |
| FR2948474A1 (en) * | 2009-07-22 | 2011-01-28 | Proton World Int Nv | COMMUNICATION PROTOCOL ON A UNIFIL BUS |
| US9569386B2 (en) * | 2013-04-16 | 2017-02-14 | Nxp B.V. | Method and system for single-line inter-integrated circuit (I2C) bus |
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