CN106201939A - Multinuclear catalogue concordance device towards GPDSP framework - Google Patents

Abstract

A multi-core directory consistency device for GPDSP architecture, including: a kernel, including DMA and L1D, L1D is a first-level data cache; the DMA is used to complete the transfer of data between peripherals and cores; the L1D includes Normal Deal and Monitor Deal two parallel processing units, the Normal Deal processing unit completes the processing of load and store instructions, and the Monitor Deal processing unit is used to respond to the monitoring request arriving at any time, and the processing process is not affected by the Normal Deal processing unit ; On-chip last-level Cache, which is distributed and connected to the on-chip interconnection network; off-chip storage DDR, data cached in L1D and on-chip last-level Cache; on-chip interconnection network, used to receive network requests, will receive network requests First, the decoding process is performed, and the destination node and the destination device are decoded, and the request is sent to the corresponding location. The invention has the advantages of simple principle, convenient operation, high flexibility, wide application range and the like.

Description

Multi-core directory consistency device for GPDSP architecture

technical field

The invention mainly relates to the field of processor micro-architecture design, in particular to a design suitable for multi-core storage paths of a General-Purpose Digital Signal Processor (GPDSP).

Background technique

As one of the troika (CPU, DSP and GPU) in the field of processors, DSP is widely used in embedded systems due to its advantages of high performance per power ratio, good programmability and low power consumption. Different from the CPU, DSP has the following characteristics: 1) Strong computing power, focusing on implementation calculations rather than control and transaction processing; 2) It has specialized hardware support for typical signal processing, such as multiplication and addition operations, circular addressing, etc.; 3 ) The common characteristics of embedded microprocessors, such as address and instruction path not more than 32 bits; imprecise interrupt; short-term offline debugging, long-term online resident running program working mode (rather than general-purpose CPU debugging and running method); 4 ) The integrated peripheral interface is mainly based on fast peripherals, which is especially conducive to online sending and receiving of AD/DA signals, and also supports high-speed direct connection between DSPs.

In view of DSP's high-performance power consumption ratio and powerful computing power, how to upgrade and improve the traditional DSP architecture to make it suitable for high-performance scientific computing is a research hotspot at home and abroad.

For example, a Chinese patent application (General Computing Digital Signal Processor, application number: 201310725118.6) proposes a multi-core microprocessor GPDSP that not only maintains the basic characteristics of DSP and has the advantages of high performance and low power consumption, but also can efficiently support general scientific computing. . The structure has the following characteristics: 1) It has direct representation of double-precision floating-point and 64-bit fixed-point data, the general-purpose register, data bus, and instruction bit width are 64 bits and above, and the address bus width is 40 bits and above; 2) CPU and DSP are different The structure is tightly coupled with multiple cores, the CPU core supports a complete operating system, and the scalar unit of the DSP core supports the micro-kernel of the operating system; 3) A unified programming model that considers the structure of the vector array in the CPU core, DSP core, and DSP core; 4) Maintains cross-simulation of other machines Debugging, while providing local CPU host debugging mode; 5) retaining the basic characteristics of ordinary DSP except the number of bits.

Another example is the Chinese patent application (GPDSP multi-level coordination and shared storage device-level memory access method, application number: 20150135194.0), aiming at the application requirements of GPDSP, it proposes a storage architecture with multi-level coordination and efficiency. Each DSP core contains global addressing and programmable local large-capacity scalar and vector array memory for programmers. Multiple DSP cores share large-capacity on-chip global Cache through the on-chip network; through direct memory access controller (DMA) and The network-on-chip provides high-bandwidth inter-core, in-core memory, and global Cache data interpretation, realizing the collaboration and sharing of data access within a single core and between multiple cores.

In GPDSP, the on-chip memory and DMA background transfer mechanism in the core are reserved, which will bring difficulties to the realization of data consistency. In the Chinese patent application (an explicit streaming application-oriented multi-core cache consistency active management method, application number: 201310166383.5), a software-programmable data consistency management method is adopted, and the work of maintaining data consistency is handed over to Programmers need to actively manage and maintain the correctness of the production and consumption process of data. If the hardware management hardware coherence protocol is adopted in GPDSP, it will be able to reduce the programming complexity of programmers and improve the versatility of GPDSP.

Contents of the invention

The technical problem to be solved by the present invention is that, aiming at the problems existing in the prior art, the present invention provides a multi-core directory consistency device for GPDSP architecture with simple principle, convenient operation, high flexibility and wide application range.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A multi-core directory consistency device for GPDSP architecture, including:

Kernel, including DMA and L1D, L1D is a first-level data cache; the DMA is used to complete the transfer of data between peripherals and the core; the L1D includes two parallel processing units, Normal Deal and Monitor Deal, and the Normal Deal processing The unit completes the processing of load and store instructions, and the Monitor Deal processing unit is used to respond to the monitoring request arriving at any time, and the processing process is not affected by the Normal Deal processing unit;

On-chip last-level Cache, distributed and connected to the on-chip interconnection network;

Off-chip storage DDR, its data will be cached in L1D and on-chip last-level Cache;

The on-chip interconnection network is used to receive network requests. After receiving network requests, it will first perform decoding processing, and after decoding the destination node and destination device, the request will be sent to the corresponding location.

As a further improvement of the present invention: the last stage Cache on the chip is divided into several individuals, each of which is composed of an input buffer unit IBUF, a pipeline unit PipeLine, an output buffer unit OBUF and a return ring network processing logic unit Rtn NAC; The input buffer unit is used to be responsible for buffering the request entering the final stage Cache from the on-chip network; the pipeline unit is used to perform pipeline processing on the access DDR storage space request from the input buffer; Level Cache accesses the request of the DDR; the return ring network processing logic unit is used to be responsible for arbitrating various types of incoming network-on-chip requests.

As a further improvement of the present invention: it also includes an MSI directory protocol unit, which is used to maintain the consistency of the request sent by the L1D; the MSI directory protocol unit is composed of three directory states of M, S, and I; the M state indicates that data is One DSPCore is exclusive and the data is dirty; the S state indicates that the data is shared by one or more DSP Cores and the data is clean; the I state indicates that all DSP Cores have no data copy.

As a further improvement of the present invention: it also includes a directory controller, which judges the correctness of the scheme at the protocol level, and is used to complete the processing of a single request in different directory states, the conflict processing of multiple related requests, and Response processing of data blocks in the "intermediate state" of the directory to related requests; the directory controller is divided into two types, one is placed in the L1D, and the other is placed in the last-level Cache on the chip, and the directory operation is performed on the L1D and on-chip It is performed in the last level Cache.

As a further improvement of the present invention: the directory structure of the complete directory is stored in the last-level Cache on the chip, and the directory structure allocates directory entries for each data block cached in the last-level Cache on the chip; the directory entries include directory status There are two parts and a sharing list, and the sharing list allocates one bit for each DSP Core to indicate whether the data is copied in the corresponding DSP Core.

As a further improvement of the present invention: a pipeline structure is adopted in the L1D to complete the pipeline process of instruction decoding, address calculation, reading flag and status bit, judging hit, data body access and data return operation.

As a further improvement of the present invention: the pipeline structure of the L1D is respectively DC1, DC2, EX1, EX2, EX3, EX4, EX5; when the L1D receives the load and store instructions, it first performs two-station pipeline decoding processing , that is, DC1 and DC2, to judge the operation type of the instruction and the function to be realized; after the instruction is decoded, the address calculation is performed, that is, EX1, to complete the function realization; then complete the L1DCache memory access pipeline that reads and executes 3 shots, and writes and executes 2 shots. Among them, the read operation pipeline is in the position of EX2, EX3, and EX4 in the mainstream pipeline of SMAC memory access, which are hit-miss judgment, memory access/missing processing, and memory access output; the write operation pipeline is in the position of EX2 and EX3, respectively. Fetch/miss handling.

As a further improvement of the present invention: a pipeline structure is used in the last stage Cache on the chip to realize the pipeline process of reading flags and status bits, reading directory entries, judging hits, monitoring processing, data body access and data return operations.

As a further improvement of the present invention: the pipeline structure of the last stage Cache on the chip comprises:

The first stage of the pipeline, Req_Arb: performs round-robin arbitration with the Flush request, and sends the arbitrated request to the next-level pipeline; at the same time, it also reads the valid bit, dirty bit, and Tag information of the requested data block;

The second stage of the pipeline Tag_Wait: determine whether it is a directory request, and read the directory information;

The third stage of the pipeline Tag_Judge: first judge whether the request is hit, if it is missing, then judge whether it is related to the address in MBUF; if it is a related missing request, send the request to MBUF; if it is an irrelevant missing request, send the request to To MBUF and OBUF; the hit request is processed according to whether it is a directory request; if it is a non-directory request, the access data body is enabled; if it is a directory request, check the directory item information, according to the directory status and share list The processing of different requests is also different; the processing methods of directory requests are divided into three types: the first type directly operates and generates the access data body enable; the second type waits for the return of L1D data, and generates the access data body after the data arrives. Enable; the third type waits for the Inv-Ack request, and generates the access data body after all invalid responses arrive;

The fourth stage of the pipeline, Data_Acc: first judge the type of the data body requested to be processed; if it is a read operation, read the requested data block from the data body and then latch it for one shot; if it is a write operation, first perform Encoding, and then update the data body operation; the request for data body read operation will finally send the read data to the next level of pipeline;

The fifth stage of the pipeline, Data_Dec: decodes the request data read by the upper stage, and sends the read back data request to the upper ring arbitration processing module for processing.

Compared with the prior art, the present invention has the advantages of:

1. The multi-core directory consistency device oriented to the GPDSP architecture of the present invention has simple principles, convenient operation, high flexibility, and wide application range. In addition to supporting data consistency maintenance for L1D requests, it also supports data consistency maintenance for DMA requests. , broaden the field of application.

2. The multi-core directory consistency device oriented to the GPDSP architecture of the present invention adopts a directory controller, and the directory controller mechanism can be used to judge the correctness of the multi-core data consistency scheme at the protocol level, which greatly shortens the design of the multi-core directory consistency device and validation cycle.

Description of drawings

Fig. 1 is a schematic diagram of the structure and principle of the present invention in a specific application example.

Fig. 2 is the schematic diagram of instruction processing principle in specific application example of the present invention; Wherein (a) is instruction processing principle diagram (1), (b) is instruction processing principle diagram (2), (c) is instruction processing principle diagram (3) ), (d) is a schematic diagram of primary data Cache replacement processing.

3 is a schematic diagram of the DMA processing principle in a specific application example of the present invention; wherein (a) is a schematic diagram of DMA read request processing, and (b) is a schematic diagram of DMA write request processing.

Fig. 4 is a directory structure diagram of a certain group in the last-level Cache directory storage body in a specific application example of the present invention.

FIG. 5 is a schematic diagram of the overall structure of the L1D pipeline in a specific application example of the present invention.

FIG. 6 is a schematic diagram of the overall structure of the last-stage Cache pipeline in a specific application example of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In a specific application example, the GPDSP architecture includes N cores; GetX request means GetS request or GetM request; Fwd-GetX request means Fwd-GetS request or Fwd-GetM request; PutX request means PutS request or PutM+data request; directory X The status indicates the directory S status or the directory M status; the directory Y status indicates the directory S status or the directory I status.

As shown in Figure 1, the multi-core directory consistency device for GPDSP architecture of the present invention includes:

Kernel, including DMA and Level 1 Data Cache (L1D); among them, DMA is used to transfer data between peripherals and kernel, and requires programmer configuration before starting. There are two parallel processing units, Normal Deal and Monitor Deal, in L1D. Among them, the Normal Deal processing unit completes the processing of load and store instructions. If the instruction is judged to be missing in L1D, it may need to be replaced; the Monitor Deal processing unit can respond to the monitoring request arriving at any time, and the processing process is not affected by the Normal Deal processing unit.

The on-chip last-level Cache is distributed and connected to the on-chip interconnection network, which can be divided into N individuals. Each body consists of an input buffer unit (IBUF), a pipeline unit (PipeLine), an output buffer unit (OBUF) and a return ring network processing logic unit (Rtn NAC). Among them, the input buffer unit is used to cache the request from the on-chip network to the last-level Cache; the pipeline unit is used to streamline the request from the input buffer to access the DDR storage space; the output buffer unit is used to cache the last-level Cache to access the DDR requests; the return ring network processing logic unit is responsible for arbitrating various types of incoming network-on-chip requests.

Off-chip storage DDR, also known as main memory, its data will be cached in L1D and last-level Cache.

The on-chip interconnection network is used to receive network requests. After receiving network requests, it will first perform decoding processing, and after decoding the destination node and destination device, the request will be sent to the corresponding location. In addition, the on-chip interconnection network can also process requests from the last-level Cache, and the principle is similar to the previous case. The network request is other requests except the local request, and the local request is a request sent by the core corresponding to each body in the last-level Cache.

Table 1 below is a detailed description of all directory requests, which includes all request types that may occur during directory operations, so as to facilitate the introduction of the directory consistency mechanism.

Table 1

In the specific application process of the present invention, the extended MSI directory protocol is further adopted. Firstly, the basic directory protocol is described in detail. The basic directory protocol only maintains the consistency of L1D.

After L1D receives the command, it will immediately operate on the command. Depending on the data block accessed by the instruction in the L1D cache and its dirty bit information, the processing process will be different. Among them, in the case of L1D read hit or dirty write hit, the instruction is directly processed. In all other cases, L1D will send a request to the last level Cache to trigger the next operation.

In the specific application process, as shown in Figure 2, the present invention can be divided into four categories according to the complexity of the operation, which are shown in Figure (a), Figure (b), Figure (c), and Figure (d) Condition.

Figure (a) is the instruction processing schematic diagram (1). It can be seen from the figure that the instruction is completed in two steps. Depending on the type of instruction, it can be divided into two cases. After an L1D read miss, a GetS request is generated and sent to the last-level Cache. After receiving the GetS request, the last-level Cache first checks the directory entry. Since the directory status is I or S, it indicates that the latest data is cached in the last level Cache. Therefore, the last-level Cache directly fetches the data and returns it to the request source; after an L1D write miss, a GetM request is generated and sent to the last-level Cache. After receiving the GetM request, the last-level Cache first checks the directory entry. Since the directory status is I, it indicates that the latest data is cached in the last level Cache. Therefore, the last-level Cache directly fetches the data and returns it to the requesting source.

Figure (b) is the instruction processing principle diagram (2). It can be seen from the figure that the instruction is completed in three steps. Depending on the type of instruction, it can be divided into two cases. After an L1D read miss, a GetS request is generated and sent to the last-level Cache. After receiving the GetS request, the last-level Cache first checks the directory entry. Since the status of the directory is M, it indicates that the latest data is not in the last level Cache. Therefore, the last-level Cache will send a Fwd-GetS request to the L1D that has the latest copy of the data. After the L1D receives the Fwd-GetS request, it will send a read and return data request to the last-level Cache and the request source at the same time, and change the local directory to the S state; after the L1D write is missing, it will generate a GetM request and send it to the last level Cache. After receiving the GetM request, the last-level Cache first checks the directory entry. Since the status of the directory is M, it indicates that the latest data is not in the last level Cache. Therefore, the last-level Cache will send a Fwd-GetM request to the L1D that has the latest copy of the data. After the L1D receives the Fwd-GetM request, it only sends a read return data request to the request source, and changes the local directory into the I state.

Figure (c) is the instruction processing schematic diagram (3). It can be seen from the figure that the instruction is completed in three steps. According to whether the instruction hits and whether the data is dirty, it can be divided into two situations. After an L1D write miss, a GetM request is generated and sent to the last-level Cache. After receiving the GetM request, the last-level Cache first checks the directory entry. Since the directory status is S, the last-level Cache will send an Inv-L request to all L1Ds that have data copies according to the shared list information, and at the same time read the data and return it to the requester with an Ack signal. After receiving the Inv-L request, L1D will invalidate the local data block and send an Inv-Ack request to the requester. Write-missing L1Ds do not perform write operations until they receive data and all invalid responses; L1Ds also generate GetM requests after clean write hits. Since its processing principle is consistent with the case of write miss, it will not be described here.

Figure (d) is a schematic diagram of L1D replacement processing. It can be seen from the figure that the instruction is completed in two steps. According to whether the data is dirty, it can be divided into two cases. When the replacement behavior is clean, L1D will send a PutS request to the last level Cache. After receiving the PutS request, the last-level Cache will update the shared list information. If the updated shared list is all zeros, the directory status needs to be modified to change to I. After the operation is completed, the last-level Cache will send a Put-Ack request to the requester; when the replacement behavior is dirty, L1D will send a PutM+data request to the last-level Cache. After receiving the PutM+data request, the last-level Cache will update the data body and directory information. After the operation is completed, the last level Cache will send a Put-Ack request to the requester.

In DSP, DMA is required to carry out a large number of data handling operations between the peripheral hardware and the core. If the consistency of DMA is not maintained, the problem of multi-core data inconsistency will inevitably arise; if the consistency of the software and hardware coordination mechanism of the synchronization unit is used for DMA, the programmer needs to monitor the processing of the storage space in real time, and it is not a small problem for the programmer. challenge. Therefore, the present invention extends the protocol of the basic directory protocol, so that it also supports the consistency maintenance operation on the DMA request. DMA directly accesses the last-level Cache through the interconnection network. According to different operations of accessing memory banks, DMA requests can be divided into two types, which are the situations shown in FIG. 3 .

Figure (a) is a schematic diagram of DMA read request processing. After receiving the DMA read request, the last-level Cache will check the directory information and perform corresponding processing according to the different directory information. When the directory is in the I and S state, since the latest data is in the last-level Cache, the DMA read request will directly return the data to the DMA; when the directory is in the M state, since the last-level Cache does not have the latest data, it will send the data to the owner The newly copied L1D sends a Fwd-Rd request. After receiving the Fwd-Rd request, the L1D will simultaneously send a read and return data request to the last-level Cache and DMA, and change the directory to the S state.

Figure (b) is a schematic diagram of DMA write request processing. After receiving the DMA write request, the last-level Cache will check the directory information and perform corresponding processing according to the different directory information. When the directory is in the I state, because the latest data is in the last-level Cache, the DMA write request will update the data body, and return a response signal to the DMA after the operation is completed; when the directory is in the M state, because there is no latest data, the last-level Cache A Fwd-Wrt request will be sent to the L1D which has the latest copy. After receiving the Fwd-Wrt request, the L1D only sends a read return data request to the last-level Cache, and invalidates the local data block. After the last-level Cache receives the latest data and returns it, it integrates with the data carried in the DMA write request, and then updates the data body and directory information. After the operation is completed, the last-level Cache will return a response signal to the DMA; when the directory is in the S state, the last-level Cache will send Inv-DE requests to all L1Ds that have data copies according to the shared list information. After receiving the Inv-DE request, these L1Ds will invalidate the local data block and send an Inv-Ack request to the last-level Cache. After receiving all invalid responses, the last-level Cache performs a write operation, and returns a response signal to the DMA after the operation is completed.

Directory operations are atomic, but there will be many conflicts in the design and implementation process. For example: From the global perspective of the chip, conflicts will occur when the next related directory request arrives before the processing of the previous directory request is completed. For these conflict situations, the present invention uses the directory controller mechanism to resolve them. According to the location of the directory controller, it is divided into two types, namely, the L1D directory controller and the last-level Cache directory controller.

Tables 2.1, 2.2, and 2.3 below are detailed descriptions of the L1D directory controller. It can be seen from the table that in addition to the three stable states of M, S, and I, there are many "intermediate" states in the data block directory state. For example: during the period from the L1D read miss to the return of the missing data, the data block accessed by the read request is always in the IS ^D state. The data block in the "intermediate" state can respond to some relevant monitoring requests, and can only perform stall processing for the monitoring requests that cannot be responded to. This not only ensures data consistency, but also improves system performance. For example: after L1D dirty replacement, the directory status of the replacement row changes to MI ^A . If the L1D receives a related Fwd-Rd request before the corresponding response signal arrives from the last-level Cache, it will respond immediately and change the directory status to ^SIA at the end of the operation.

Table 2.1

Table 2.2

Table 2.3

The L1D clean write hit operation in the directory protocol designed by the present invention is relatively special. Under normal circumstances, the request hit does not need to fetch data from the next level of Cache. To simplify directory protocol complexity, it is grouped with L1D write miss handling in the same category.

There are two types of invalid requests received by the L1D, which are Inv-L requests and Inv-DE requests. Because the directory protocol designed by the present invention adds the consistency maintenance to DMA, and adopts the mode of writing waste to operate. Therefore, when a DMA write request operates on the last-level Cache, the request sent to each Inv-DE that owns the data copy L1D should return a response signal to the last-level Cache. And L1D may also cause write waste operation (send Inv-L request) when executing the store command, but the invalid response signal is returned to L1D. For different types of invalid requests, the devices returned by the response signals are different. Therefore, the present invention classifies it.

After the invalid response (Inv-Ack) request arrives at L1D, it will deal with it according to the situation. If it is not the last invalid response request, the directory status of the corresponding data block is not changed; otherwise, the directory status of the corresponding data block is changed from ^IMA or ^SMA to M.

There are two sources of data read and return requests arriving at L1D, namely the last level Cache and other L1Ds. And because some data read and return requests need to carry Ack information (record the number of invalid responses that need to be returned), it needs to be processed differently. As shown in the first row of Table 2.3, the data read return request can be divided into: from the owner L1D without Ack, from the owner L1D with Ack, from the last-level cache without Ack, and from the last-level cache with Ack 0. It comes from the last level Cache and the Ack is greater than 0 in five situations.

Tables 3.1, 3.2, and 3.3 below are detailed descriptions of the last-level cache directory controller. Similar to the L1D directory controller, there is also an "intermediate" state in the last-level Cache directory controller. For example: after an L1D read miss, a GetS request is sent to the last-level Cache. When the data block accessed by the request is in the M state in the last-level Cache, the directory state will change to ^SD until the latest data is returned. The Inv-Ack request is similar to the L1D directory controller and will not be described here.

chart 3.1

Table 3.2

Table 3.3

L1D replacement is divided into clean row replacement and dirty row replacement.

Clean row replacement will send a PutS request to the last level cache. In actual operation, there may be multiple cores sharing a data block. At this time, the PutS request can be divided into two cases: not the last one (PutS-NotLast) and the last one (PutS-Last) according to the order of arriving at the last level Cache. When the PutS-NotLast request is processed, the directory status of the data block does not change, but only the corresponding share list information changes. When the PutS-Last request is processed, the directory status of the data block changes from S to I, and the corresponding share list information is cleared.

Dirty row replacement will send a PutM+data request to the last level Cache. The directory entry of the data block accessed by the request may have changed before the request is processed, which needs to be handled differently. If the status of the data block directory accessed by the dirty row replacement request is M and the L1D indicated by the shared list happens to be the L1D for the dirty row replacement, it is called a PutM+data from Owner request. In this case, the dirty replacement data will update the last-level Cache data body and return a response request; otherwise, the dirty row replacement request is called a PutM+data from Non-Owner request. In this case, simply return the reply request.

The present invention designs the directory consistency mechanism based on the last-level Cache, and the directory structure diagram of a certain group in the last-level Cache directory storage body is shown in FIG. 4 . It can be seen from the figure that the last-level Cache adopts an 8-way set-associative mapping mechanism, and assigns a directory entry to each way. A directory entry consists of two parts: directory status and share list. Wherein, the directory status indicates whether the cached data block has the latest data in the last-level cache and whether it is dirty data; the sharing list indicates the copy status of the cached data block in the first-level storage. Combined with the directory status and shared list information, the specific situation of the cache data block on the slice can be clearly known, so as to facilitate its consistency maintenance operation.

The directory mechanism will vary with different pipelines in the implementation process. The present invention briefly describes the implementation of pipelines in L1D and last-level Cache by way of example.

As shown in FIG. 5 , it is a schematic diagram of the overall structure of the L1D pipeline in a specific application example. Its assembly line consists of seven stages, namely DC1, DC2, EX1, EX2, EX3, EX4, EX5. After L1D receives the load and store instructions, it first performs two-station pipeline decoding processing (DC1 and DC2) to judge the operation type of the instruction and the function to be realized. Address calculation (EX1) is performed after instruction decoding is completed. Next, is the process of function realization. The present invention designs an L1DCache memory access pipeline with 3 shots for reading and 2 shots for writing. Among them, the read operation pipeline is in the positions of EX2, EX3, and EX4 in the mainstream pipeline of SMAC memory access, which are hit-miss judgment, memory access/missing processing, and memory access output respectively; the write operation pipeline is in the positions of EX2 and EX3, which are miss judgment respectively. , Fetching/missing handling. As part of the main pipeline of scalar memory access, the L1DCache pipeline is also controlled by the kernel global pause signal (Stall) and the pipeline clear signal.

As shown in FIG. 6 , it is a schematic diagram of the overall structure of the last-stage Cache pipeline in a specific application example. It can be seen from the figure that requests entering the last-level Cache will take two different paths in the pipeline. The read return request of L1D or the invalid response request returned by L1D does not need to be cached in the input buffer, but directly passed to the Tag_Judge station of the pipeline through the bypass, which is the first path; the data request for accessing the DDR storage space needs to be cached in the input buffer first. In buffering, pipeline processing starts from the first stage pipeline, which is the second path. The pipeline consists of five stages, namely Req_Arb, Tag_Wait, Tag_Judge, Data_Acc, Data_Dec.

The functions realized by each level of pipeline are described in detail below.

The first stage of the pipeline (Req_Arb): The request performs round-robin arbitration with the Flush request in this station, and sends the arbitrated request to the next-level pipeline. At the same time, the valid bit, dirty bit and Tag information of the requested data block will be read.

The second stage of the pipeline (Tag_Wait): the request at this station is only to judge whether it is a directory request, and to read the directory information.

The third stage of the pipeline (Tag_Judge): first judge whether the request is hit, if it is missing, then judge whether it is related to the address in the MBUF. If it is a relevant missing request, send the request to MBUF; if it is an irrelevant missing request, send the request to MBUF and OBUF. The hit request is processed accordingly according to whether it is a directory request. If it is a non-directory request, it will generate the access data body enable; if it is a directory request, it will check the directory item information, and the processing of different requests is different according to the directory status and the shared list. The processing methods of directory requests are divided into three categories: the first category directly operates and generates access data body enable; the second category needs to wait for the return of L1D data because the latest data is not in the last-level cache, and generates it after the data arrives Access to the data body is enabled; the third type needs to wait for the Inv-Ack request, and the access to the data body is enabled after all invalid responses arrive.

The fourth stage of the pipeline (Data_Acc): first judge the category of the requested processing data body. If it is a read operation, read the requested data block from the data body and then latch it for one beat; if it is a write operation, first encode the written data, and then perform the operation of updating the data body. A request for a data volume read operation will finally send the read data to the next-level pipeline.

The fifth stage of the pipeline (Data_Dec): decodes the request data read by the upper stage, and sends the request to read the returned data to the upper ring arbitration processing module for processing.

The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (9)

1. the multinuclear catalogue concordance device towards GPDSP framework, it is characterised in that including:

Kernel, comprising DMA and L1D, L1D is level one data Cache；Described DMA has been used for removing of peripheral hardware and interior internuclear data Fortune；Described L1D includes Normal Deal and two parallel processing elements of Monitor Deal, described Normal Deal process Unit completes the process of load, store instruction, and described Monitor Deal processing unit is used for responding the prison that any time arrives at Listen request, and processing procedure is not affected by Normal Deal processing unit；

Final stage Cache on sheet, distributed is connected on on-chip interconnection network；

Sheet external memory DDR, data buffer storage is on L1D and sheet in final stage Cache；

On-chip interconnection network, is used for receiving network request, can first carry out decoding process, decode out mesh after receiving network request Node and purpose equipment after request is sent to the position of correspondence.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 1, it is characterised in that described Be divided into several body in upper final stage Cache, each described body by input buffer cell IBUF, pipelined units PipeLine, Output buffer cell OBUF and return looped network process logical block Rtn NAC composition；Described input buffer cell is used for being responsible for Cache the request entering final stage Cache from network-on-chip；Described pipelined units is used for depositing the access DDR from input buffering The request of storage space carries out streamlined process；Described output buffer cell is used for being responsible for caching final stage Cache and accesses the request of DDR； Described return looped network processes logical block and is used for being responsible for the request of polytype entrance network-on-chip is carried out arbitration process.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 1 and 2, it is characterised in that also wrap Including MSI directory protocol unit, the request being used for sending L1D carries out consistency maintenance；Described MSI directory protocol unit by M, S, Tri-directory states compositions of I；M state represents that data are by certain DSP Core is exclusive and data are dirty；S state represents that data are by one Individual or multiple DSP Core share and data are clean；I state represents that all of DSP Core does not has data to copy.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 3, it is characterised in that also include Contents controller, described contents controller judges the correctness of scheme on protocol hierarchy, has been used for single request not With the process under directory states, the clash handle of multiple association requests and be in the data block of catalogue " intermediate state " to relevant please The response asked processes；Described contents controller is divided into two classes, a class to be placed in L1D, another kind of is placed on final stage Cache on sheet In, directory operation is carried out in final stage Cache on L1D and sheet.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 3, it is characterised in that described Depositing the bibliographic structure of complete catalogue in upper final stage Cache, described bibliographic structure is be buffered on sheet in final stage Cache every One data block distribution directory entry；Described directory entry includes directory states and shared list two parts, and described shared list is each Individual DSP Core distributes one and represents whether data exist copy in corresponding DSP Core.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 1 and 2, it is characterised in that in institute State employing pipeline organization in L1D, in order to complete Instruction decoding, address computation, read flag and mode bit, judgement hit, data Body accesses and data return the fluvial processes operated.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 6, it is characterised in that described L1D Pipeline organization be respectively DC1, DC2, EX1, EX2, EX3, EX4, EX5；After L1D receives load, store instruction, first First its decoding carrying out two station flowing water is processed, i.e. DC1 and DC2, it is judged that the action type of instruction and function to be realized；Instruction Decode laggard row address to calculate, i.e. EX1, complete functional realiey；Then complete to read to perform 3 bats, write and perform 2 bats L1DCache memory access streamline, wherein read operation streamline is in EX2, EX3, EX4 position in SMAC memory access main pipeline, point It not that hit disappearance judges, memory access/disappearance processes, memory access output；Write operation streamline is then in EX2, EX3 position, is respectively Disappearance judges, memory access/disappearance processes.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 1 and 2, it is characterised in that in institute State and final stage Cache uses on sheet pipeline organization, in order to realize read flag and mode bit, reading directory entry, to judge hit, monitoring Process, data volume accesses and data return the fluvial processes operated.

Multinuclear catalogue concordance device towards GPDSP framework the most according to claim 8, it is characterised in that described The pipeline organization of upper final stage Cache includes:

Streamline first order Req_Arb: carry out round-robin arbitration with Flush request, and request arbitration gone out is sent to next stage stream Water；Meanwhile, the significance bit of read requests data block, dirty position and Tag information are gone back；

Streamline second level Tag_Wait: determine whether catalog request, and read directory information；

Streamline third level Tag_Judge: first determine whether to ask whether to hit, if disappearance, then judge whether and address in MBUF Relevant；If relevant miss request, then request is sent to MBUF；If incoherent miss request, then request is sent to MBUF and OBUF；Hit requests, according to whether be catalog request, processes accordingly；If non-catalog request, then produce visit Ask that data volume enables；If catalog request, then check directory entry information, according to directory states and the different requests of shared list Process the most different；The processing mode of catalog request is divided three classes: the first kind directly operates, and produces access data volume Enable；Equations of The Second Kind waits that L1D data return, and pending data produces after arriving at again and accesses data volume enable；3rd class waits Inv-Ack Request, response to be invalidated produces after all arriving at again and accesses data volume enable；

Streamline fourth stage Data_Acc: first determine whether the classification of request processing data body；If read operation, then request is accessed Data block from data volume read after latch one bat；If write operation, the most first write data are encoded, then be updated number Make according to gymnastics；The data of reading finally can be sent to next stage flowing water by the request carrying out data volume read operation；

Streamline level V Data_Dec: the request data reading upper level carries out decoded operation, and please by reading return data Ask and be sent to ring arbitration process module and process.