CN106201326A - Information processor - Google Patents

Abstract

According to an embodiment, an information processing device (17) includes a transmitting unit (18) and a receiving unit (19). The transmitting unit (18) transmits write data and a logical address of the write data to a memory device (5). The memory device (5) includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The receiving unit (19) receives area information including data identification information indicating data written to an erasure unit area to be subjected to garbage collection from the memory device (5).

Description

information processing device

Cross References to Related Applications

This application is based on, and claims the benefit of priority from, the following applications: U.S. Provisional Application No. 62/097,538, filed December 29, 2014; 2015- 038999; and U.S. Nonprovisional Application No. 14/656,524, filed March 12, 2015, all of which are incorporated herein by reference in their entirety.

technical field

Embodiments described herein generally relate to an information processing device.

Background technique

Solid state drives (SSDs) include non-volatile semiconductor memory such as NAND flash memory. The NAND flash memory includes a plurality of blocks (physical blocks). The plurality of blocks includes a plurality of memory cells arranged at intersections of word lines and bit lines.

Contents of the invention

In general, according to an embodiment, an information processing device includes a transmitting unit and a receiving unit. The transmit unit transmits write data and a logical address of the write data to a memory device. The memory device includes a plurality of unit areas of erase. Each of the erase unit areas includes a plurality of write unit areas. The receiving unit receives area information including data identification information indicating data written to an erase unit area to be subjected to garbage collection from the memory device.

Description of drawings

FIG. 1 is a block diagram showing a configuration example of an information processing system according to a first embodiment;

FIG. 2 is a flowchart showing an example of a process performed by the information processing system according to the first embodiment;

3 is a block diagram showing a configuration example of an information processing system according to a second embodiment;

4 is a flowchart showing an example of the first cache control of the second embodiment;

FIG. 5 is a flowchart showing an example of the second cache control of the second embodiment;

6 is a flowchart showing an example of the third cache control of the second embodiment;

7 is a flowchart showing an example of the fourth cache control of the second embodiment;

8 is a block diagram showing an example of a detailed configuration of an information processing system according to a third embodiment; and

Fig. 9 is a perspective view showing an example of a storage system according to a third embodiment.

detailed description

Embodiments will be described below with reference to the drawings. In the following description, the same reference numerals denote components having almost the same function and arrangement, and a repeated description will be given to the components when necessary.

In each of the embodiments mentioned later, in the nonvolatile memory and the nonvolatile cache memory, data is commonly erased per erase unit area. The erase unit area includes a plurality of write unit areas and a plurality of read unit areas.

In this embodiment, a NAND flash memory is used as each of the nonvolatile memory and the nonvolatile cache memory. However, each of the nonvolatile memory and the nonvolatile cache memory may be a memory other than a NAND flash memory, provided that the memory satisfies the erase unit area, The above-described relationship among the write unit area and the read unit area.

When the nonvolatile memory and the nonvolatile cache memory are NAND flash memories, the erase unit area corresponds to one block. The writing unit area and the reading unit area correspond to one page.

In this embodiment, for example, the erase unit area can be controlled in another unit such as two blocks, which allows data to be erased collectively.

In this embodiment, the access indicates both writing data to and reading data from the memory device.

[first embodiment]

In this embodiment, data and information transmission and reception between an information processing device and a memory device are described.

In this embodiment, logical addresses (for example, logical block addressing) are used as identification information of data. However, data can be identified by other information.

FIG. 1 is a block diagram showing a configuration example of an information processing system according to the present embodiment.

The information processing system 35 includes the information processing device 17 and the SSD 5 . SSD 5 is an example of a memory device. The information processing device 17 may be a host device corresponding to the SSD 5 .

The SSD 5 may be included in the information processing device 17, or may be connected to the information processing device 17 so as to transmit and receive data via a network or the like. Instead of SSD 5, another non-volatile memory device such as a hard disk drive (HDD) may be used.

The information processing device 17 includes a cache control unit 9 , a memory 3 storing management information 61 to 64 , and a nonvolatile cache memory 4 . However, all or part of the cache control unit 9 , the management information 61 to 64 , the memory 3 , and the nonvolatile cache memory 4 may be provided outside the information processing device 17 .

The memory 3 stores various types of control data such as management information (lists) 61 to 64 and address conversion information 7 . The memory 3 may be a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or may be a nonvolatile memory. The memory 3 may be included in a non-volatile cache memory 4 . The memory may be included in a non-volatile cache memory 4 .

The management information 61 to 64 are metadata of data written to the later-mentioned block groups BG ₁ to BG ₄ , respectively. For example, the management information 61 to 64 includes information indicating the usage status of the corresponding data by the processor. For example, the management information 61 to 64 includes identification information of the corresponding data, deletion information indicating whether the data is data to be deleted, valid/invalid information indicating whether the data is valid data, and determining whether the criteria for erasing blocks are satisfied. Cache determination information for erasure conditions.

The delete information is information indicating the issuance of a delete command for data. More specifically, the deletion information is information indicating that a deletion command for data has been received from an application program executed by a processor or an operating system (OS), or the like. In this embodiment, for example, the deletion information includes information correlating identification information of each block with a logical address indicating data to be deleted written in each block.

The valid/invalid information is information indicating, for example, that when the same data is written to a plurality of locations, the latest data is valid data and data other than the latest data is invalid data. In other words, valid data is updated data, for example, in the case where updating of data written to the nonvolatile cache memory 4 is performed. For example, in the case of performing an update, invalid data is data that has not been updated. In this embodiment, for example, the valid/invalid information includes information correlating identification information of each block with a logical address indicating valid data or invalid data written to each block.

The cache specifying information is, for example, information including at least one of write information and read information for each data or at least one of write information and read information for each block.

For example, the writing information includes at least one of writing time, writing times, writing frequency and writing order.

For example, the read information includes at least one of read time, read times, read frequency and read order.

For example, the address translation information 7 relates the logical address of the data to the physical address of the non-volatile cache memory 4 corresponding to said logical address (eg physical block addressing). For example, the address conversion information 7 is managed in the form of a table.

The cache control unit 9 performs cache control for the nonvolatile cache memory 4 whose access speed is higher than that of the SSD 5 . For example, the cache control unit 9 manages data and indicates logical addresses and physical addresses of the data by a write-through method or a write-back method.

In the write-through method, data is stored in the non-volatile cache memory 4 and also in the SSD 5 .

In the write-back method, data stored in the nonvolatile cache memory 4 is not stored in the SSD 5 together. The data is first stored in the non-volatile cache memory 4 , and the data pushed from the non-volatile cache memory 4 is then stored in the SSD 5 .

In the first embodiment, the cache control unit 9 includes a transmitting unit 18 , a receiving unit 19 , a writing unit 20 and a transmitting unit 21 . All or part of the cache memory 9 may be implemented by software or may be implemented by hardware.

The transmitting unit 18 transmits write data for the SSD 5 and an address of the write data to the SSD 5 . In this embodiment, for example, the address transmitted from the transmitting unit 18 to the SSD 5 is a logical address.

The receiving unit 19 receives block information including a logical address indicating valid data written to a block to be subjected to garbage collection from the SSD 5 .

In this embodiment, the block information may include information correlating identification information of each block in the SSD 5 with identification information of data written to each block.

The writing unit 20 writes (duplicates) all or a part of the valid data indicated by the logical address contained in the block information to the non-volatile memory 24 based on the block information received from the SSD 5 and the management information 61 to 64 of memory. The other memory may be, for example, a non-volatile cache memory 4 .

For example, in the case of receiving a delete command, the writing unit 20 excludes a logical address indicating data that is data to be deleted (deletion candidate) from a logical address indicating valid data included in the block information. Thus, valid data written to a block to be subject to garbage collection and not data to be deleted can be selected. The writing unit 20 writes selected data to another memory.

The transmission unit 21 generates deletion information including a logical address indicating data to be deleted and transmits the deletion information to the SSD 5 . For example, the deletion information may include a logical address indicating data that is a deletion target that is not written to another memory by the writing unit 20 among logical addresses indicating valid data included in the block information. Instead of deleting information, maintaining information including logical addresses of data to be maintained may be transmitted from transmitting unit 21 to SSD 5 .

The SSD 5 includes a processor 22 , a memory 23 and a non-volatile memory 24 .

For example, the memory 23 stores various types of control data, such as address translation information 32 , valid/invalid information 33 and deletion information 34 . The memory 23 may be a volatile memory such as DRAM or SRAM, or may be a nonvolatile memory. Memory 23 may be included in non-volatile memory 24 .

The processor 22 functions as an address conversion unit 25, a write unit 26, a valid/ The invalid generation unit 27 , the selection unit 28 , the transmitting unit 29 , the receiving unit 30 and the garbage collection unit 31 .

In this embodiment, for example, to cause the processor 22 to act as an address conversion unit 25, a writing unit 26, a valid/invalid generating unit 27, a selecting unit 28, a transmitting unit 29, a receiving unit 30 and a garbage collection unit The program at 31 may be OS, middleware or firmware. In this embodiment, all or a part of the address conversion unit 25, the writing unit 26, the valid/invalid generating unit 27, the selecting unit 28, the transmitting unit 29, the receiving unit 30 and the garbage collecting unit 31 can be implemented by hardware.

When receiving the write data and the logical address of the write data from the cache control unit 9, the address conversion unit 25 generates the logical address of the write data and the storage instruction in the nonvolatile memory 24. The information related to the physical address of the location of the data is stored in the address translation information 32 .

In this embodiment, the address translation unit 25 is implemented by the processor 22 . However, the address conversion unit 25 may be configured separately from the processor 22 .

The address conversion unit 25 converts addresses based on, for example, tabular address conversion information 32 . Alternatively, addresses may be translated by key-value retrieval. For example, address translation may be implemented by means of key-value retrieval by using a logical address as a key and a physical address as a value.

The writing unit 26 writes write data to the location indicated by the physical address obtained by the address conversion unit 25 .

Valid/invalid generating unit 27 generates valid/invalid information 33 indicating whether each item of data written to nonvolatile memory 24 is valid data or invalid data based on, for example, address conversion information 32 . Subsequently, the valid/invalid generating unit 27 stores the valid/invalid information 33 in the memory 23 .

Selection unit 28 selects blocks to be subjected to garbage collection.

For example, selection unit 28 may select, from the blocks in non-volatile memory 24, the block with the oldest write time as the block to be subjected to garbage collection.

For example, selection unit 28 may randomly select blocks from blocks in non-volatile memory 24 to be subject to garbage collection.

For example, selection unit 28 may select, based on valid/invalid information 33, a block having a maximum amount of invalid data or having an amount of invalid data greater than a predetermined amount as a block to be subjected to garbage collection.

For example, the selection unit 28 may select, based on the valid/invalid information 33 and the deletion information 34, a block having the largest amount of invalid data and data to be deleted or having more than a predetermined amount of invalid data and the amount of data to be deleted as a block to be subjected to garbage collection of blocks.

The transmission unit 29 generates block information by deleting a logical address indicating invalid data determined to be invalid by the valid/invalid information 33 from a logical address indicating data written to a block to be subjected to garbage collection. In other words, the block information includes information correlating identification information of a block to be subjected to garbage collection with a logical address indicating valid data written to the block. The transmission unit 29 transmits the block information to the cache memory control unit 9 .

The receiving unit 30 receives deletion information from the cache control unit 9 and stores the deletion information 34 in the nonvolatile memory 24 .

The garbage collection unit 31 excludes invalid data and data to be deleted from data written to blocks to be subjected to garbage collection based on valid/invalid information 33 and deletion information 34 stored in the nonvolatile memory 24, and only Garbage collection is performed for valid data that is not data to be deleted.

FIG. 2 is a flowchart showing an example of a procedure executed by the information processing system according to the present embodiment.

In step S201 , the transmitting unit 18 transmits the write data and the logical address to the SSD 5 .

In step S202 , the address conversion unit 25 receives the write data and the logical address, and registers information relating the logical address of the write data to the physical address in the address conversion information 32 .

In step S203 , the writing unit 26 writes the write data into the location indicated by the physical address in the nonvolatile memory 24 .

In step S204, the valid/invalid generating unit 27 generates valid/invalid information 33 indicating whether each data item written to the nonvolatile memory 24 is valid data or invalid data and stores the valid/invalid information 33 in the memory 23 middle.

In step S205, the selection unit 28 selects a block to be subjected to garbage collection.

In step S206, the transmitting unit 29 generates block information by deleting a logical address indicating invalid data indicated by the valid/invalid information 33 as invalid from a logical address indicating data written to a block to be subjected to garbage collection, and The block information is transmitted to the cache control unit 9 .

In step S207 , the receiving unit 19 receives block information from the SSD 5 .

In step S208, the writing unit 20 writes all or a part of the data indicated by the logical address contained in the block information to the nonvolatile memory of the SSD 5 based on the block information received from the SSD 5 and the management information 61 to 64. Memory other than permanent memory 24.

For example, when a delete command is received, the writing unit 20 excludes a logical address indicating data to be deleted from the logical addresses contained in the block information, and writes the data to be maintained indicated by the logical address into Another memory.

In step S209, the transmitting unit 21 transmits deletion information including the logical address of the data to be deleted to the SSD5.

In step S210 , the receiving unit 30 receives deletion information from the cache control unit 9 and stores the deletion information 34 in the memory 23 .

In step S211, the garbage collection unit 31 excludes invalid data and data to be deleted from the data written to the block to be subjected to garbage collection based on the valid/invalid information 33 and the deletion information 34, and for data not to be deleted Garbage collection is performed on valid data.

In the present embodiment described above, the cache control unit 9 can acquire information on data written to a block of the nonvolatile memory 24 from the SSD 5 . The cache control unit 9 can thereby identify the write status of data in the block of the non-volatile memory 24 . For example, in this embodiment, it can be identified whether the data written to the block of the nonvolatile memory 24 is valid data or invalid data and whether the data can be deleted.

In this embodiment, the SSD 5 includes valid/invalid information 33 for determining whether the data is valid or invalid, and deletion information 34 for determining whether the data can be deleted. By this, whether or not to erase data written to a block to be subjected to garbage collection can be determined when garbage collection is performed in the SSD 5 . Therefore, unnecessary data writing can be avoided and the lifetime of the nonvolatile memory 24 can be increased.

In the present embodiment, the cache control unit 9 can prevent deletion target data among valid data indicated by a logical address contained in the block information received from the SSD 5 from being transcribed from the nonvolatile memory 24 to another memory. In this embodiment, the SSD 5 can delete from the SSD 5 data that is not transcribed from the cache control unit 9 to another memory (for example, invalid data or valid data that can be deleted).

In the present embodiment described above, the block information related to the block to be erased is transmitted from the SSD 5 to the information processing device 17 . However, the block information may include information that correlates each block in the nonvolatile memory 24 with identification information of data written to each block, for example. The information processing device 17 can recognize the storage relationship between blocks and data in the SSD 5 by receiving the relationship information from the SSD 5 .

[Second embodiment]

A cache memory device including the nonvolatile cache memory 4 is described in this embodiment.

FIG. 3 is a block diagram showing a configuration example of the information processing device 35 according to the present embodiment.

The information processing device 17 includes a processor 2 , a memory 3 and a nonvolatile cache memory 4 .

The nonvolatile cache memory 4 includes block groups BG ₁ to BG ₄ . The nonvolatile cache memory 4 has an access speed higher than that of the SSD 5 .

The block group (first group) BG ₁ includes blocks (first erase unit regions) B _1,1 to B _1,K . Block group BG1 stores data accessed by processor ₂ (ie, data used by processor 2).

In this embodiment, when the block group BG ₁ satisfies the erasure condition (the first erasure condition), blocks B _1,1 to B _{1 , K} selects a block to be erased (a block to be discarded or pushed out) (the first area to be erased).

For example, when the data amount of each of the blocks B _1,1 to B _1,K of the block group BG ₁ exceeds a predetermined value, the erasure condition is satisfied. For example, an erase condition may be satisfied when the number of pages written to each of blocks B _1,1 to B _1,K of block group BG ₁ exceeds a predetermined number.

When data written to a block to be erased selected from blocks B _1,1 to B _1,K on a FIFO basis is in a first low usage state (for example, when the data is accessed for less than the set The data is written into the block group BG ₂ when it is accessed for a predetermined number of times or less than the set first frequency). In contrast, when the data written to the block to be erased selected from blocks B _1,1 to B _1,K is in the first high usage state (for example, when the data is accessed for the first the number of times or more or the first frequency or more), the data is written to the block group BG ₃ . Data written to blocks to be erased selected from blocks B _1,1 to B _1,K are erased (ie discarded or pushed out) on a block-by-block basis.

The block group (second group) BG ₂ includes blocks (second erase unit regions) B _2,1 to B _2,L . The block group BG ₂ stores data in a first low usage state written to data of blocks to be erased selected from the block group BG ₁ .

In this embodiment, when the block group BG ₂ satisfies the erasing condition (the third erasing condition), the blocks B _2,1 to B _2,L in the block group BG ₂ are selected to be erased based on FIFO block (the third area to be erased).

When the data written to the block to be erased selected from the blocks B _2,1 to B _2,L according to the FIFO is in the third low usage state (for example, when the data is accessed for less than the set When accessing for a predetermined third number of times or less than the set third frequency), the data is erased. In contrast, when data written to a block to be erased selected from blocks B _2,1 to B _2,L is in the third highest usage state (for example, when the data is accessed up to the third or more times or is accessed at a third frequency or more), the data is written to the block group BG ₃ . Subsequently, the data written to the blocks to be erased selected from the blocks B _2,1 to B _2,L are erased block by block.

The block group (third group) BG ₃ includes blocks (third erase unit regions) B _3,1 to B _3,M . Block group BG ₃ stores data in a first low usage state written to data of blocks to be erased selected from block group BG ₁ . The block group BG ₃ also stores data in the third highest usage state written to the data of the blocks to be erased selected from the block group BG ₂ .

In this embodiment, when the block group BG3 satisfies the erasing condition (second erasing condition), the blocks _B3,1 to _{B3 ,M in} the block group BG3 are selected to be erased based on FIFO block (the second area to be erased).

When data written to a block to be erased selected from blocks B _3,1 to B _3,M according to the FIFO is in the second least used state (for example, when the data is accessed for less than the set The data is written into the block group BG ₄ when it is accessed for a predetermined second number of times or less than the set second frequency. In contrast, when the data written to the block to be erased selected from blocks B _3,1 to B _3,M is in the second highest usage state (for example, when the data is accessed for the second or more times or at the second frequency or more), the data is written again to another block in the block group _BG3 . Subsequently, the data written to the blocks to be erased selected from the blocks B _3,1 to B _3,M are erased block by block.

Block group (fourth group) BG ₄ includes blocks (fourth erasing unit area) B _4,1 to B _4,N , and block group BG ₄ stores and writes to the data to be erased selected from block group BG ₃ . The data in the second least used state among the data except the block.

In this embodiment, when the block group BG ₄ satisfies the erasing condition (the fourth erasing condition), the blocks B _4,1 to B _4,N in the block group BG ₄ are selected to be erased based on FIFO block (the fourth area to be erased).

Data written to blocks to be erased selected from blocks B _4,1 to B _4,N according to the FIFO are erased.

In the present embodiment, FIFO is used as a method for selecting a block to be erased from each of the block groups BG ₁ to BG ₄ . By selecting blocks to be erased according to the FIFO, erasing is sequentially performed starting from the block with the oldest writing time and writing order in each _of the block groups BG1 to _BG4 . However, blocks to be erased may be selected randomly or based on least recently used (LRU) or least frequently used (LFU), for example. For example, the management information 61 to 64 includes identification information of the data, information indicating whether the data is data to be deleted, and usage status information of the data. A block having the largest amount of invalid data or a block having an amount of invalid data greater than a predetermined amount may be selected as a block to be erased based on the management information 61 to 64 . For example, a block with the largest amount of invalid data and data to be deleted (deletion target data) or a block with an amount of invalid data and data to be deleted larger than a predetermined amount may be selected as a block to be erased based on the management information 61 to 64 .

In the present embodiment, the cache control unit 9 can recognize identification information of the cached data (for example, a logical address (for example, logical block addressing)), the location where the data is written to, and the usage status of the data. For example, cache control unit 9 may select data cached to each of block groups BG ₁ to BG ₄ and blocks erased according to FIFOs based on management information 61 to 64 and address translation information 7 .

The processor 2 functions as the address conversion unit 8 and the cache control unit 9 by executing programs stored in the memory of the processor 2 , the memory 3 , the nonvolatile cache memory 4 , or the SSD 5 .

In this embodiment, for example, the program for causing the processor 2 to function as the address translation unit 8 and the cache control unit 9 may be OS, middleware or firmware. In this embodiment, all or a part of the address translation unit 8 or all or a part of the cache control unit 9 may be implemented by hardware.

The address conversion unit 8 generates information correlating the logical address of the write data with the physical address indicating the location in the nonvolatile cache memory 4 where the write data is stored, and registers the generated information to the address conversion information 7 .

When receiving a logical address of read data from processor 2 , address conversion unit 8 converts the logical address into a physical address based on address conversion information 7 .

Cache control unit 9 includes generation unit 10 , control units 11 to 14 and variation units 15 and 16 .

The generating unit 10 generates management information 61 to 64 corresponding to the block groups BG ₁ to BG ₄ in the nonvolatile cache memory 4 and writes the management information 61 to 64 to the memory 3 .

The control units 11 to ₁₄ control data writing and block erasing for the block groups _BG1 to BG4, respectively.

The control unit 11 includes a writing unit 111 , a determining unit 112 , a selecting unit 113 , a determining unit 114 and an erasing unit 115 .

The writing unit (first writing unit) 111 writes data accessed by the processor 2 to the block group BG ₁ .

The determination unit (first determination unit) 112 determines whether the block group BG1 satisfies _an erasure condition (first erasure condition).

When the block group BG1 satisfies the erasing condition, the selection unit ( _first selection unit) 113 selects a block to be erased ( _first area to be erased) from the block group BG1.

Determining unit (second determining unit) 114 determines whether each data item written into the block to be erased is in the first high usage state or the first low usage state and whether each item of the data is based on the management information 61 Data to be deleted.

When each data item written to the block to be erased can be discarded because each data item is written into block groups BG ₂ to BG ₃ or data to be deleted, the erasing unit (the first erasing unit ) 115 erases the block to be erased.

The control unit 12 includes a writing unit 121 , a determining unit 122 , a selecting unit 123 , a determining unit 124 and an erasing unit 125 .

When the determining unit 114 determines that the data written to the block to be erased in the block group BG ₁ is in the first low usage state and is not data to be deleted, the writing unit (second writing unit) 121 writes the data into to block group BG ₂ .

The determination unit (fifth determination unit) 122 determines whether the block group _BG2 satisfies an erasure condition (third erasure condition).

When the block group _BG2 satisfies the erasing condition, the selection unit (third selection unit) 123 selects a block to be erased (third region to be erased ₎ from the block group BG2.

The determining unit 124 determines whether each data item written into the block to be erased is in the third highest usage state or the third lowest usage state and whether each item of data is data to be deleted based on the management information 62 .

When the data written to the block to be erased that is not the data to be erased is written into the block group BG ₃ in the third high usage state, the erase unit (second erase unit) 125 erases the data written to the block to be erased. Erases the data of a block.

The control unit 13 includes a writing unit 131 , a determining unit 132 , a selecting unit 133 , a determining unit 134 , a writing unit 135 , an erasing unit 136 and a writing unit 137 .

When the determination unit 114 determines that the data written to the block to be erased in the block group BG ₁ is in the first high usage state and is not data to be deleted, the writing unit (third writing unit) 131 writes the data into to block group BG ₃ .

When the data written into the block group BG ₂ is in the third highest usage state and is not data to be deleted, the writing unit (sixth writing unit) 137 writes the data into the block group BG ₃ . For example, when the data written into the block group BG2 is data to be accessed by the processor ₂ , the writing unit 137 may write the data to be accessed of the block group _BG2 into the block group BG ₃ .

The determination unit ( _third determination unit) 132 determines whether the block group BG3 satisfies an erasure condition (second erasure condition).

When the block group _BG3 satisfies the erasure condition, the selection unit (second selection unit) 133 selects a block to be erased (second area to be erased ₎ from the block group BG3.

Determining unit (the 4th determining unit) 134 is based on the management information 63 and determines whether each data item written into the block to be erased is in the second high usage state or the second low usage state and whether each item of the data is Data to be deleted.

When the data written to the block to be erased in the block group BG ₃ is determined to be in the second highest usage state and not to be deleted, the writing unit (fifth writing unit) 135 writes the data again to another writable block in block group BG ₃ .

When each item of data written to the block to be erased can be discarded due to each data item being written to the block group _BG4 , written again to the block group _BG3 , or data to be deleted, The erasing unit (third erasing unit) 136 erases a block to be erased.

The control unit 14 includes a writing unit 141 , a determining unit 142 , a selecting unit 143 and an erasing unit 144 .

When the determining unit 134 determines that the data written to the block to be erased in the block group BG ₃ is in the second low usage state and is not data to be deleted, the writing unit (fourth writing unit) 141 writes the data into to block group BG ₄ .

The determination unit (sixth determination unit) 142 determines whether the block group BG4 satisfies an erasure condition ( _fourth erasure condition).

When block group BG4 satisfies the erase condition ( _fourth erase condition), the selection unit ( _fourth selection unit) 143 selects a block to be erased (fourth area to be erased) from block group BG4.

The erasing unit ( _fourth erasing unit) 144 erases the data written to the block to be erased of the block group BG4.

When the data written into block group BG ₂ reaches the third highest usage state, change unit (first change unit) 15 increases the number of blocks contained in block group BG ₁ and decreases the number of blocks contained in block group BG ₃ The number of blocks to contain. For example, when data written to block group BG ₂ is accessed by processor 2, change unit 15 increases the number of blocks contained in block group BG ₁ and decreases the number of blocks contained in block group BG ₃ number of blocks.

When the data written to block group BG ₄ reaches the fourth highest usage state, change unit (second change unit) 16 increases the number of blocks contained in block group BG ₃ and decreases the number of blocks contained in block group BG ₁ The number of blocks to contain. For example, when data written to block group BG ₄ is accessed by processor 2, variation unit 16 increases the number of blocks contained in block group BG ₃ and decreases the number of blocks contained in block group BG ₁ number of blocks.

FIG. 4 is a flowchart showing an example of the first cache control according to the present embodiment. FIG. 4 exemplarily shows _a process in which data is written to block group BG1, data is written to block group _BG2 or _BG3 , and _a block to be erased in block group BG1 is erased.

In step S401 , the writing unit 111 writes data accessed by the processor 2 into the block group BG ₁ .

In step 402, the determination unit 112 determines whether the block group BG1 satisfies _an erasure condition.

When the block group _BG1 does not satisfy the erasure condition, the process proceeds to step S406.

When the block group BG ₁ satisfies the erasing condition, in step S403 , the selection unit 113 selects a block to be erased from the block group BG ₁ .

In step S404, the determination unit 114 determines based on the management information 61 whether each data item written to the block to be erased is in the first high usage state or the first low usage state and whether each item of the data is a pending block. Wipe data (delete target data).

When the data item is in the first low usage state and the data is not data to be deleted (non-deletion target data), in step S501 , the writing unit 121 writes the data item into the block group BG ₂ .

When the data item is in the first high usage state and is not data to be deleted, in step S601 , the writing unit 131 writes the data item into the block group BG ₃ .

When each item of data written into the block to be erased may be discarded due to each item of data being written into the block group _BG2 or block group BG3 or the data to be deleted, in step S405, The erasing unit 115 erases a block to be erased.

In step S406, the cache control unit 9 determines whether the process is to be ended.

When the cache control unit 9 does not end the process, the process returns to step S401.

When the cache control unit 9 ends the process, the process ends.

FIG. 5 is a flowchart showing an example of the second cache control according to the present embodiment. FIG. 5 exemplarily shows a process in which data is written to the block group _BG2 and blocks to be erased in the block group _BG2 are erased.

When in step S404, the data written to the block to be erased in block group BG ₁ is determined to be in the first low usage state and not to be deleted, in step S501, the writing unit 121 writes the data Write to block group BG ₂ .

In step S502, the determination unit 122 determines whether the block group _BG2 satisfies the erasure condition.

When the block group BG ₂ does not satisfy the erasure condition, the process proceeds to step S506.

When the block group BG ₂ satisfies the erasing condition, in step S503 , the selection unit 123 selects a block to be erased from the block group BG ₂ .

In step S504, the determination unit 124 determines based on the management information 62 whether each data item written to the block to be erased is in the third high usage state or the third low usage state and whether each item of the data is a pending block. delete data.

When the data item is in the third lowest usage state or is data to be deleted, the process proceeds to step S505.

When the data item is in the third highest usage state and is not data to be deleted, in step S601 , the writing unit 137 writes the data item into the block group BG ₃ .

In step S505, the erasing unit 125 erases the data written to the block to be erased in the block group _BG2 .

In step S506, the cache control unit 9 determines whether the process is to be ended.

When the cache control unit 9 does not end the process, the process returns to step S501.

When the cache control unit 9 ends the process, the process ends.

FIG. 6 is a flowchart showing an example of the third cache control according to the present embodiment. FIG. ₆ exemplarily shows the process from writing data into the block group _BG3 to erasing the data in the block group BG3.

When in step S404, the data written to the block to be erased in block group BG ₁ is determined to be in the first high usage state and not to be deleted, in step S601, the writing unit 131 writes the data Write to block group BG ₃ . When in step S304, the data written into the block group BG2 is determined to be in the third highest usage state (for example, the data is accessed by the processor ₂ ) and not to be deleted, the write unit 137 writes the data of the block group BG ₂ into the block group BG ₃ .

In step S602, the determination unit 132 determines whether the block group _BG3 satisfies the erasure condition.

When the block group BG ₃ does not satisfy the erasure condition, the process proceeds to step S607.

When the block group BG ₃ satisfies the erasing condition, in step S603 , the selection unit 133 selects a block to be erased from the block group BG ₃ .

In step S604, the determining unit 134 determines based on the management information 63 whether each data item written to the block to be erased is in the second high usage state or the second low usage state and whether each item of the data is a pending block. delete data.

When the data item is in the second lowest usage state and is not data to be deleted, in step S701 , the writing unit 141 writes the data into the block group BG ₄ .

When the data is in the second highest usage state and is not data to be deleted, in step S605, the writing unit 135 writes the data of the block to be erased written into the block group BG ₃ into the block group BG ₃ again another piece of .

In step S606, when each item of data written into the block to be erased can be written into block group BG ₄ , rewritten into block group BG ₃ or data to be deleted When discarded, the erasing unit 136 erases the block to be erased.

In step S607, the cache control unit 9 determines whether the process is to be ended.

When the cache control unit 9 does not end the process, the process returns to step S601.

When the cache control unit 9 ends the process, the process ends.

FIG. 7 is a flowchart showing an example of fourth cache control according to the present embodiment. FIG. ₇ exemplarily shows a process in which data is written to block group _BG4 and data in block group BG4 is erased.

When in step S604, the data written to the block to be erased in block group BG ₃ is determined to be in the second low state and not to be deleted, in step S701, the writing unit 141 writes the data to into block group BG ₄ .

In step S702, the determination unit 142 determines whether the block group _BG4 satisfies the erasure condition.

When the block group BG ₄ does not satisfy the erasure condition, the process proceeds to step S705.

When the block group BG ₄ satisfies the erasing condition, in step S703 , the selection unit 143 selects a block to be erased from the block group BG ₄ .

In step S704, the erasing unit 144 erases the data written in the block to be erased in the block group _BG4 .

In step S705, the cache control unit 9 determines whether the process is to be ended.

When the cache control unit 9 does not end the process, the process returns to step S701.

When the cache control unit 9 ends the process, the process ends.

In the block group BG ₁ of the present embodiment, for example, data is first written to block B _1,1 , next sequentially written to block B _1,2 , and then similarly written to block B _{1 ,3} to B _1,K . When the data volume of the blocks B _1,1 to B _1,K contained in the block group BG ₁ exceeds the predetermined data volume, among them, the block B _1,1 which is completed first is erased and written according to the FIFO, and the data is written again Sequential writes to erased block B _1,1 . After writing to block B _1,1 is complete, block B _1,2 is erased according to the FIFO. Subsequently, data is sequentially written to erased block B _1,2 again. Repeat the same control.

_In the block group BG1, it is determined based on the management information 61 whether the data of the block to be erased written in the block group BG1 is, for example, accessed less than the _first number or at a rate less than the first frequency is accessed. When the data written into the block to be erased in the block group BG ₁ is accessed for less than the first number of times or is accessed less than the first frequency, select the block group BG ₂ as the writing destination of the data land.

In contrast, when the data of the block to be erased written in the block group BG ₁ is accessed for the first number of times or more or is accessed at the first frequency or more, the block group is selected BG ₃ serves as the write destination of data.

When the data written in the block to be erased in the block group _BG1 is data to be deleted, the data is discarded.

In block group BG ₂ of this embodiment, data from block group BG ₁ in the first low usage state is first sequentially written to block B _2,1 , followed by sequential writing to block B _2,2 , and then similarly write to blocks B _2,3 to B _2,L . When the data volume of the blocks B _2,1 to B _2,L included in the block group BG ₂ exceeds a predetermined data volume, the block B _2,1 in which writing is completed first is erased according to the FIFO and the data is sequentially again Write to erased block B _2,1 . After writing to block B _2,1 is complete, block B _2,2 is erased according to the FIFO. Subsequently, data is sequentially written to erased block B _2,2 . Repeat the same control.

In the block group BG2, it is determined based _on the management information 62 whether the data written to the block to be erased in the block group BG2 is, for example, accessed less _than the third number of times or less than the third frequency. access. When the data written in the block to be erased in the block group BG2 is accessed less _than a third number of times or accessed less than a third frequency, the data is erased.

In contrast, when the data of the block to be erased written in the block group BG ₂ is accessed a third number of times or more or is accessed at a third frequency or more, the block group BG is selected ₃ as the write destination of the data.

When the data written in the block to be erased in the block group _BG2 is data to be deleted, the data is discarded.

In the block group BG ₃ of this embodiment, the data in the first high usage state from the block group BG ₁ , the data in the third high usage state from the block group BG ₂ or the data in the third high usage state from the block group BG ₃ The rewritten data of is first sequentially written to block B _3,1 , next sequentially written to block B _3,2 , and then similarly written to blocks B _3,3 to B _3,M . When the data volume of the blocks B _3,1 to B _3,M contained in the block group BG ₃ exceeds a predetermined data volume, the block B _3,1 in which writing is completed first is erased according to the FIFO and the data is sequentially again Write to erased block B _3,1 . After writing to block B _3,1 is complete, block B _3,2 is erased according to the FIFO. Subsequently, data is sequentially written to erased block B _3,2 again. Repeat the same control.

_In the block group BG3, it is determined based on the management information 63 whether the data written to the block to be erased in the block group _BG3 is, for example, accessed less than the second number of times or less than the second frequency. access. When the data written into the block to be erased in the block group BG3 is accessed less _than the second number of times or is accessed less than the second frequency, the block group _BG4 is selected as the write destination of the data .

In contrast, when the data written to the block to be erased in the block group BG ₃ is accessed the second number of times or more or is accessed at the second frequency or more, the data is written again to block group BG ₃ .

When the data written in the block to be erased in the block group _BG3 is data to be deleted, the data is discarded.

In block group BG ₄ of the present embodiment, data from block group BG ₃ in the second lowest usage state is first sequentially written to block B _4,1 , followed by sequential writing to block B _4,2 , and then similarly write to blocks B _4,3 to B _4,N . When the data volume of the blocks B _4,1 to B _4,N contained in the block group BG ₄ exceeds a predetermined data volume, the block B _4,1 in which writing is completed first is erased according to the FIFO and the data is sequentially again Write to erased block B _4,1 . After writing to block B _4,1 is complete, block B _4,2 is erased according to the FIFO. Subsequently, data is sequentially written to erased block B _4,2 . Repeat the same control.

In this embodiment, the control unit 14 can determine whether the data written to the block to be erased in the block group BG ₄ is in the fifth highest usage state. When the data written to the block to be erased of the block group BG ₄ is determined to be in the fifth most used state, in terms of maintaining the data in the nonvolatile cache memory 4, the control unit 13 may The data is written to a writable destination block _of the block group BG3. In this case, processor ₂ may reduce the size of block group BG1.

In the present embodiment, data is managed based on four block groups BG ₁ to BG ₄ .

For example, first data accessed once by the processor ₂ (data accessed once) is managed in the block group BG1.

For example, if the second data in block group BG ₁ is accessed by processor 2 two or more times and pushed out from block group BG ₁ based on FIFO, then the second data in block group BG _1Move to block group BG ₃ .

It should be noted that in this embodiment, the size of the block group BG ₁ is larger than the size of the block group BG ₃ .

For example, when the third data in the block group BG ₁ is pushed out from the block group BG ₁ based on the FIFO without being accessed by the processor 2, the third data is moved from the block group BG ₁ to block group BG ₂ .

For example, if the fourth data in block group BG ₃ is cleared from block group BG ₃ based on FIFO without being accessed by processor 2, then the fourth data is moved from block group BG ₃ to block group BG ₄ .

For example, in block groups BG ₂ and BG ₄ , metadata may be cached rather than data. Metadata contains information related to data. In other words, metadata is highly abstract and additional data about data and is attached to the data.

In this embodiment, for example, when the fifth data is stored in the block group _BG1 , the sixth data in the block group BG2 can be deduced based _on FIFO.

For example, when the seventh data in block group BG ₁ is accessed and pushed out from block group BG ₁ based on FIFO, the seventh data can be moved from block group BG ₁ to block group BG ₃ , the eighth data in block group BG ₃ can be moved from block group BG ₃ to block group BG ₄ based on FIFO, and the eighth data in block group BG ₄ can be deduced from block group BG ₄ based on FIFO Nine data.

For example, when accessing the tenth data in the block group _BG2 , the size _of the block group BG1 will be increased. If the size _of the block group BG1 increases, the eleventh data in the block group BG3 is moved to the block group _BG4 based _on FIFO.

For example, when the twelfth data in block group BG ₄ is accessed and pushed out from block group BG ₄ based on FIFO, the twelfth data is moved to block group BG ₃ and will decrease Size _of block group BG1.

In the present embodiment described above, the maintenance determination is performed to determine whether to maintain data in block units, the transfer write writes the block data to be maintained to the destination block, and writes to the nonvolatile cache Data in the memory 4 is erased block by block.

In this embodiment, the effective cache capacity can be increased, the bit rate of the nonvolatile cache memory 4 can be increased, and the speed of the information processing device 17 can be increased.

In this embodiment, without performing garbage collection for the nonvolatile cache memory 4, performance degradation can be avoided. Since garbage collection is not necessary, the number of writes to the non-volatile cache memory 4 can be reduced and the lifetime of the non-volatile cache memory 4 can be increased. Also, since garbage collection is not required, there is no need to guarantee a provisioning area. Therefore, the data capacity usable as a cache memory can be increased, and use efficiency can be improved.

For example, when using nonvolatile memory as a cache memory and discarding data regardless of block boundaries, garbage collection may be frequently performed to move valid data in a block of nonvolatile memory to another block . In this embodiment, there is no need to perform garbage collection in the nonvolatile cache memory 4 . Therefore, as described above, in the present embodiment, the lifetime of the nonvolatile cache memory 4 can be increased.

[Third embodiment]

In this embodiment, the information processing system 35 including the information processing system 17 and the SSD 5 explained in the first and second embodiments is explained in further detail.

FIG. 8 is a block diagram showing an example of the detailed structure of the information processing system 35 according to the present embodiment.

The information processing system 35 includes an information processing device 17 and a memory system 37 .

The SSD 5 according to the first and second embodiments corresponds to the memory system 37 .

The processor 22 of the SSD 5 corresponds to the CPU 43B.

The address translation information 32 corresponds to a LUT (Look Up Table) 45 .

The memory 23 corresponds to the DRAM 47 .

The information processing device 17 functions as a host device.

The controller 36 of the memory system 37 includes a front end 4F and a back end 4B.

The front end (host communication unit) 4F includes a host interface 41, a host interface controller 42, an encoding/decoding unit (Advanced Encryption Standard (AES)) 44, and a CPU 43F.

The host interface 41 communicates with the information processing device 17 to exchange requests (write command, read command, erase command), LBA, and data.

A host interface controller (control unit) 42 controls communication of the host interface 41 based on the control of the CPU 43F.

The encoding/decoding unit 44 encodes write data (plaintext) transmitted from the host interface controller 42 in a data writing operation. The encoding/decoding unit 44 decodes the encoded read data transmitted from the read buffer RB of the back end 4B in a data read operation. It should be noted that the transmission of write data and read data may be performed without using the encoding/decoding unit 44 in accordance with temporary commands.

The CPU 43F controls the above components 41, 42, and 44 of the front end 4F to control the entire functions of the front end 4F.

The backend (memory communication unit) 4B includes a write buffer WB, read buffer RB, LUT 45, DDRC 46, DRAM 47, DMAC 48, ECC 49, random function generator RZ, NANDC 50, and CPU 43B.

The write buffer (write data transfer unit) WB temporarily stores write data transmitted from the information processing device 17 . Specifically, the write buffer WB temporarily stores the data until it reaches a predetermined data size suitable for the nonvolatile memory 24 .

The read buffer (read data transfer unit) RB temporarily stores read data read from the nonvolatile memory 24 . Specifically, the read buffer RB rearranges read data into an order suitable for the information processing device 17 (order of logical addresses LBA specified by the information processing device 17 ).

The LUT 45 is data to convert a logical address LBA into a physical address PBA (Physical Block Addressing).

DDRC 46 controls double data rate (DDR) in DRAM 47 .

The DRAM 47 is a nonvolatile memory that stores, for example, the LUT 45 .

A direct memory access controller (DMAC) 48 transfers write data and read data via an internal bus IB. In FIG. 8 , only a single DMAC 48 is shown; however, the controller 36 may include two or more DMACs 48 . DMAC 48 may be located in various locations within controller 36 .

An ECC (Error Correction Unit) 49 adds an error correction code (ECC) to the write data transmitted from the write buffer WB. When the read data is transmitted to the read buffer RB, the ECC 49 corrects the read data read from the nonvolatile memory 24 using the added ECC, if necessary.

In a data write operation, the randomizer RZ (or scrambler) spreads the write data in such a way that the write data is not biased into a certain page or is not biased into a non-volatile In the word line direction of the non-volatile memory 24. By spreading the write data in this way, the number of times of writing can be normalized and the cell life of the memory cells MC of the nonvolatile memory 24 can be extended. Therefore, the reliability of the nonvolatile memory 24 can be improved. In addition, in the data read operation, the read data read from the non-volatile memory 24 passes through the random function generator RZ.

A NAND controller (NANDC) 50 uses multiple channels (four channels CH0 to CH3 are shown in the figure) to access the non-volatile memory 24 in parallel to meet the demand for a certain speed.

The CPU 43B controls each of the above components (45 to 50 and RZ) of the backend 4B to control the entire function of the backend 4B.

It should be noted that the configuration of controller 36 is merely an example and is not intended to be limiting thereby.

FIG. 9 is a perspective view showing an example of a storage system according to the present embodiment.

Storage system 100 includes memory system 37 as an SSD.

For example, memory system 37 is a relatively small module whose external dimensions will be approximately 20mm x 30mm. It should be noted that the size and dimensions of the memory system 37 are not limited thereto and can be arbitrarily changed into various sizes.

Furthermore, the memory system 37 is applicable to the information processing device 17 as a server used in a data center or cloud computing system employed in a company (enterprise) or the like. Thus, memory system 37 may be an enterprise SSD (eSSD).

For example, memory system 37 includes a plurality of connectors (eg, sockets) 38 that open upwardly. Each connector 38 is a Serial Attached SCSI (SAS) connector or the like. By means of the SAS connector, high-speed mutual communication can be established between the information processing device 17 and each memory system 37 via a dual port of 6Gbps. It should be noted that connector 38 may be PCI Express (PCIe) or NVM Express (NVMe).

A plurality of memory systems 37 are individually attached to connectors 38 of the information processing device 17 and are supported in an arrangement such that they stand in a substantially vertical direction. With this structure, a plurality of memory systems 37 can be commonly mounted in a compact size, and the memory system 37 can be miniaturized. Furthermore, each memory system 37 of the present embodiment is shaped as a 2.5-inch small form factor (SFF). Because of this shape, memory system 37 is compatible with enterprise HDDs (eHDDs) and simple system compatibility with eHDDs can be achieved.

It should be noted that memory system 37 is not limited to use in enterprise HDDs. For example, the memory system 37 can be used as a memory medium for consumer electronic devices such as notebook or tablet terminals.

As can be understood from the above, the information processing system 35 and the storage system 100 having the structure of the present embodiment can realize the advantages of large-capacity storage with the same advantages of the second embodiment.

The structure of the memory system 37 according to the present embodiment is applicable to the information processing device 17 according to the first embodiment. For example, the processor 2 according to the first embodiment may correspond to the CPU 43B. The address conversion information 7 may correspond to the LUT 45 . The memory 3 corresponds to the DRAM 47 . The nonvolatile cache memory 4 may correspond to the nonvolatile memory 24 .

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions and substitutions in the form of the embodiments described herein may be made without departing from the spirit of the invention. Change. It is intended that the appended claims and their equivalents cover such forms or modifications as would fall within the scope and spirit of the invention.

Claims (9)

1. An information processing device, characterized in that it comprises: a transmitting unit that transmits write data and a logical address of the write data to a memory device including a nonvolatile memory including a plurality of erase unit areas, the erase unit areas each of which includes a plurality of write unit areas; and a receiving unit that receives, from the memory device, area information including data identification information indicating data written to a unit-of-erase area to be subjected to garbage collection. 2. The information processing device according to claim 1, characterized in that The area information includes the data identification information indicating valid data written to the erase unit area to be subjected to garbage collection. 3. The information processing device according to claim 1, characterized in that The data identification information is a logical address. 4. The information processing device according to claim 1, further comprising: a deletion transmitting unit that transmits deletion information including data identification information indicating data to be deleted among the data written in the memory device to the memory device. 5. The information processing device according to claim 1, further comprising: a writing unit that writes at least a part of the data indicated by the data identification information included in the area information to a memory device other than the memory device. 6. The information processing device according to claim 5, characterized in that The writing unit writes valid data that is not data to be deleted among the data indicated by the data identification information included in the area information to the another memory device. 7. The information processing device according to claim 5, further comprising: A deletion transmitting unit that transmits to the memory device deletion information including data identification information indicating data that has not been written to the another memory device among the data written to the memory device. 8. The information processing device according to claim 5, characterized in that The writing unit does not write the data to be deleted among the data indicated by the data identification information included in the area information to the another memory device. 9. The information processing device according to claim 1, characterized in that The non-volatile memory is a NAND flash memory, The erasing unit area is one block, The writing unit area is one page, and The memory device is a solid state drive.