CN106201111B - Touch drive circuit and touch display device - Google Patents

Abstract

The present invention provides a touch drive circuit and a touch display device, wherein a power consumption reduction module is provided, and the power consumption reduction module receives the first input signal from the first input signal end and the second input signal end Under the control of the second input signal, write the first clock signal of the first clock signal terminal or the first power signal of the first power signal terminal into the second node. In this way, the first clock signal at the first clock signal terminal can be prevented from continuously being input to the second node, thereby reducing corresponding power consumption.

Description

Touch driving circuit and touch display device

technical field

The present invention relates to the field of display technology, in particular to a touch driving circuit and a touch display device.

Background technique

With the continuous development of electronic technology, more and more display devices begin to use the human-computer interaction mode to realize the user's operation of the display device. At present, the human-computer interaction mode has entered the touch sensing mode from the mechanical button mode. Taking the touch panel as an example, the touch panel includes multiple scanning electrodes and sensing electrodes. In the touch sensing mode, when the user touches the touch panel, the capacitance between the scanning electrodes and the sensing electrodes at the touch point will change. , the sensing signal in the sensing electrode also changes accordingly, and the position of the touch point can be known by analyzing the sensing signal, so that the user can realize human-computer interaction with the display device through the touch panel installed on the display device. Wherein, the touch panel installed on the display device includes multi-level touch driving units, and each level of touch driving units is used to provide touch signals for the scanning electrodes.

In the process of implementing the present invention, the inventors found that the power consumption of the touch drive unit in the prior art is generally relatively large, which is not conducive to reducing the overall power consumption of the display device.

Contents of the invention

An object of the present invention is to provide a novel touch driving circuit to reduce power consumption.

In the first aspect, the present invention provides a touch driving circuit, including a multi-level scanning driving unit; each level of touch driving unit includes a shift register unit and a scanning driving unit; wherein the shift register unit includes: an input module , power reduction module, shift register module and output module,

The input module is respectively connected to the first input signal terminal, the first node, the first clock signal terminal and the second clock signal terminal, so that the first clock signal terminal is at a first level and the second clock signal terminal When it is at the second level, write the signal of the first input signal terminal into the first node;

The power consumption reducing module is respectively connected to the first input signal terminal, the second input signal terminal, the third clock signal terminal, the first power supply signal terminal and the second node, and is used to connect the first input signal terminal and the second When any signal terminal in the input signal terminal is at the first level, write the third clock signal of the first clock signal terminal into the second node; both the first input signal terminal and the second input signal terminal are the second level, write the first power signal of the first power signal terminal into the second node;

The shift register module is respectively connected to the first node, the second node, the third node, the first control signal terminal and the second power signal terminal, and is used to input the first When the reset valid signal is active, the third node is set as the inversion signal of the power signal at the second power signal terminal; when the first reset invalid signal is input at the first control signal terminal and the second node is at the first level, the first node is set to The signal is written to the third node;

The output module is respectively connected to the third node, the fourth clock signal terminal, the first power signal terminal, the second power signal terminal, the second control signal terminal and the scan pulse output terminal for When the second control signal terminal inputs the second reset invalid signal and the third node is at the first level, write the clock signal of the fourth clock signal terminal into the scan pulse output terminal;

The scan drive unit is connected to the scan pulse output terminal, the touch drive signal terminal, and the touch scan drive signal output terminal, and is used to transmit the signal input from the touch drive signal terminal to the touch scan drive according to the signal output from the scan pulse output terminal. signal output;

Among the touch drive units of two adjacent levels, the third node of the touch drive unit of the upper level is connected to the second input signal terminal of the touch drive unit of the next level; the third node of the touch drive unit of the next level is connected to The first input signal terminal in the upper-level touch drive unit.

Further, the input module includes: a first transmission gate;

The input terminal of the first transmission gate is connected to the first input signal terminal, the first control terminal is connected to the first clock signal terminal, the second control terminal is connected to the second clock signal terminal, and the output terminal is connected to the second clock signal terminal. The first node is connected; suitable for conducting when the first control terminal is at the first level and the second control terminal is at the second level.

Further, the power consumption reducing module includes: a NOR gate, a first inverter, a second transmission gate and a first transistor,

The first input terminal of the NOR gate is connected to the first input signal terminal, the second input terminal is connected to the second input signal terminal, and the output terminal is respectively connected to the input terminal of the first inverter and the The second control terminal of the second transmission gate is connected to the gate of the first transistor;

The output end of the first inverter is connected to the first control end of the second transmission gate;

The input terminal of the second transmission gate is connected to the third clock signal terminal, and the output terminal is connected to the second node; it is suitable for the first control terminal to be the first level and the second control terminal to be the second voltage Normal conduction;

The first pole of the first transistor is connected to the first power signal terminal, and the second pole is connected to the second node; the conduction level is the first level.

Further, the output module includes: a third transmission gate, a second inverter, a third inverter, a fourth inverter, a second transistor, a third transistor, and a fourth transistor,

The input terminal of the third transmission gate is connected to the fourth clock signal terminal, the first control terminal is connected to the third node, and the second control terminal is respectively connected to the output terminal of the second inverter and the The gate of the fourth transistor is connected, and the output terminal is connected to the input terminal of the third inverter; it is suitable for conducting when the first control terminal is at the first level and the second control terminal is at the second level;

The input end of the second inverter is connected to the third node;

The output end of the third inverter is connected to the input end of the fourth inverter;

The output end of the fourth inverter is connected to the scan pulse output end;

The first pole of the second transistor is connected to the second power signal terminal, the second pole is connected to the input terminal of the third inverter, and the gate is connected to the second control signal terminal;

The first pole of the third transistor is connected to the second pole of the fourth transistor, the second pole is connected to the input terminal of the third inverter, and the gate is connected to the second control signal terminal;

The first pole of the fourth transistor is connected to the first power signal terminal;

The turn-on levels of the second transistor and the third transistor are opposite; the turn-on level of the third transistor is the level of the second reset valid signal; the turn-on level of the fourth transistor for the first level.

Further, both the turn-on level of the third transistor and the second active reset signal are at the first level.

Further, the shift register module includes a first tri-state gate, a second tri-state gate, a fifth inverter, a sixth inverter and a fifth transistor; wherein, the input end of the fifth inverter is connected to the first Two nodes, the output terminal is connected to the fifth node; the input terminal of the sixth inverter is connected to the fourth node, and the output terminal is connected to the third node; the first control terminal of the first tri-state gate and the second control terminal of the second tri-state gate The terminal is connected to the second node, and the first control terminal of the second tri-state gate and the second control terminal of the first tri-state gate are connected to the fifth node;

The input end of the first tri-state gate is connected to the first node, and the output end is connected to the fourth node; the input end of the second tri-state gate is connected to the third node, and the output end is connected to the fourth node; the first pole of the fifth transistor is connected to the fourth node. The second power signal terminal and the second pole are connected to the fourth node, the gate is connected to the first control signal terminal, and the conduction level is the level of the first reset valid signal; each three The state gate is suitable for inverting the signal at the input terminal and outputting it through the output terminal when the first control terminal is at the first level and the second control terminal is at the second level.

Further, the scan driving unit includes a gating module, an inversion amplification module and an inversion interception module;

Wherein, the gating module is connected to the scan pulse output terminal, the sixth node, the first power signal terminal, the third control signal terminal and the fourth control signal terminal; it is used for inputting the third reset valid signal at the third control signal terminal , write the signal of the first power signal terminal to the sixth node; when the third control signal terminal inputs the third reset invalid signal and the scan pulse output terminal is at the first level, write the signal of the fourth control signal terminal to the sixth node node;

an inverting amplification module, connected to the sixth node and the seventh node, for amplifying and inverting the signal written to the sixth node and outputting it to the seventh node;

The reverse phase interception module is connected to the seventh node, the touch drive signal terminal, the third power supply signal terminal and the touch scan drive signal output terminal; it is used to drive the touch drive signal when the signal input at the seventh node is an output enable signal. The signal at the signal terminal is output to the touch scanning driving signal output terminal; when the signal input at the seventh node is an output invalid signal, the signal at the third power supply signal terminal is output to the touch scanning driving signal output terminal.

Further, the gating module includes a fourth transmission gate, a seventh inverter, a seventh transistor, and an eighth transistor; the first control terminal of the fourth transmission gate is connected to the scan pulse output terminal, and the second control terminal connected to the eighth node; the input end is connected to the fourth control signal end; the input end of the seventh inverter is connected to the input end to the scan pulse output end, and the output end is connected to the eighth node;

The first stages of the seventh transistor and the eighth transistor are both connected to the sixth node, and the second poles are connected to the first power signal terminal; the gate of the seventh transistor is connected to the eighth node, and the gate of the eighth transistor is connected to the third node. The control signal terminal; the conduction level of the seventh transistor, the conduction level of the eighth transistor and the third reset valid signal are all at the first level.

Further, the inverting amplification module includes an eighth inverter, a ninth inverter and a tenth inverter;

The input end of the eighth inverter is connected to the sixth node, and the output end is connected to the input end of the ninth inverter;

The input end of the tenth inverter is connected to the output end of the ninth inverter, and the output end is connected to the seventh node.

Further, the reverse phase interception module includes:

a fifth transmission gate, a sixth transmission gate and an eleventh inverter;

The input end of the eleventh inverter is connected to the seventh node, and the output end is connected to the ninth node;

Wherein the first control terminal of the fifth transmission gate and the second control terminal of the sixth transmission gate are connected to the ninth node; the second control terminal of the fifth transmission gate and the first control terminal of the sixth transmission gate are connected to the seventh node; The output terminals of the fifth transmission gate and the sixth transmission gate are both connected to the output terminal of the touch scanning driving signal;

The input terminal of the fifth transmission gate is connected to the touch driving signal terminal, and the input terminal of the sixth transmission gate is connected to the third power supply signal terminal;

Both the fifth transmission gate and the sixth transmission gate are turned on when the first control terminal is at the first level and the second control terminal is at the second level; the output enable signal is at the first level, and the output The invalid signal is at the second level.

In the second aspect, the present invention provides a touch display device, which is characterized in that it includes a substrate and a touch driving circuit formed on the substrate through a patterning process; the touch driving circuit is any one of the above-mentioned touch drive circuit.

In the touch drive circuit provided by the present invention, a power consumption reduction module is provided, and the power consumption reduction module is controlled by the first input signal from the first input signal terminal and the second input signal from the second input signal terminal , writing the first clock signal of the first clock signal terminal CLK1 or the first power signal of the first power signal terminal VGL into the second node. In this way, the first clock signal of the first clock signal terminal CLK1 can be prevented from continuously being input to the second node, thereby reducing corresponding power consumption.

Description of drawings

The characteristic information and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way, in the accompanying drawings:

FIG. 1 is a schematic structural diagram of a touch drive unit in a touch drive circuit in the prior art;

FIG. 2 is a schematic diagram of driving a touch driving circuit including the touch driving unit in FIG. 1;

FIG. 3 is a schematic structural diagram of a touch driving unit in a touch driving circuit according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a touch driving circuit provided by an embodiment of the present invention;

FIG. 5 is a potential diagram of some signals and some nodes in the method for driving the touch driving circuit provided in FIG. 4 according to the present invention.

Detailed ways

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

The structure of each level of touch drive unit TXD in a touch drive circuit in the prior art can refer to FIG. 1, including a shift register unit 110 and a scan drive unit 120; wherein the shift register unit 110 includes: a shift register module 113 and output module 112;

The output module 112 includes: a third transmission gate TR3, a second inverter OP2, a third inverter OP2, and a fourth inverter OP3;

The input terminal of the third transmission gate TR3 is connected to the fourth clock signal terminal CLK4, the first control terminal is connected to the third node N3, the second control terminal is connected to the output terminal of the second inverter OP2, and the output terminal is connected to the scan pulse output Terminal OUTPUT connection; conduction when the first control terminal is high level and the second control terminal is low level;

The input end of the second inverter OP2 is connected to the third node N3;

The shift register module 113 includes a first tri-state gate S1, a second tri-state gate S2, a fifth inverter OP5, a sixth inverter OP6 and a fifth transistor T5; wherein, the input terminal of the fifth inverter OP5 Connect the third clock signal input terminal CLK3, the output terminal is connected to the fifth node N5; the input terminal of the sixth inverter OP6 is connected to the fourth node N4, and the output terminal is connected to the third node N3; the first control of the first tri-state gate S1 The terminal and the second control terminal of the second tri-state gate S2 are connected to the third clock signal input terminal CLK3, and the first control terminal of the second tri-state gate S2 and the second control terminal of the first tri-state gate S1 are connected to the fifth node;

The input end of the first tri-state gate S1 is connected to the third clock signal input end CLK3, and the output end is connected to the fourth node N4; the input end of the second tri-state gate S2 is connected to the third node N3, and the output end is connected to the fourth node N4; The first pole of the fifth transistor T5 is connected to the second power signal terminal VGH, the second pole is connected to the third node N3, the gate is connected to the first control signal terminal EN1, and the conduction level is the first reset The level of the effective signal; each tri-state gate is used to invert the signal at the input terminal and output it through the output terminal when the first control terminal is at the first level and the second control terminal is at the second level;

The scanning driving unit 120 is connected to the scanning pulse output terminal OUTPUT, the touch driving signal terminal TX and the touch scanning driving signal output terminal TX-OUT, and is used to input the signal input from the touch driving signal terminal TX according to the signal output from the scanning pulse output terminal OUTPUT. It is transmitted to the touch scanning driving signal output terminal TX-OUT.

The touch drive unit TXD in Figure 1 can be driven by the driving method shown in Figure 2, see Figure 2: Assume that the first level is high and the second level is low; , a DC high level can be applied to the second power signal terminal VGH; a DC low level can be applied to the first power signal terminal VGL; a duty cycle can be applied to both the third clock signal line CLKA and the fourth clock signal line CLKB 1/2 of the clock signal, and the third clock signal line CLKA and the fourth clock signal line CLKB are applied on the third clock signal line CLKA and the fourth clock signal line CLKB clock signal with a duty ratio of 1/2 is opposite in phase; The width of the start signal input in the input signal terminal INPUT1 of 1 is one clock cycle, and the rising edge of the input signal is the same as the rising edge of the clock signal applied on the fourth clock signal line CLKB, and the falling edge of the input signal The edge is the same as the falling edge of the clock signal applied on the third clock signal line CLKA;

First, in the first stage Stg1, the input signal terminal INPUT1 is at high level, and the third clock signal terminal CLK3 is at low level; then the first tri-state gate S1 cannot be opened at this stage, and accordingly the fourth node N4 cannot be set to low level, it is impossible to set the third node N3 to a high level;

In the second stage Stg2, the input signal terminal INPUT1 is at a high level, and the third clock signal terminal CLK3 is also at a high level; at this time, the first tri-state gate S1 is turned on, and the fourth node N4 is set at a low level; In turn, the third node N3 is set to a high level; and since the fifth node N5 is set to a low level, the second tri-state gate S2 cannot be turned on at this time; at this stage, the fourth clock signal CLK4 is a low level level, the scan pulse output terminal OUTPUT outputs a low level;

In the third stage Stg3, the input signal terminal INPUT1 is low level, and the third clock signal terminal CLK3 is also low level; then the first tri-state gate S1 cannot be opened at this time; the third clock signal terminal CLK3 is low level, Cause the fifth node N5 to be a high level, thereby causing the second tri-state gate S2 to be turned on; thus the fourth node N4 is set to the opposite level of the level of the third node N3, that is, a low level; and the fourth node When N4 is at low level, it will cause the third node N3 to be at high level; thus making the third node N3 maintain at high level; at this stage, the fourth clock signal CLK4 is at high level, and the scan pulse output terminal OUTPUT output high level; the scan drive unit 120 transmits the signal input from the touch drive signal terminal TX to the touch scan drive signal output terminal TX-OUT at this stage to form a touch drive scan signal;

In the fourth stage Stg4, the input signal terminal INPUT1 is at low level, and the third clock signal terminal CLK3 is at high level; at this time, the first tri-state gate S1 is turned on, and the fourth node N4 is set at high level; and So that the fourth node N4 is set to a low level. The reset of the third node N3 is realized. After this stage and before the next scan, since the input signal terminal INPUT1 is no longer at a high level, the level of the fourth node N4 will no longer be set at a low level. Correspondingly, the third node N3 will no longer be set to a high level; that is, the touch driving scan signal will no longer be output.

It can be seen that the third clock signal terminal CLK3 will be after the fourth stage Stg4, and the fifth node N5 will be pulled high and low repeatedly, which will inevitably cause waste of electric energy and is not conducive to reducing power consumption.

In view of the above problems, an embodiment of the present invention provides a touch driving circuit, as shown in FIG. 3 and FIG. 4 , the touch driving circuit includes a multi-level touch driving unit TXD (the nth level is represented as TXD-n ), each level of touch drive unit TXD-n includes a shift register unit 110 and a scan drive unit 120; wherein the shift register unit 110 includes: an input module 111, a power reduction module 114, a shift register module 113 and an output module 112;

The input module 111 is respectively connected to the first input signal terminal INPUT1, the first node N1, the first clock signal terminal CLK1 and the second clock signal terminal CLK2, for when the first clock signal terminal CLK1 is at the first level and the second clock When the signal terminal CLK2 is at the second level, write the signal of the first input signal terminal INPUT1 into the first node N1;

The power consumption reducing module 114 is respectively connected with the first input signal terminal INPUT1, the second input signal terminal INPUT2, the third clock signal terminal CLK3, the first power signal terminal VGL and the second node N2, for the first input signal terminal INPUT1 When any signal terminal in the second input signal terminal INPUT2 is at the first level, the third clock signal of the third clock signal terminal CLK3 is written into the second node N2; at the first input signal terminal INPUT1 and the second input When the signal terminal INPUT2 is at the second level, write the first power signal of the first power signal terminal VGL into the second node N2;

The shift register module 113 is respectively connected to the first node N1, the second node N2, the third node N3, the first control signal terminal EN1 and the second power signal terminal VGH, and is used to input the first reset at the first control signal terminal EN1 When the signal is valid, the third node N3 is set as the inversion signal of the power signal of the second power signal terminal VGH; when the first reset invalid signal is input at the first control signal terminal EN1 and the second node N2 is at the first level, the writing the signal of the first node N1 into the third node N3;

The output module 112 is respectively connected with the third node N3, the fourth clock signal terminal CLK4, the first power signal terminal VGL, the second power signal terminal VGH, the second control signal terminal EN2 and the scan pulse output terminal OUTPUT, and is used in the second When the second reset valid signal is input to the control signal terminal EN2, the first power signal of the first power signal terminal VGL is written into the scan pulse output terminal OUTPUT; the second reset invalid signal is input at the second control signal terminal EN2 and the third node When N3 is at the first level, write the clock signal of the fourth clock signal terminal CLK4 into the scan pulse output terminal OUTPUT;

The scanning driving unit 120 is connected to the scanning pulse output terminal OUTPUT, the touch driving signal terminal TX and the touch scanning driving signal output terminal TX-OUT, and is used to input the signal input from the touch driving signal terminal TX according to the signal output from the scanning pulse output terminal OUTPUT. Transmit to the touch scanning drive signal output terminal TX-OUT;

Two adjacent levels of touch drive units, such as the first level touch drive unit TXD-1 and the second level touch drive unit TXD-2, the third node N3 of the upper level touch drive unit TXD-1 is connected to The first input signal terminal INPUT1 in the next-level touch drive unit TXD-2; the third node N3 of the next-level touch drive unit TXD-1 is connected to the second input signal terminal INPUT2 in the upper-level touch drive unit ; and the odd-numbered touch drive units in each touch drive unit (such as the first-level touch drive unit TXD-1, and the penultimate second-level touch drive unit TXD-(M-1), here it is assumed that M is an even number ) in the shift register unit 110 of the first clock signal terminal CLK1 and each even-level touch drive unit (such as the first-level touch drive unit TXD-1, and the last-level touch drive unit TXD-M) The second clock signal terminal CLK2 of the shift register unit 110 is connected to the first clock signal line CN; the second clock signal terminal CLK2 of the shift register unit 110 in the odd-numbered touch drive unit is connected to the touch The first clock signal terminal CLK1 of the shift register unit 110 in the drive unit is connected to the second clock signal line CNB; the third clock signal terminal CLK3 of the shift register unit 110 in the odd-numbered touch drive unit is connected to each even-level The fourth clock signal terminal CLK4 of the shift register unit 110 in the touch drive unit TXD is connected to the third clock signal line CLKA; the fourth clock signal terminal CLK4 of the shift register unit 110 in the odd-numbered touch drive unit The third clock signal line CLKB is connected to the third clock signal terminal CLK3 of the shift register unit 110 in the touch driving units of each even stage.

In specific implementation, for the touch driving circuit in FIG. 3 and FIG. 4 , compared with the touch driving circuit composed of the touch driving unit in FIG. 1 , the power consumption can be reduced. The principle will be described in detail below in conjunction with the accompanying drawings.

It is also assumed that the first level is high level and the second level is low level; then in the corresponding driving method, a DC low level can be applied to the first power signal terminal VGL. A high level of direct current is applied to the second power supply signal terminal VGH; in addition, referring to FIG. 5, the method may also include:

In the display phase (not shown in the figure), the corresponding reset active level (assumed to be high level) is applied to the first control signal terminal EN1, the second control signal terminal EN2 and the third control signal terminal EN3; For any level of scanning drive unit, at this time, the power consumption reducing module 114 will set the level of the third node N3 to a level opposite to the level applied to the second power signal terminal VGH, that is, a low level; The scan pulse output terminal OUTPUT will be set to high level only when the third node N3 is high level; therefore, at this stage, the scan pulse output terminal OUTPUT will not be set to low level; in addition, the output module 112 will The power signal (low level) of the first power signal terminal VGL is written into the scan pulse output terminal OUTPUT, further ensuring that the scan pulse output terminal OUTPUT is set to low level. In addition, at this stage, the input signal terminals INPUT1 and INPUT2 of the touch drive units at all levels will not have a high level input, so the first node N1 and the second node N2 will maintain a low level;

In the touch stage; the corresponding reset invalid level (low level shown in the figure) is applied to the first control signal terminal EN1, the second control signal terminal EN2 and the third control signal terminal EN3; A clock signal with a duty ratio of 1/2 is applied to the clock signal line CN, the second clock signal line CNB, the third clock signal line CLKA and the fourth clock signal line CLKB; and the first clock signal line CN and the third clock signal line The clock signal of the clock signal line CLKA is synchronous, and the phase of the clock signal of the second clock signal line CNB and the fourth clock signal line CLKB is also synchronous; and the clock signal applied on the first clock signal line CN and the third clock signal line CLKA The phase of the clock signal applied to the second clock signal line CNB and the fourth clock signal line CLKB is opposite in real time; in addition, a starting signal is applied to the first input signal terminal INPUT1 in the first-level touch drive unit TXD-1. Start pulse, the width of the start pulse is the same as the width of one clock period of any one of the clock signals mentioned above; The rising edge is consistent with the rising edge, and the falling edge is consistent with the falling edge of a high-level pulse in the first clock signal line CN and the third clock signal line CLKA;

For the first-level touch drive unit TXD-1, in the first stage Stg1, the first clock signal terminal CLK1 (connected to the first clock signal line CN) is at low level, and the input module 111 cannot connect the first input signal terminal The signal of INPUT1 (high level at this time) is output to the first node N1; in addition, since the first input signal terminal INPUT1 is high level, the power consumption reducing module 114 will output the signal of the third clock signal terminal CLK3 ( It is low level at this time) is written to the second node N2; referring to the Stg1 stage description of the touch drive unit in FIG. 1 and the driving method shown in FIG. 2, it can be known that the third node N3 is low level at this time; Correspondingly, the scanning pulse output terminal OUTPUT is also at low level, and the touch scanning driving signal output terminal TX-OUT will not output the touch scanning driving signal;

In the second stage Stg2, for the first-level touch drive unit TXD-1, the first clock signal terminal CLK1 (connected to the first clock signal line CN) is at a high level, and the second clock signal terminal CLK2 (connected to the second The clock signal line CNB) is low level; the input module 111 outputs the signal (high level at this time) of the first input signal terminal INPUT1 to the first node N1, causing the first node N1 to be high level; and at this time The first input signal terminal INPUT1 is still maintained at a high level, which will cause the power reduction module 114 to write the signal of the third clock signal terminal CLK3 (high level at this time) into the second node N2, resulting in the second node N2 N2 is set to a high level; referring to the Stg2 stage description of the touch drive unit in FIG. 1 and the driving method shown in FIG. If the four clock signal terminal CLK4 (connected to the fourth clock signal line CLKB) is at low level, then the scan pulse output terminal OUTPUT will still not output high level at this time;

For the second-level touch drive unit TXD-2, the state of each clock signal terminal and the state of each signal input terminal are the same as the state of the port corresponding to the first-level touch drive unit TXD-1 in the first stage Stg1, then The level state of the corresponding node is the same as the level state of the corresponding node in the first-level touch driving unit TXD- 1 in the first stage Stg1.

In the third stage Stg3, for the second-level touch drive unit TXD-2, the state of each clock signal terminal and the state of each signal input terminal correspond to the port corresponding to the first-level touch drive unit TXD-1 in the second stage The state of Stg2 is the same, and the level state of the corresponding node is the same as the level state of the corresponding node in the first-level touch drive unit TXD-1 in the second stage Stg2; that is, in this stage, the second-level touch The third node N3 of the driving unit TXD-2 is at a high level;

For the first-level touch drive unit TXD-1, in the first stage Stg1, the first clock signal terminal CLK1 (connected to the first clock signal line CN) is at low level, and the input module 111 cannot connect the first input signal terminal The signal of INPUT1 (high level at this time) is output to the first node N1; at this time, the second input signal terminal INPUT2 (connected to the third node N3 of the second-level touch drive unit TXD-2) is also high level, Then at this time, the power consumption reduction module 114 writes the clock signal (low level) of the third clock signal terminal CLK3 into the second node N2, and sets the second node to a low level; It can be seen from the Stg3 stage description of the touch driving unit and the driving method shown in FIG. 2 that at this time, the third node N3 and the scan pulse output terminal OUTPUT are both set to high level;

In the fourth stage Stg4, for the second-level touch drive unit TXD-2, the state of each clock signal terminal and the state of each signal input terminal are in the third stage corresponding to the port corresponding to the first-level touch drive unit TXD-1. The state of Stg3 is the same, and the level state of the corresponding node is the same as the level state of the corresponding node in the first-level touch drive unit TXD-1 in the third stage Stg3; that is, in this stage, the second-level touch The third node N3 of the drive unit TXD-2 continues to maintain a high level;

For the first-level touch drive unit TXD-1, the first clock signal terminal CLK1 (connected to the first clock signal line CN) is high level, and the second clock signal terminal CLK2 (connected to the second clock signal line CNB) is Low level; the input module 111 outputs the signal of the first input signal terminal INPUT1 (high level at this time) to the first node N1, causing the first node N1 to be low level; at this time, the second input signal terminal INPUT2 If it remains at a high level, the power consumption reducing module 114 will write the signal of the third clock signal terminal CLK3 (high level at this time) into the second node N2, causing the second node N2 to be set to a high level. level; refer to the description of the touch drive unit in FIG. 1 and the Stg4 stage of the driving method shown in FIG.

After this stage Stg4, before the next scan, since both the first input signal terminal INPUT1 and the second input signal terminal INPUT2 are no longer at high level, the clock signal input by the third clock signal terminal CLK3 will not be written to In this way, on the one hand, the touch drive circuit will no longer output the touch drive scan signal, and on the other hand, it can well avoid power consumption. In addition, since the output module 112 is set to write the power signal of the first DC power supply terminal VGL into the scan pulse output terminal OUTPUT when the second effective reset signal is applied to the second control signal terminal EN2, the output of the scan pulse can be better realized. Reset of terminal OUTPUT.

From the above description, it can be seen that in the two adjacent levels of touch driving units, the potentials of each port of the lower level touch driving unit and the corresponding nodes at the current stage are the same as those of the ports of the upper level touch driving unit and the corresponding nodes. The potential state of the node in the previous phase will be exactly the same. Thus, the entire scan driving process is completed.

It can be known from the above description that on the premise that corresponding functions can be realized, the specific design of each module will not affect the protection scope of the present invention. An example is given below.

Referring to FIG. 3, the input module 111 may include: a first transmission gate TR1;

The input terminal of the first transmission gate TR1 is connected to the first input signal terminal INPUT1, and the first control terminal (for convenience of description, the end with a circle in each transmission gate is named as the second control terminal, and the end without a circle is named as The first control terminal) is connected to the first clock signal terminal CLK1, the second control terminal is connected to the second control signal terminal EN2, and the output terminal is connected to the first node N1; it is suitable for the first control terminal to be at the first level And the second control terminal is turned on when it is at the second level. In this way, when the first control terminal is at the first level and the second control terminal is at the second level, the first transmission gate TR1 is turned on, and the level of its output terminal is consistent with that of the input terminal. Thus, the function of the above-mentioned input module 111 is realized. And because the transmission gate itself has a shaping function, this design can realize the shaping of the signal input by the first input signal terminal INPUT1, and improve the regularity of the touch driving signal output by the touch driving unit.

The power consumption reducing module 114 may specifically include: a NOR gate NR, a first inverter OP1, a second transmission gate TR2 and a first transistor T1;

The first input terminal of the NOR gate NR is connected to the first input signal terminal INPUT1, the second input terminal is connected to the second input signal terminal INPUT2, and the output terminals are respectively connected to the input terminal of the first inverter OP1 and the first transmission gate TR1. The second control terminal of is connected to the gate of the first transistor T1;

The output end of the first inverter OP1 is connected to the first control end of the second transmission gate TR2;

The input terminal of the second transmission gate TR2 is connected to the third clock signal terminal CLK3, and the output terminal is connected to the second node N2; it is suitable for conducting when the first control terminal is at the first level and the second control terminal is at the second level ;

The first pole of the first transistor T1 is connected to the first power signal terminal VGL, and the second pole is connected to the second node of N2; the conduction level is the first level.

Such a structure realizes the above-mentioned principle of power consumption module 114: when any one of the first input signal terminal INPUT1 and the second input signal terminal INPUT2 is at the first level, the output terminal of the NOR gate NR is The second level causes the first transistor T1 to be turned off to realize the reset of the N2 node. The output terminal of the NOR gate NR is at the second level, which will cause the first control terminal of the second transmission gate TR2 to be at the first level, thus achieving the opening condition of the second transmission gate TR2, so that the second node N2 The level of is set to be consistent with the level of the second transmission gate TR2, thus realizing the function of the power consumption reducing module 114 mentioned above. And because the first transistor T1 is provided, the second node N2 can be well reset to avoid corresponding noise interference.

In specific implementation, the output module 112 may include: a third transmission gate TR3, a second inverter OP2, a third inverter OP2, a fourth inverter OP3, a second transistor T2, a third transistor T3 and a fourth Transistor T4,

The input terminal of the third transmission gate TR3 is connected to the fourth clock signal terminal CLK4, the first control terminal is connected to the third node N3, and the second control terminal is connected to the output terminal of the second inverter OP2 and the gate of the fourth transistor T4 respectively. Pole connection, the output end is connected with the input end of the third inverter OP3;

The input end of the second inverter OP2 is connected to the third node N3;

The output end of the third inverter OP3 is connected to the input end of the fourth inverter OP4;

The output end of the fourth inverter OP4 is connected to the scan pulse output end OUTPUT;

The first pole of the second transistor T2 is connected to the second power signal terminal VGH, the second pole is connected to the input terminal of the third inverter OP3, and the gate is connected to the second control signal terminal EN2;

The first pole of the third transistor T3 is connected to the second pole of the fourth transistor T4, the second pole is connected to the input terminal of the third inverter OP3, and the gate is connected to the second control signal terminal EN2;

The first pole of the fourth transistor T4 is connected to the first power signal terminal VGL;

The turn-on levels of the second transistor T2 and the third transistor T3 are opposite; the turn-on level of the third transistor T3 is the level of the second active reset signal; the turn-on level of the fourth transistor T4 is the second level.

Furthermore, the turn-on level of the third transistor T3 and the second valid reset signal are both at the first level.

The shift register module 113 may include a first tri-state gate S1, a second tri-state gate S2, a fifth inverter OP5, a sixth inverter OP6 and a fifth transistor T5; wherein, the input of the fifth inverter OP5 terminal is connected to the second node N2, and the output terminal is connected to the fifth node N5; the input terminal of the sixth inverter OP6 is connected to the fourth node N4, and the output terminal is connected to the third node N3; the first control terminal of the first tri-state gate S1 and The second control terminal of the second tri-state gate S2 is connected to the second node, and the first control terminal of the second tri-state gate S2 and the second control terminal of the first tri-state gate S1 are connected to the fifth node;

The input end of the first tri-state gate S1 is connected to the first node N1, and the output end is connected to the fourth node N4; the input end of the second tri-state gate S2 is connected to the third node N3, and the output end is connected to the third node N3; the fifth transistor T5 The first pole of the grid is connected to the second power supply signal terminal VGH, the second pole is connected to the fourth node N4, the gate is connected to the first control signal terminal EN1, and the conduction level is the level of the first reset valid signal; each three The state gate is used for inverting the signal at the input terminal and outputting it through the output terminal when the first control terminal is at the first level and the second control terminal is at the second level.

The scanning driving unit 120 may include a gating module 121, an inverting amplification module 122 and an inverting intercepting module 123;

Wherein, the gating module 121 is connected to the scan pulse output terminal OUTPUT, the sixth node N6, the first power signal terminal VGL, the third control signal terminal EN3 and the fourth control signal terminal TX_EN; When the three-reset valid signal is used, the signal of the first power signal terminal VGL is written into the sixth node N6; when the third reset invalid signal is input at the third control signal terminal EN3 and the scan pulse output terminal OUTPUT is at the first level, the second The signal TX_EN of the four control signal terminals is written into the sixth node N6;

The inverting amplification module 122 is connected to the sixth node N6 and the seventh node N7, and is used to amplify and invert the signal written to the sixth node N6 and output it to the seventh node N7;

The reverse phase interception module 123 is connected to the seventh node N7, the touch drive signal terminal TX, the third power supply signal terminal VCOM, and the touch scan drive signal output terminal TX-OUT; the signal input at the seventh node N7 is used to output When the signal is enabled, the signal of the touch driving signal terminal TX is output to the touch scanning driving signal output terminal TX-OUT; when the signal input at the seventh node N7 is an output invalid signal, the signal of the third power signal terminal VCOM output to the touch scanning drive signal output terminal TX-OUT.

The gating module 121 may include a fourth transmission gate TR4, a seventh inverter OP7, a seventh transistor T7, and an eighth transistor T8; the first control terminal of the fourth transmission gate TR4 is connected to the scan pulse output terminal OUTPUT, and the second control terminal The terminal is connected to the eighth node N8; the input terminal is connected to the fourth control signal terminal TX_EN; the input terminal of the seventh inverter OP7 is connected to the input terminal to the scan pulse output terminal OUTPUT, and the output terminal is connected to the eighth node N8;

Both the first poles of the seventh transistor T7 and the eighth transistor T8 are connected to the sixth node N6, and the second poles are both connected to the first power signal terminal VGL; the gate of the seventh transistor T7 is connected to the eighth node N8, and the gate of the eighth transistor T8 The gate is connected to the third control signal terminal EN3; the conduction level of the seventh transistor T7, the conduction level of the eighth transistor T8 and the third reset active signal are all at the first level.

The inverting and amplifying module 122 may include an eighth inverter OP8, a ninth inverter OP9, and a tenth inverter OP10;

The input end of the eighth inverter OP8 is connected to the sixth node N6, and the output end is connected to the input end of the ninth inverter OP9;

The input end of the tenth inverter OP10 is connected to the output end of the ninth inverter OP9, and the output end is connected to the seventh node N7.

The anti-phase interception module 123 may include:

The fifth transmission gate TR5, the sixth transmission gate TR6 and the eleventh inverter OP11;

The input end of the eleventh inverter OP11 is connected to the seventh node N7, and the output end is connected to the ninth node N9;

The first control terminal of the fifth transmission gate TR5 and the second control terminal of the sixth transmission gate TR6 are connected to the ninth node N9; the second control terminal of the fifth transmission gate TR5 is connected to the first control terminal of the sixth transmission gate TR6 The seventh node N7; the output terminals of the fifth transmission gate TR5 and the sixth transmission gate TR6 are both connected to the touch scanning driving signal output terminal TX-OUT;

The input terminal of the fifth transmission gate TR5 is connected to the touch driving signal terminal TX, and the input terminal of the sixth transmission gate TR6 is connected to the third power signal terminal VCOM;

Both the fifth transmission gate TR5 and the sixth transmission gate TR6 are turned on when the first control terminal is at the first level and the second control terminal is at the second level; the output enable signal is at the first level, and the output invalid signal is at the second level. Two levels.

In the second aspect, the present invention also provides a touch display device, including a substrate and a touch driving circuit formed on the substrate through a patterning process; the touch driving circuit is the touch driving circuit described in any one of the above circuit.

The touch display device here can be: electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator and any other product or component with display function.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (11)

1. A touch drive circuit, characterized in that it comprises a multi-level scan drive unit; each level of touch drive unit includes a shift register unit and a scan drive unit; wherein the shift register unit includes: an input module, a lower power consumption block, shift register block and output block, The input module is respectively connected to the first input signal terminal, the first node, the first clock signal terminal and the second clock signal terminal, so that the first clock signal terminal is at a first level and the second clock signal terminal When it is at the second level, write the signal of the first input signal terminal into the first node; The power consumption reducing module is respectively connected to the first input signal terminal, the second input signal terminal, the third clock signal terminal, the first power supply signal terminal and the second node, and is used to connect the first input signal terminal and the second When any signal terminal in the input signal terminal is at the first level, write the third clock signal of the first clock signal terminal into the second node; both the first input signal terminal and the second input signal terminal are the second level, write the first power signal of the first power signal terminal into the second node; The shift register module is respectively connected to the first node, the second node, the third node, the first control signal terminal and the second power signal terminal, and is used to input the first When the reset valid signal is active, the third node is set as the inversion signal of the power signal at the second power signal terminal; when the first reset invalid signal is input at the first control signal terminal and the second node is at the first level, the first node is set to The signal is written to the third node; The output module is respectively connected to the third node, the fourth clock signal terminal, the first power signal terminal, the second power signal terminal, the second control signal terminal and the scan pulse output terminal, for When the second control signal terminal inputs the second reset invalid signal and the third node is at the first level, write the clock signal of the fourth clock signal terminal into the scan pulse output terminal; The scan drive unit is connected to the scan pulse output terminal, the touch drive signal terminal, and the touch scan drive signal output terminal, and is used to transmit the signal input from the touch drive signal terminal to the touch scan drive according to the signal output from the scan pulse output terminal. signal output; Among the touch drive units of two adjacent levels, the third node of the touch drive unit of the upper level is connected to the second input signal terminal of the touch drive unit of the next level; the third node of the touch drive unit of the next level is connected to The first input signal terminal in the upper-level touch drive unit. 2. The touch driving circuit according to claim 1, wherein the input module comprises: a first transmission gate; The input terminal of the first transmission gate is connected to the first input signal terminal, the first control terminal is connected to the first clock signal terminal, the second control terminal is connected to the second clock signal terminal, and the output terminal is connected to the second clock signal terminal. The first node is connected; suitable for conducting when the first control terminal is at the first level and the second control terminal is at the second level. 3. The touch drive circuit according to claim 1, wherein the power consumption reducing module comprises: a NOR gate, a first inverter, a second transmission gate and a first transistor, The first input terminal of the NOR gate is connected to the first input signal terminal, the second input terminal is connected to the second input signal terminal, and the output terminal is respectively connected to the input terminal of the first inverter and the The second control terminal of the second transmission gate is connected to the gate of the first transistor; The output end of the first inverter is connected to the first control end of the second transmission gate; The input terminal of the second transmission gate is connected to the third clock signal terminal, and the output terminal is connected to the second node; it is suitable for the first control terminal to be the first level and the second control terminal to be the second voltage Normal conduction; The first pole of the first transistor is connected to the first power signal terminal, and the second pole is connected to the second node; the conduction level is the first level. 4. The touch drive circuit according to claim 1, wherein the output module comprises: a third transmission gate, a second inverter, a third inverter, a fourth inverter, and a second transistor , the third transistor and the fourth transistor, The input terminal of the third transmission gate is connected to the fourth clock signal terminal, the first control terminal is connected to the third node, and the second control terminal is respectively connected to the output terminal of the second inverter and the The gate of the fourth transistor is connected, and the output terminal is connected to the input terminal of the third inverter; it is suitable for conducting when the first control terminal is at the first level and the second control terminal is at the second level; The input end of the second inverter is connected to the third node; The output end of the third inverter is connected to the input end of the fourth inverter; The output end of the fourth inverter is connected to the scan pulse output end; The first pole of the second transistor is connected to the second power signal terminal, the second pole is connected to the input terminal of the third inverter, and the gate is connected to the second control signal terminal; The first pole of the third transistor is connected to the second pole of the fourth transistor, the second pole is connected to the input terminal of the third inverter, and the gate is connected to the second control signal terminal; The first pole of the fourth transistor is connected to the first power signal terminal; The turn-on levels of the second transistor and the third transistor are opposite; the turn-on level of the third transistor is the level of the second reset valid signal; the turn-on level of the fourth transistor is the level of the first One level. 5 . The touch driving circuit according to claim 4 , wherein both the conduction level of the third transistor and the second valid reset signal are at a first level. 6. The touch drive circuit according to claim 1, The shift register module includes a first tri-state gate, a second tri-state gate, a fifth inverter, a sixth inverter and a fifth transistor; wherein, the input end of the fifth inverter is connected to the second node, The output end is connected to the fifth node; the input end of the sixth inverter is connected to the fourth node, and the output end is connected to the third node; the first control end of the first tri-state gate and the second control end of the second tri-state gate are connected to the first Two nodes, the first control terminal of the second tri-state gate and the second control terminal of the first tri-state gate are connected to the fifth node; The input end of the first tri-state gate is connected to the first node, and the output end is connected to the fourth node; the input end of the second tri-state gate is connected to the third node, and the output end is connected to the fourth node; the first pole of the fifth transistor is connected to the fourth node. The second power signal terminal and the second pole are connected to the fourth node, the gate is connected to the first control signal terminal, and the conduction level is the level of the first reset valid signal; each three The state gate is suitable for inverting the signal at the input terminal and outputting it through the output terminal when the first control terminal is at the first level and the second control terminal is at the second level. 7. The touch drive circuit according to claim 1, characterized in that, The scanning drive unit includes a gating module, an inverting amplification module and an inverting interception module; Wherein, the gating module is connected to the scan pulse output terminal, the sixth node, the first power signal terminal, the third control signal terminal and the fourth control signal terminal; it is used for inputting the third reset valid signal at the third control signal terminal , write the signal of the first power signal terminal to the sixth node; when the third control signal terminal inputs the third reset invalid signal and the scan pulse output terminal is at the first level, write the signal of the fourth control signal terminal to the sixth node node; an inverting amplification module, connected to the sixth node and the seventh node, for amplifying and inverting the signal written to the sixth node and outputting it to the seventh node; The reverse phase interception module is connected to the seventh node, the touch drive signal terminal, the third power supply signal terminal and the touch scan drive signal output terminal; it is used to drive the touch drive signal when the signal input at the seventh node is an output enable signal. The signal at the signal terminal is output to the touch scanning driving signal output terminal; when the signal input at the seventh node is an output invalid signal, the signal at the third power supply signal terminal is output to the touch scanning driving signal output terminal. 8. The touch driving circuit according to claim 7, characterized in that, The gating module includes a fourth transmission gate, a seventh inverter, a seventh transistor, and an eighth transistor; the first control terminal of the fourth transmission gate is connected to the scan pulse output terminal, and the second control terminal is connected to the eighth node; the input end is connected to the fourth control signal end; the input end of the seventh inverter is connected to the input end and the scan pulse output end, and the output end is connected to the eighth node; The first stages of the seventh transistor and the eighth transistor are both connected to the sixth node, and the second poles are connected to the first power signal terminal; the gate of the seventh transistor is connected to the eighth node, and the gate of the eighth transistor is connected to the third node. The control signal terminal; the conduction level of the seventh transistor, the conduction level of the eighth transistor and the third reset valid signal are all at the first level. 9. The touch drive circuit according to claim 7, wherein the inverting amplification module comprises an eighth inverter, a ninth inverter and a tenth inverter; The input end of the eighth inverter is connected to the sixth node, and the output end is connected to the input end of the ninth inverter; The input end of the tenth inverter is connected to the output end of the ninth inverter, and the output end is connected to the seventh node. 10. The touch drive circuit according to claim 7, characterized in that, the reverse phase interception module comprises: a fifth transmission gate, a sixth transmission gate and an eleventh inverter; The input end of the eleventh inverter is connected to the seventh node, and the output end is connected to the ninth node; Wherein the first control terminal of the fifth transmission gate and the second control terminal of the sixth transmission gate are connected to the ninth node; the second control terminal of the fifth transmission gate and the first control terminal of the sixth transmission gate are connected to the seventh node; The output terminals of the fifth transmission gate and the sixth transmission gate are both connected to the output terminal of the touch scanning driving signal; The input terminal of the fifth transmission gate is connected to the touch driving signal terminal, and the input terminal of the sixth transmission gate is connected to the third power supply signal terminal; Both the fifth transmission gate and the sixth transmission gate are turned on when the first control terminal is at the first level and the second control terminal is at the second level; the output enable signal is at the first level, and the output The invalid signal is at the second level. 11. A touch display device, characterized in that it comprises a substrate and a touch driving circuit formed on the substrate through a patterning process; the touch driving circuit is the touch control circuit according to any one of claims 1-10. control drive circuit.