CN106200167B - Array substrate and liquid crystal display - Google Patents
Array substrate and liquid crystal display Download PDFInfo
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- CN106200167B CN106200167B CN201610729146.9A CN201610729146A CN106200167B CN 106200167 B CN106200167 B CN 106200167B CN 201610729146 A CN201610729146 A CN 201610729146A CN 106200167 B CN106200167 B CN 106200167B
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 37
- 239000003990 capacitor Substances 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 160
- 238000009413 insulation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention discloses a kind of array substrate and liquid crystal display.Gate driving circuit is formed in the array substrate, gate driving circuit includes grid layer, source/drain layer and the first insulating layer between grid layer and source/drain layer, and grid layer and source/drain layer are least partially overlapped with first capacitor needed for forming gate driving circuit.The present invention can increase the capacitor of GOA on the whole, reduce area shared by capacitor, be conducive to the narrow frame and high PPI design of LCD.
Description
Technical field
The present invention relates to technical field of liquid crystal display, in particular to a kind of array substrate and including the array substrate
Liquid crystal display.
Background technique
LCD (Liquid Crystal Display, liquid crystal display) is mesh due to the advantages that its is lightening and low-power consumption
Mainstream display device in preceding market.With the raising of the PPI (Pixels Per Inch, number of pixels or pixel density) of LCD
And the industry demand of narrow frame, the series of GOA (Gate Driver On Array, the driving of array substrate row) gradually increase,
The width of GOA is caused to become narrow gradually, this can undoubtedly make the TFT (Thin Film Transistor, thin film transistor (TFT)) in GOA
And the arrangement of capacitor is more difficult.Also, as the width of GOA becomes smaller, the occupied area of capacitor is smaller, in order to enable electric
Container has bigger capacity (Holding) with more stable work, and the capacitance of GOA just needs to be promoted.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of array substrate and liquid crystal display, it is capable of increasing the capacitor of GOA,
Area shared by capacitor is reduced, the narrow frame and high PPI design of LCD are conducive to.
A kind of array substrate provided in an embodiment of the present invention is formed with gate driving circuit, gate driving circuit packet thereon
Include grid layer, source/drain layer and the first insulating layer between grid layer and source/drain layer, wherein grid layer with
Source/drain layer is least partially overlapped, and then forms the first electricity needed for gate driving circuit as grid layer and source/drain layer
Hold.
Wherein, gate driving circuit further comprise positioned at grid layer separate source/drain layer side channel layer with
And the second insulating layer between grid layer and channel layer, wherein channel layer and grid layer are least partially overlapped, and with source electrode/
Drain electrode layer electrical connection, and then second capacitor in parallel with first capacitor is formed with channel layer by grid layer.
Wherein, it is provided with and the spaced through-hole of grid layer, source/drain layer in the first insulating layer and second insulating layer
It is electrically connected via through-hole with channel layer.
Wherein, gate driving circuit further comprise positioned at channel layer separate grid layer side light shield layer and between
Third insulating layer between channel layer and light shield layer, wherein light shield layer and the least partially overlapped setting of channel layer, and and grid layer
Electrical connection, and then the third capacitor in parallel with first capacitor and the second capacitor is formed with light shield layer by channel layer.
Wherein, be provided on second insulating layer and third insulating layer with the spaced through-hole of channel layer, grid layer via
Through-hole is electrically connected with light shield layer.
Wherein, gate driving circuit further comprises the touch-control cabling positioned at the separate grid layer side of source/drain layer
Layer and the 4th insulating layer between source/drain layer and touch-control routing layer, wherein touch-control routing layer and source/drain layer
Least partially overlapped setting, and be electrically connected with grid layer, and then formed and the first electricity by source/drain layer and touch-control routing layer
Appearance, the second capacitor, third capacitor parallel connection the 4th capacitor.
Wherein, it is provided with and the spaced through-hole of source/drain layer, grid layer on the first insulating layer and the 4th insulating layer
It is electrically connected via through-hole with touch-control routing layer.
Wherein, grid layer, source/drain layer, light shield layer and touch-control routing layer are metal layer, and channel layer is polysilicon
Layer.
A kind of liquid crystal display provided in an embodiment of the present invention, including above-mentioned array substrate.
Another kind array substrate provided in an embodiment of the present invention, is formed with gate driving circuit, gate driving circuit thereon
Multiple conductive layers including being stacked and the insulating layer between adjacent conductive layer, plurality of conductive layer be selected from by
At least three in group composed by grid layer, source/drain layer, light shield layer, channel layer and touch-control routing layer, it is multiple to lead
Electric layer is electrically connected at least two capacitors for being connected into and being connected in parallel to each other.
The utility model has the advantages that the embodiment of the present invention is driven by grid layer and the least partially overlapped formation grid of source/drain layer
A capacitor needed for dynamic circuit, the capacitor provide liquid crystal together with the capacitor that public electrode and pixel electrode insulation overlap to form and ring
Required electricity is answered, so as to increase the capacitor of GOA, area shared by capacitor is reduced, is conducive to the narrow frame and height of LCD
PPI design.
Detailed description of the invention
Fig. 1 is the structure sectional view of the liquid crystal display panel of one embodiment of the invention；
Fig. 2 is the dot structure schematic diagram of the embodiment of liquid crystal display panel one shown in Fig. 1；
Fig. 3 is the equivalent circuit diagram of dot structure shown in Fig. 2；
Fig. 4 is the structure sectional view of the array substrate of first embodiment of the invention；
Fig. 5 is the structure sectional view of the array substrate of second embodiment of the invention；
Fig. 6 is the structure sectional view of the array substrate of third embodiment of the invention；
Fig. 7 is the structure sectional view of the array substrate of fourth embodiment of the invention；
Fig. 8 is the structure sectional view of the liquid crystal display of one embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, to the skill of each exemplary embodiment provided by the present invention
Art scheme is clearly and completely described.In the absence of conflict, the feature in following each embodiments and embodiment can
To be combined with each other.
Fig. 1 is the structure sectional view of the liquid crystal display panel of one embodiment of the invention.As shown in Figure 1, the liquid of the present embodiment
LCD panel 10 include relative spacing setting color membrane substrates (Color Filter Substrate, abbreviation CF substrate, also known as
Colored filter substrate) 11 and array substrate (Thin Film Transistor Substrate, abbreviation TFT substrate are also known as thin
Film transistor substrate or Array substrate) 12 and the liquid crystal (liquid crystal molecule) 13 that is filled between two substrates, the liquid crystal 13 be located at
In the liquid crystal cell that array substrate 12 and the superposition of color membrane substrates 11 are formed.
The dot structure schematic diagram of liquid crystal display panel 10 as shown in connection with fig. 2, array substrate 12 include being arranged along column direction
Multiple data lines D, the multi-strip scanning line G along line direction setting and multiple pixel regions for being defined by scan line G and data line D
Domain P.Wherein, the corresponding data line D of each pixel region P connection and scan line a G, each scan line G are connected to grid
For pole driving circuit 21 to provide scanning voltage to each pixel region P, pieces of data line D is connected to source electrode drive circuit 22 to each
Pixel region P provides gray scale voltage.Further combined with the equivalent circuit diagram of dot structure shown in Fig. 3, gate driving circuit 21
Including TFT 14, storage capacitance CstAnd liquid crystal capacitance Clc, liquid crystal capacitance ClcBy pixel electrode, the color film positioned at pixel region P
The public electrode of 11 side of substrate and positioned between the two liquid crystal 13 formation.
According to the displaying principle of liquid crystal display panel 10, by inputting scanning voltage for scan line G, positioned at same a line
TFT 14 is simultaneously open, and is simultaneously open after a certain time positioned at the TFT 14 of next line, and so on.Due to each
The time that row TFT 14 is opened is shorter, liquid crystal capacitance ClcThe time that charge control liquid crystal 13 deflects is shorter, is extremely difficult to liquid crystal
13 response time, storage capacitance CstThe voltage of each pixel region P can be maintained after the closing of TFT 14, to be liquid crystal
13 responses provide the time.
In the prior art, storage capacitance CstIt is the public electrode and pixel electrode of 12 side of array substrate by being held on
The storage capacitance of passivation layer formation between the two.Different from the prior art, the embodiment of the present invention is in storage capacitance CstBase
Increase capacitor on plinth.
It is the structure sectional view of the array substrate of first embodiment of the invention refering to Fig. 4.The gate driving circuit 21 wraps
Each layer structure for including substrate 120 and being sequentially formed in substrate 120: the first metal layer Ml, the first insulating layer
121, second metal layer M2.Wherein, the first insulating layer 121 is buffer layer (the Interlayer dielectric of TFT 14
Isolation, abbreviation ILD), the first metal layer MlFor the grid layer of TFT 14, second metal layer M2For TFT 14 source layer or
Drain electrode layer.For ease of description, the embodiment of the present invention is with second metal layer M2To be described for source layer, certainly, second
Metal layer M2All embodiments of the invention also may be implemented for drain electrode layer.
In the present embodiment, grid layer MlWith source layer M2It is least partially overlapped, the grid layer M of laplWith source layer
M2By being held on 121 insulation set of the first insulating layer between the two, to form first capacitor Cst1.This newly increase first
Capacitor Cst1With existing storage capacitance CstLiquid crystal 13 is provided together and responds required electricity, so as to increase the capacitor of GOA,
Area shared by capacitor is reduced, the narrow frame and high PPI design of liquid crystal display panel 10 are conducive to.
It is the structure sectional view of the array substrate of second embodiment of the invention refering to Fig. 5.For and embodiment illustrated in fig. 4
Identical structural detail, the present embodiment use identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Driving circuit 21 further comprises being located at grid layer MlSeparate source layer M2The channel layer 122 of side and between grid layer Ml
Second insulating layer 123 between channel layer 122.Wherein, channel layer 122 is the polysilicon semiconductor of the heavy doping N+ of TFT 14
(polycrystalline silicon, P-Si) layer, second insulating layer 123 are gate insulating layer (Gate Insulation
Layer,GI)。
In the present embodiment, it is provided with and grid layer M in the first insulating layer 121 and second insulating layer 123lIt is spaced
Through-hole 124, source layer M2It is electrically connected via through-hole 124 with channel layer 122.Channel layer 122 and grid layer MlIt is least partially overlapped,
The channel layer 122 and grid layer M of laplBy being held on 123 insulation set of second insulating layer between the two, to be formed
Second capacitor Cst2.Second capacitor Cst2With first capacitor Cst1Parallel connection, the capacitor (C=C after parallel connectionst1+Cst2) it is greater than the first electricity
Hold Cst1, so as to increase the capacitor of GOA on the basis of the embodiment shown in fig. 4.Also, the second capacitor Cst2With first capacitor
Cst1To be superposed, it is compared to previous embodiment, the present embodiment will not increase area shared by capacitor, be conducive to liquid crystal
The narrow frame of display panel 10 and high PPI design.
It is the structure sectional view of the array substrate of third embodiment of the invention refering to Fig. 6.For and embodiment illustrated in fig. 5
Identical structural detail, the present embodiment use identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Driving circuit 21 further comprises the separate grid layer M positioned at channel layer 122lThe light shield layer M of side0And between channel layer 122
With light shield layer M0Between third insulating layer 125.
In the present embodiment, it is also equipped on second insulating layer 123 and third insulating layer 125 and is set with the interval of channel layer 122
The through-hole 124 set, grid layer MlVia through-hole 124 and light shield layer M0Electrical connection.Light shield layer M0It is at least partly heavy with channel layer 122
Folded setting, the light shield layer M of lap0Pass through the insulation of third insulating layer 125 being held between the two with channel layer 122 to set
It sets, to form third capacitor Cst3.Third capacitor Cst3With first capacitor Cst1With the second capacitor Cst2Parallel connection, the capacitor after parallel connection
(C=Cst1+Cst2+Cst3) it is greater than first capacitor Cst1, so as to further increase GOA on the basis of the embodiment shown in fig. 4
Capacitor.Also, third capacitor Cst3With first capacitor Cst1With the second capacitor Cst2To be superposed, it is compared to aforementioned implementation
Example, the present embodiment not will increase area shared by capacitor, be conducive to the narrow frame and high PPI design of liquid crystal display panel 10.
It is the structure sectional view of the array substrate of third embodiment of the invention refering to Fig. 7.For and embodiment illustrated in fig. 6
Identical structural detail, the present embodiment use identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Driving circuit 21 further comprises being located at source layer M2Separate grid layer M1The touch-control routing layer M of side3And between source layer
M2With touch-control routing layer M3Between the 4th insulating layer 126.
In the present embodiment, it is also equipped with and source layer M on the first insulating layer 121 and the 4th insulating layer 1262Interval setting
Through-hole 124, grid layer M1Via through-hole 124 and touch-control routing layer M3Electrical connection.Touch-control routing layer M3With source layer M2At least portion
Divide and overlaps, the touch-control routing layer M of lap3With source layer M2By being held on the 4th insulating layer 126 between the two absolutely
Edge setting, to form the 4th capacitor Cst4.4th capacitor Cst4With first capacitor Cst1, the second capacitor Cst2, third capacitor Cst3And
Connection, the capacitor (C=C after parallel connectionst1+Cst2+Cst3+Cst4) it is greater than first capacitor Cst1, so as to embodiment shown in Fig. 4
On the basis of further increase the capacitor of GOA.Also, the 4th capacitor Cst4With first capacitor Cst1, the second capacitor Cst2, third electricity
Hold Cst3To be superposed, it is compared to previous embodiment, the present embodiment will not increase area shared by capacitor, be conducive to liquid
The narrow frame of LCD panel 10 and high PPI design.
Above-mentioned Fig. 5~embodiment illustrated in fig. 6 can be considered that the gate driving circuit 21 of the embodiment of the present invention includes being stacked
Multiple conductive layers and the insulating layer between adjacent conductive layer, plurality of conductive layer be selected from by grid layer M1, source
Pole layer (or drain electrode layer) M2, light shield layer M0, channel layer 122 and touch-control routing layer M3At least three in composed group, it is more
A conductive layer is electrically connected at least two capacitors for being connected into and being connected in parallel to each other.
The embodiment of the present invention also provides a kind of liquid crystal display 80 as shown in Figure 8, which includes above-mentioned
Liquid crystal display panel 10 and the light source module group 81 of light is provided for liquid crystal display panel 10.Since the liquid crystal display 80 also has
There is the above-mentioned design of above-mentioned array substrate 12, therefore also beneficial effect having the same.
It is to be appreciated that the above description is only an embodiment of the present invention, it is not intended to limit the scope of the invention, it is all
It is special using technology between equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, such as each embodiment
Sign be combined with each other, and being applied directly or indirectly in other relevant technical fields, similarly includes protecting in patent of the invention
It protects in range.
Claims (7)
1. a kind of array substrate, which is characterized in that be formed with gate driving circuit, the gate driving electricity in the array substrate
Road includes grid layer, source/drain layer, the first insulating layer between the grid layer and the source/drain layer, is located at
The grid layer far from the source/drain layer side channel layer, between the grid layer and the channel layer
Second insulating layer, the light shield layer positioned at the channel layer far from the grid layer side and between the channel layer with it is described
Third insulating layer between light shield layer, wherein the grid layer and the source/drain layer are least partially overlapped, and then by institute
State grid layer and the source/drain layer form the gate driving circuit needed for first capacitor, the channel layer with it is described
Grid layer is least partially overlapped, and is electrically connected with the source/drain layer, and then is formed by the grid layer and the channel layer
Second capacitor in parallel with the first capacitor, the light shield layer and the least partially overlapped setting of the channel layer, and with it is described
Grid layer electrical connection, and then formed with the light shield layer by the channel layer in parallel with the first capacitor and second capacitor
Third capacitor.
2. array substrate according to claim 1, which is characterized in that on first insulating layer and the second insulating layer
It is provided with and is electrically connected with the spaced through-hole of the grid layer, the source/drain layer via the through-hole and the channel layer
It connects.
3. array substrate according to claim 1, which is characterized in that in the second insulating layer and the third insulating layer
It is provided with and is electrically connected via the through-hole with the light shield layer with the spaced through-hole of the channel layer, the grid layer.
4. array substrate according to claim 1, which is characterized in that the gate driving circuit further comprises being located at institute
State the touch-control routing layer of the separate grid layer side of source/drain layer and between the source/drain layer and the touching
The 4th insulating layer between routing layer is controlled, wherein touch-control routing layer and the least partially overlapped setting of the source/drain layer, and with
Grid layer electrical connection, and then formed and the first capacitor, described by the source/drain layer and the touch-control routing layer
Second capacitor, third capacitor parallel connection the 4th capacitor.
5. array substrate according to claim 4, which is characterized in that on first insulating layer and the 4th insulating layer
Be provided with the spaced through-hole of the source/drain layer, the grid layer is via the through-hole and the touch-control routing layer
Electrical connection.
6. array substrate according to claim 4, which is characterized in that the grid layer, the source/drain layer, described
Light shield layer and the touch-control routing layer are metal layer, and the channel layer is polysilicon layer.
7. a kind of liquid crystal display, which is characterized in that the liquid crystal display includes as claimed in any one of claims 1 to 6
Array substrate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610729146.9A CN106200167B (en) | 2016-08-25 | 2016-08-25 | Array substrate and liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610729146.9A CN106200167B (en) | 2016-08-25 | 2016-08-25 | Array substrate and liquid crystal display |
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| CN106200167A CN106200167A (en) | 2016-12-07 |
| CN106200167B true CN106200167B (en) | 2019-06-11 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107219660B (en) * | 2017-07-12 | 2020-09-25 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN107527599B (en) | 2017-08-16 | 2020-06-05 | 深圳市华星光电半导体显示技术有限公司 | Scanning driving circuit, array substrate and display panel |
| CN108020971A (en) | 2017-12-22 | 2018-05-11 | 武汉华星光电技术有限公司 | Array base palte, liquid crystal panel and liquid crystal display device |
| CN108761939A (en) * | 2018-05-28 | 2018-11-06 | 武汉华星光电技术有限公司 | Array substrate, display panel and display |
| US10690978B2 (en) | 2018-05-28 | 2020-06-23 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display |
| CN108766382A (en) * | 2018-06-06 | 2018-11-06 | 深圳市华星光电半导体显示技术有限公司 | Bootstrap capacitor, GOA circuits and the display panel of GOA circuits |
| CN108957884B (en) * | 2018-07-23 | 2021-07-27 | Tcl华星光电技术有限公司 | Array substrate, liquid crystal panel and manufacturing method of array substrate |
| CN111221162B (en) * | 2018-11-26 | 2022-11-04 | 群创光电股份有限公司 | electronic device |
| CN110568686A (en) * | 2019-08-08 | 2019-12-13 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113363300B (en) * | 2021-06-01 | 2022-08-23 | 霸州市云谷电子科技有限公司 | Array substrate and display panel |
| CN121464477A (en) * | 2024-05-30 | 2026-02-03 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
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| KR20130007065A (en) * | 2011-06-28 | 2013-01-18 | 삼성디스플레이 주식회사 | Thin film transistor, pixel and organic light emitting display device having the same |
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