CN106209064B - Low-power dynamic threshold comparator interface circuit and rectifier, wireless sensor - Google Patents

Abstract

The present invention relates to a kind of low-power consumption dynamic threshold comparator interface circuit and rectifiers, wireless sensor.The interface circuit includes: input terminal VIN, output end VAUX, first comparator circuit 11, the second comparator circuit 13, switching load circuit 15 and ground terminal GND；Second power switch MNS is electrically connected between input terminal VIN and ground terminal GND and its control terminal is electrically connected to the output end vo ut2 of the second comparator circuit 13；The non-inverting input terminal Vinp1 of first comparator circuit 11 is electrically connected to output end VAUX and inverting input terminal Vinn1 is electrically connected to input terminal VIN；The non-inverting input terminal Vinp2 of second comparator circuit 13 is electrically connected to ground terminal GND and inverting input terminal Vinn2 is electrically connected to input terminal VIN.The present invention is made of dynamic threshold comparator circuit and switching load circuit, and using dual comparator structure, whole design framework is simple, can effectively reduce operating voltage needed for circuit, reduces system power dissipation, is suitable for middle low-power consumption energy capturing systems.

Description

Low-power dynamic threshold comparator interface circuit and rectifier, wireless sensor

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a low-power consumption dynamic threshold comparator interface circuit, a rectifier, and a wireless sensor.

Background technique

Since most of the current wireless sensors use traditional batteries to supply energy, and the wireless sensors are small in size, the battery energy they carry is limited, which cannot meet the needs of long-term work. On the other hand, as the energy consumption of more and more micro-power products has been reduced to the level of microwatts, it has become possible for microelectronic devices to harvest energy from the environment and realize self-powered work.

As an emerging energy technology, micro-energy harvesting is especially suitable for contracts that require long-term monitoring, harsh working environments, and inconvenient battery replacement, such as pressure monitoring in automobile tires, structural health testing of aircraft and ships, and health of train wheel and rail bearings. Global positioning devices for detecting and tracking wild animals, biomedical portable or implantable health equipment applications, etc., are one of the research hotspots in the field of new power generation. The power density of ^cm3 . Therefore, harvesting micro-energy to power low-power devices has a good application prospect. Its principle is to use a series of energy harvesting technologies to collect and convert micro-energy in the environment into electrical energy for storage, so as to provide the energy required for low-power electronic devices to work. As an important means of saving energy and protecting the environment, people have been in many In this field, research and application of micro-energy harvesting technology have been carried out. Since the micro-energy collection is generally alternating current, in the actual circuit, a rectifier must be used to convert the alternating current into direct current, and then charge the energy storage elements such as supercapacitors or rechargeable batteries for use by the load.

The interface circuit of the rectifier is the core unit in the micro-energy acquisition technology. The load converts the collected micro-energy from a small AC signal into a DC signal that can be used directly. It must meet the low-voltage working conditions and be able to provide a large enough output. The voltage is used to maximize the energy obtained and provide working energy for low-voltage equipment, and at the same time, the energy consumed by itself should be as small as possible.

Therefore, how to design a low-power dynamic threshold comparator interface circuit for micro-energy harvesting becomes extremely important.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a low power consumption dynamic threshold comparator interface circuit, a rectifier, and a wireless sensor. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides a low-power dynamic threshold comparator interface circuit 10, including: an input terminal VIN, an output terminal VAUX, a first comparator circuit 11, a second comparator circuit 13, a switch load circuit 15 and Ground terminal GND; among them,

The switch load circuit 15 includes a first power switch MPS, a second power switch MNS, a load capacitor CL and a load resistor RLOAD, the first power switch MPS is electrically connected between the input terminal VIN and the output terminal VAUX And its control terminal is electrically connected to the output terminal Vout1 of the first comparator circuit 11, the load capacitor CL and the load resistor RLOAD are connected in parallel and then connected in series between the output terminal VAUX and the ground terminal GND, so the second power switch MNS is electrically connected between the input terminal VIN and the ground terminal GND and its control terminal is electrically connected to the output terminal Vout2 of the second comparator circuit 13;

The non-inverting input terminal Vinp1 of the first comparator circuit 11 is electrically connected to the output terminal VAUX and the inverting input terminal Vinn1 is electrically connected to the input terminal VIN;

The non-inverting input terminal Vinp2 of the second comparator circuit 13 is electrically connected to the ground terminal GND and the inverting input terminal Vinn2 is electrically connected to the input terminal VIN.

In an embodiment of the present invention, the first comparator circuit 11 includes a power supply terminal VDD, a first positive voltage switch P1, a second positive voltage switch P2, a third positive voltage switch P3, a fourth positive voltage switch P4, The fifth positive pressure switch P5, the first negative pressure switch N1, the second negative pressure switch N2, the third negative pressure switch N3, and the fourth negative pressure switch N4; wherein,

The first positive pressure switch P1, the first negative pressure switch N1 and the third negative pressure switch N3 are connected in series and are electrically connected between the power terminal VDD and the ground terminal GND; the second The positive pressure switch P2 and the second negative pressure switch N2 are connected in series and are electrically connected to the power supply terminal VDD and the node a1 formed by the series connection of the first negative pressure switch N1 and the third negative pressure switch N3. the control terminal of the first positive pressure switch P1 is electrically connected to the control terminal of the second positive pressure switch P2; the control terminals of the first negative pressure switch N1 and the third negative pressure switch N3 are both electrically connected connected to the inverting input terminal Vinn1 of the first comparator circuit 11 ; the control terminal of the second negative pressure switch N2 is electrically connected to the non-inverting input terminal Vinp1 of the first comparator circuit 11 ;

The third positive pressure switch P3 and the fourth positive pressure switch P4 are connected in series and are electrically connected to the power supply terminal VDD and the second positive pressure switch P2 and the second negative pressure switch N2 are connected in series. between nodes b1; the control terminals of the third positive pressure switch P3 and the fourth positive pressure switch P4 are electrically connected to the second positive pressure switch P2 and the second negative pressure switch N2 in series to form at node b1 of ;

The fifth positive pressure switch P5 and the fourth negative pressure switch N4 are connected in series and are electrically connected between the power supply terminal VDD and the ground terminal GND, and the fifth positive pressure switch P5 and the fourth The control terminals of the negative pressure switch N4 are all electrically connected to the inverting input terminal Vinn1 of the first comparator circuit 11;

The output terminal Vout1 of the first comparator circuit 11 is electrically connected to the node formed by the series connection of the third positive voltage switch P3 and the fourth positive voltage switch P4, and the fifth positive voltage switch P5 and the The fourth negative pressure switch N4 is connected in series to form the node.

In an embodiment of the present invention, the second comparator circuit 13 includes a power supply terminal VDD, a sixth positive voltage switch P6, a seventh positive voltage switch P7, an eighth positive voltage switch P8, a ninth positive voltage switch P9, The tenth positive pressure switch P10, the fifth negative pressure switch N5, the sixth negative pressure switch N6, the seventh negative pressure switch N7, and the eighth negative pressure switch N8; wherein,

The sixth positive pressure switch P6, the fifth negative pressure switch N5 and the seventh negative pressure switch N7 are connected in series and are electrically connected between the power supply terminal VDD and the ground terminal GND; the seventh negative pressure switch N7 The positive pressure switch P7 and the sixth negative pressure switch N6 are connected in series and are electrically connected to the power supply terminal VDD and the node a2 formed by the series connection of the fifth negative pressure switch N5 and the seventh negative pressure switch N7. the control terminal of the sixth positive pressure switch P6 is electrically connected to the control terminal of the seventh positive pressure switch P7; the control terminals of the fifth negative pressure switch N5 and the seventh negative pressure switch N7 are both electrically connected connected to the inverting input terminal Vinn2 of the second comparator circuit 13; the control terminal of the sixth negative pressure switch N6 is electrically connected to the non-inverting input terminal Vinp2 of the second comparator circuit 13;

The eighth positive pressure switch P8 and the ninth positive pressure switch P9 are connected in series and are electrically connected to the power supply terminal VDD and the seventh positive pressure switch P7 and the sixth negative pressure switch N6 are connected in series. between nodes b2; the control terminals of the eighth positive pressure switch P8 and the ninth positive pressure switch P9 are electrically connected to the seventh positive pressure switch P7 and the sixth negative pressure switch N6 in series to form at node b2 of ;

The tenth positive voltage switch P10 and the eighth negative voltage switch N8 are connected in series and are electrically connected between the power supply terminal VDD and the ground terminal GND, and the tenth positive voltage switch P10 is connected to the eighth negative voltage switch N8. The control terminals of the negative pressure switch N8 are all electrically connected to the inverting input terminal Vinn2 of the second comparator circuit 13;

The output terminal Vout2 of the second comparator circuit 13 is electrically connected to the node formed by the eighth positive voltage switch P8 and the ninth positive voltage switch P9 connected in series, and the tenth positive voltage switch P10 and the The eighth negative pressure switch N8 is connected in series to form the node.

In an embodiment of the present invention, the first positive pressure switch P1, the second positive pressure switch P2, the third positive pressure switch P3, the fourth positive pressure switch P4, and the fifth positive pressure switch The pressure switch P5, the sixth positive pressure switch P6, the seventh positive pressure switch P7, the eighth positive pressure switch P8, the ninth positive pressure switch P9 and the tenth positive pressure switch P10 are all PMOS tube, and its control terminal is the gate of the PMOS tube.

In an embodiment of the present invention, the first negative pressure switch N1, the second negative pressure switch N2, the third negative pressure switch N3, the fourth negative pressure switch N4, and the fifth negative pressure switch The pressure switch N5, the sixth negative pressure switch N6, the seventh negative pressure switch N7, and the eighth negative pressure switch N8 are all NMOS transistors, and their control terminals are all gates of the NMOS transistors.

In an embodiment of the present invention, the first power switch MPS is a PMOS transistor and its control terminal is the gate of the PMOS transistor, and the second power switch MNS is an NMOS transistor and its control terminal is the gate of the NMOS transistor .

Another embodiment of the present invention provides a rectifier, including the interface circuit 10 described in any one of the foregoing embodiments.

Yet another embodiment of the present invention provides a wireless sensor including a rectifier, wherein the rectifier includes the interface circuit 10 described in any one of the above embodiments.

Compared with the prior art, the beneficial effects of the present invention:

1. In the dynamic threshold comparator interface circuit for micro-energy acquisition of the present invention, a dual-comparator structure is adopted, and each comparator is implemented by a dynamic threshold MOS, the structure is simple, and the use of DTMOS tube makes the MOS tube in the conduction state. In the off state, the threshold voltage is reduced, that is, the requirement for the gate-source voltage is reduced, so it has a lower operating voltage; while in the off state, the threshold voltage is increased, which reduces the leakage current, so it has lower power consumption ;

2. The dynamic threshold comparator interface circuit for micro-energy acquisition of the present invention obtains the output states of the dynamic threshold comparator 1 and comparator 2 according to the size comparison between VIN and VAUX, and then controls the power switch MPS and the power switch MNS. Disconnection and conduction improve the noise tolerance of the interface circuit, eliminate the oscillation phenomenon near the zero-crossing point, reduce the problem of zero-crossing distortion, improve the limit of harmonic current and frequency on the system, and improve the system stability.

Description of drawings

1 is a schematic diagram of a circuit structure of a low-power dynamic threshold comparator interface circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a circuit structure of a first comparator circuit according to an embodiment of the present invention;

3 is a schematic diagram of a circuit structure of a second comparator circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a circuit structure of a switch load circuit according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1:

Please refer to FIG. 1 and FIG. 4. FIG. 1 is a schematic diagram of a circuit structure of a low-power dynamic threshold comparator interface circuit provided by an embodiment of the present invention; FIG. 4 is a circuit structure of a switch load circuit provided by an embodiment of the present invention. Schematic. The low-power dynamic threshold comparator interface circuit 10 includes: an input terminal VIN, an output terminal VAUX, a first comparator circuit 11, a second comparator circuit 13, a switch load circuit 15 and a ground terminal GND; wherein the switch The load circuit 15 includes a first power switch MPS, a second power switch MNS, a load capacitor CL and a load resistor RLOAD, the first power switch MPS is electrically connected between the input terminal VIN and the output terminal VAUX and controls the The terminal is electrically connected to the output terminal Vout1 of the first comparator circuit 11, the load capacitor CL and the load resistor RLOAD are connected in parallel and connected in series between the output terminal VAUX and the ground terminal GND, the second The power switch MNS is electrically connected between the input terminal VIN and the ground terminal GND and its control terminal is electrically connected to the output terminal Vout2 of the second comparator circuit 13 ; the non-inverting input of the first comparator circuit 11 The terminal Vinp1 is electrically connected to the output terminal VAUX and the inverting input terminal Vinn1 is electrically connected to the input terminal VIN; the non-inverting input terminal Vinp2 of the second comparator circuit 13 is electrically connected to the ground terminal GND and is inverting input The terminal Vinn2 is electrically connected to the input terminal VIN.

Specifically, please refer to FIG. 2 , which is a schematic diagram of a circuit structure of a first comparator circuit according to an embodiment of the present invention. The first comparator circuit 11 includes a power supply terminal VDD, a first positive voltage switch P1, a second positive voltage switch P2, a third positive voltage switch P3, a fourth positive voltage switch P4, a fifth positive voltage switch P5, a first Negative pressure switch N1, second negative pressure switch N2, third negative pressure switch N3, fourth negative pressure switch N4; wherein, the first positive pressure switch P1, the first negative pressure switch N1 and the third negative pressure switch N1 The negative pressure switch N3 is connected in series and is electrically connected between the power supply terminal VDD and the ground terminal GND; the second positive pressure switch P2 and the second negative pressure switch N2 are connected in series and electrically connected to the power supply between the terminal VDD and the node a1 formed by the series connection of the first negative pressure switch N1 and the third negative pressure switch N3; the control terminal of the first positive pressure switch P1 is electrically connected to the second positive pressure The control terminal of the switch P2; the control terminals of the first negative pressure switch N1 and the third negative pressure switch N3 are both electrically connected to the inverting input terminal Vinn1 of the first comparator circuit 11; the second negative pressure switch The control terminal of the voltage switch N2 is electrically connected to the non-inverting input terminal Vinp1 of the first comparator circuit 11; the third positive voltage switch P3 and the fourth positive voltage switch P4 are connected in series and are electrically connected to the power supply terminal Between VDD and the node b1 formed by the series connection of the second positive pressure switch P2 and the second negative pressure switch N2; the control terminals of the third positive pressure switch P3 and the fourth positive pressure switch P4 are both It is electrically connected to the node b1 formed by the series connection of the second positive pressure switch P2 and the second negative pressure switch N2; the fifth positive pressure switch P5 and the fourth negative pressure switch N4 are connected in series and then electrically connected Between the power supply terminal VDD and the ground terminal GND, the control terminals of the fifth positive voltage switch P5 and the fourth negative voltage switch N4 are electrically connected to the inverting phase of the first comparator circuit 11 . The input terminal Vinn1; the output terminal Vout1 of the first comparator circuit 11 is electrically connected to the node formed by the series connection of the third positive voltage switch P3 and the fourth positive voltage switch P4 and the fifth positive voltage respectively The switch P5 and the fourth negative pressure switch N4 are connected in series to form a node.

Specifically, please refer to FIG. 3 , which is a schematic diagram of a circuit structure of a second comparator circuit according to an embodiment of the present invention. The second comparator circuit 13 includes a power supply terminal VDD, a sixth positive pressure switch P6, a seventh positive pressure switch P7, an eighth positive pressure switch P8, a ninth positive pressure switch P9, a tenth positive pressure switch P10, a fifth positive pressure switch Negative pressure switch N5, sixth negative pressure switch N6, seventh negative pressure switch N7, eighth negative pressure switch N8; wherein, the sixth positive pressure switch P6, the fifth negative pressure switch N5 and the seventh negative pressure switch N8 The negative pressure switch N7 is connected in series and is electrically connected between the power supply terminal VDD and the ground terminal GND; the seventh positive pressure switch P7 and the sixth negative pressure switch N6 are electrically connected to the power supply after being connected in series between the terminal VDD and the node a2 formed by the series connection of the fifth negative pressure switch N5 and the seventh negative pressure switch N7; the control terminal of the sixth positive pressure switch P6 is electrically connected to the seventh positive pressure The control terminal of the switch P7; the control terminals of the fifth negative pressure switch N5 and the seventh negative pressure switch N7 are electrically connected to the inverting input terminal Vinn2 of the second comparator circuit 13; the sixth negative pressure switch N7 The control terminal of the voltage switch N6 is electrically connected to the non-inverting input terminal Vinp2 of the second comparator circuit 13; the eighth positive voltage switch P8 and the ninth positive voltage switch P9 are connected in series and are electrically connected to the power supply terminal between VDD and the node b2 formed by the series connection of the seventh positive pressure switch P7 and the sixth negative pressure switch N6; the control terminals of the eighth positive pressure switch P8 and the ninth positive pressure switch P9 are both It is electrically connected to the node b2 formed by the series connection of the seventh positive pressure switch P7 and the sixth negative pressure switch N6; the tenth positive pressure switch P10 and the eighth negative pressure switch N8 are connected in series and then electrically connected Between the power supply terminal VDD and the ground terminal GND, the control terminals of the tenth positive voltage switch P10 and the eighth negative voltage switch N8 are both electrically connected to the inverting phase of the second comparator circuit 13 . The input terminal Vinn2; the output terminal Vout2 of the second comparator circuit 13 is electrically connected to the node formed by the series connection of the eighth positive voltage switch P8 and the ninth positive voltage switch P9 and the tenth positive voltage respectively The switch P10 and the eighth negative pressure switch N8 are connected in series to form a node.

Optionally, the first positive pressure switch P1, the second positive pressure switch P2, the third positive pressure switch P3, the fourth positive pressure switch P4, the fifth positive pressure switch P5, the The sixth positive pressure switch P6, the seventh positive pressure switch P7, the eighth positive pressure switch P8, the ninth positive pressure switch P9 and the tenth positive pressure switch P10 can all be PMOS transistors, and The control terminals are the gates of the PMOS transistors.

In addition, the first negative pressure switch N1, the second negative pressure switch N2, the third negative pressure switch N3, the fourth negative pressure switch N4, the fifth negative pressure switch N5, the sixth negative pressure switch The pressure switch N6, the seventh negative pressure switch N7, and the eighth negative pressure switch N8 can all be NMOS transistors, and their control terminals are all gates of the NMOS transistors.

Optionally, the first power switch MPS may be a PMOS transistor and its control terminal may be the gate of the PMOS transistor, and the second power switch MNS may be an NMOS transistor and its control terminal may be the gate of the NMOS transistor.

This embodiment is composed of a dynamic threshold comparator circuit and a switch load circuit, adopts a dual comparator structure, and has a simple overall design architecture, which can effectively reduce the operating voltage required by the circuit, reduce system power consumption, and is suitable for medium and low power consumption energy. Get the system. In the interface circuit, when VIN is greater than VAUX, the outputs of the dynamic threshold comparator 1 and comparator 2 are both low, the switch MPS is turned on, and the switch MNS is turned off. The input charges the load capacitance through the switch MPS and provides the output; when VIN is less than VAUX, the output of the comparator 1 is high, and the switch MPS is disconnected. Comparator 2 can occur in two cases:

1) When VIN is greater than zero, the output of comparator 2 is still low, MNS is disconnected, and CL discharges the load resistance to provide output;

2) When VIN is less than zero, the output of comparator 2 becomes high, the switch MNS is turned on, and the input VIN is connected to GND, which improves the noise tolerance of the interface circuit, eliminates the oscillation phenomenon near the zero-crossing point, and reduces the zero-crossing Distortion problem, improve the limitation of harmonic current and frequency on the system, and improve system stability.

Example 2:

Referring to FIGS. 1 to 4 again, this embodiment will describe in detail the low-power dynamic threshold comparator interface circuit 10 of the present invention on the basis of the above-mentioned embodiments. details as follows:

1. The dynamic threshold comparator 1 is the first comparator circuit 11

Please refer to Figure 2, which is mainly composed of five PMOS transistors P1, P2, P3, P4, and P5 and four NMOS transistors N1, N2, N3, and N4.

The source terminal of P1 is connected to the power supply voltage VDD, the drain terminal of P1 is connected to the drain terminal of N1, the gate terminal of P1 is connected to the substrate of P1, the gate terminal of P2, and the substrate of P2, and the substrate of P1 is connected to the gate terminal of P1 The gate terminal of P2 and the substrate of P2 are connected;

The source terminal of P2 is connected to the power supply voltage VDD, the drain terminal of P2 is connected to the drain terminal of N2, the gate terminal of P3, the substrate of P3, the drain terminal of P4, the gate terminal of P4 and the substrate of P4, and the gate terminal of P2 is connected. Connect to the gate terminal of P1, the substrate of P1, and the substrate of P2, and the substrate of P2 is connected to the gate terminal of P1, the substrate of P1, and the gate terminal of P2;

The source terminal of P3 is connected to the power supply voltage VDD, the drain terminal of P3 is connected to the source terminal of P4, the drain terminal of P5, the drain terminal of N4 and the output terminal Vout1, the gate terminal of P3 is connected to the drain terminal of P2, the drain terminal of N2, The substrate of P3, the drain terminal of P4, the gate terminal of P4, and the substrate of P4 are connected. The substrate of P3 is connected to the drain terminal of P2, the gate terminal of P3, the drain terminal of P4, the gate terminal of P4, and the substrate of P4. , the drain of N2 is connected;

The source terminal of P4 is connected to the drain terminal of P3, the drain terminal of P5, the drain terminal of N4, and the output terminal Vout1, and the drain terminal of P4 is connected to the gate terminal of P3, the substrate of P3, the gate terminal of P4, and the substrate of P4. , the gate terminal of P4 is connected to the gate terminal of P3, the substrate of P3, the drain terminal of P4, and the substrate of P4, and the substrate of P4 is connected to the gate terminal of P3, the substrate of P3, the drain terminal of P4, and the gate of P4. end connected;

The source terminal of P5 is connected to the power supply voltage VDD, the drain terminal of P5 is connected to the drain terminal of P3, the source terminal of P4, the drain terminal of N4 and the output terminal Vout1, the gate terminal of P5 is connected to the substrate of P5, the gate terminal of N1, The substrate of N1, the gate terminal of N3, the substrate of N3, the gate terminal of N4, the substrate of N4, the inverting input terminal Vinn1 are connected; the substrate of P5 is connected to the gate terminal of P5, the gate terminal of N1, the substrate of N1 The bottom, the gate terminal of N3, the substrate of N3, the gate terminal of N4, the substrate of N4, and the inverting input terminal Vinn1 are connected;

The source terminal of N1 is connected to the source terminal of N2 and the drain terminal of N3, the drain terminal of N1 is connected to the drain terminal of P1, the gate terminal of N1 is connected to the substrate of N1, the gate terminal of N3, the substrate of N3 and the gate of N4 Terminal, N4 substrate, P5 gate terminal, P5 substrate, reverse input terminal Vinn1 connected, N1 substrate is connected to N1 gate terminal, N3 gate terminal, N3 substrate, N4 gate terminal, N4 The substrate, the gate terminal of P5, the substrate of P5, and the inverting input terminal Vinn1 are connected;

The source terminal of N2 is connected to the source terminal of N1 and the drain terminal of N3, the drain terminal of N2 is connected to the drain terminal of P2, the gate terminal of P3, the substrate of P3, the gate terminal of P4, the drain terminal of P4, the substrate of P4 connected, the gate terminal of N2 is connected to the substrate of N2 and the non-inverting input terminal Vinp1, and the substrate of N2 is connected to the gate terminal of N2 and the non-inverting input terminal Vinp1;

The source terminal of N3 is connected to the ground, the drain terminal of N3 is connected to the source terminal of N1 and the source terminal of N2, the gate terminal of N3 is connected to the substrate of N3, the gate terminal of N1, the substrate of N1, the gate terminal of N4, and the gate terminal of N4. The substrate, the gate terminal of P5, the substrate of P5, the inverting input terminal Vinn1 are connected, the substrate of N3 is connected to the gate terminal of N3, the gate terminal of N1, the substrate of N1, the gate terminal of N4, the substrate of N4 , the gate terminal of P5, the substrate of P5, and the inverting input terminal Vinn1 are connected;

The source terminal of N4 is connected to the ground, the drain terminal of N4 is connected to the drain terminal of P3, the source terminal of P4, the drain terminal of P5, and the output terminal Vout1, the gate terminal of N4 is connected to the gate terminal of N1, the substrate of N1, and the output terminal of N3. The gate terminal, the substrate of N3, the substrate of N4, the gate terminal of P5, the substrate of P5, the inverting input terminal Vinn1 are connected, the substrate of N4 is connected to the gate terminal of N1, the substrate of N1, the gate terminal of N3, The substrate of N3, the gate terminal of N4, the gate terminal of P5, the substrate of P5, and the inverting input terminal Vinn1 are connected.

As can be seen from Figure 2, the working principle of the dynamic threshold comparator 1 is as follows:

When Vinn1 is greater than Vinp1, that is, VIN is greater than VAUX, the MPS should be turned on, and the difference between (Vinn1-Vinp1), that is, (VIN-VAUX), determines the size of Vb1. The larger the (Vinn1-Vinp1) is, the larger the Vb1 is, the more difficult it is for P3 to conduct, the closer Vout1 is to GND, that is, strong zero, the MPS conduction degree increases, the current increases, and the CL charging speed is accelerated; (Vinn1-Vinp1) The more Small, the smaller Vb1 is, when Vb1 turns on P3, Vout1 depends on the size ratio of P3 and N4, the output of Vout1 is weak zero, the MPS conduction degree is small, and the CL charging current is small; in the whole working process, P4 always acts as a reverse bias The diode isolates Vout1 and Vb1, improves the noise tolerance, the load capacity of the comparator, reduces the quiescent current, and reduces the power consumption; when Vinn1 is less than Vinp1, that is, VIN is less than VAUX, MPS should be disconnected, (Vinp1 -Vinn1) difference, that is (VAUX-VIN), determines the size of Vb1.

2. The dynamic threshold comparator 2 is the first comparator circuit 13

Please refer to Figure 3, which is mainly composed of five PMOS transistors P6, P7, P8, P9, and P10 and four NMOS transistors N5, N6, N7, and N8.

The source terminal of P6 is connected to the power supply voltage VDD, the drain terminal of P6 is connected to the drain terminal of N5, the gate terminal of P6 is connected to the substrate of P6, the gate terminal of P7, and the substrate of P7, and the substrate of P6 is connected to the gate terminal of P6 The gate terminal of P7 and the substrate of P7 are connected;

The source terminal of P7 is connected to the power supply voltage VDD, the drain terminal of P7 is connected to the drain terminal of N6, the gate terminal of P8, the substrate of P8, the drain terminal of P9, the gate terminal of P9, the substrate of P9, and the gate terminal of P7. Connect to the gate terminal of P6, the substrate of P6, and the substrate of P7, and the substrate of P7 is connected to the gate terminal of P6, the substrate of P6, and the gate terminal of P7;

The source terminal of P8 is connected to the power supply voltage VDD, the drain terminal of P8 is connected to the source terminal of P9, the drain terminal of P10, the drain terminal of N8 and the output terminal Vout2, the gate terminal of P8 is connected to the drain terminal of P7, the drain terminal of N6, The substrate of P8, the drain terminal of P9, the gate terminal of P9, and the substrate of P9 are connected. The substrate of P8 is connected to the drain terminal of P7, the gate terminal of P8, the drain terminal of P9, the gate terminal of P9, and the substrate of P9. , the drain terminal of N6 is connected;

The source terminal of P9 is connected to the drain terminal of P8, the drain terminal of P10, the drain terminal of N8, and the output terminal Vout2, and the drain terminal of P9 is connected to the gate terminal of P8, the substrate of P8, the gate terminal of P9, and the substrate of P9. , the gate terminal of P9 is connected to the gate terminal of P8, the substrate of P8, the drain terminal of P9, and the substrate of P9, and the substrate of P9 is connected to the gate terminal of P8, the substrate of P8, the drain terminal of P9, the gate of P9 end connected;

The source terminal of P10 is connected to the power supply voltage VDD, the drain terminal of P10 is connected to the drain terminal of P8, the source terminal of P9, the drain terminal of N8 and the output terminal Vout2, the gate terminal of P10 is connected to the substrate of P10, the gate terminal of N5, The substrate of N5, the gate terminal of N7, the substrate of N7, the gate terminal of N8, the substrate of N8, the inverting input terminal Vinn2 are connected; the substrate of P10 is connected to the gate terminal of P10, the gate terminal of N5, the substrate of N5 The bottom, the gate terminal of N7, the substrate of N7, the gate terminal of N8, the substrate of N8, and the inverting input terminal Vinn2 are connected;

The source terminal of N5 is connected to the source terminal of N6 and the drain terminal of N7, the drain terminal of N5 is connected to the drain terminal of P6, the gate terminal of N5 is connected to the substrate of N5, the gate terminal of N7, the substrate of N7 and the gate of N8 Terminal, N8 substrate, P10 gate terminal, P10 substrate, reverse input terminal Vinn2 connected, N5 substrate is connected to N5 gate terminal, N7 gate terminal, N7 substrate, N8 gate terminal, N8 The substrate, the gate terminal of P10, the substrate of P10, and the inverting input terminal Vinn2 are connected;

The source terminal of N6 is connected to the source terminal of N5 and the drain terminal of N7, the drain terminal of N6 is connected to the drain terminal of P7, the gate terminal of P8, the substrate of P8, the gate terminal of P9, the drain terminal of P9, the substrate of P9 connected, the gate terminal of N6 is connected to the substrate of N6 and the non-inverting input terminal Vinp2, and the substrate of N6 is connected to the gate terminal of N6 and the non-inverting input terminal Vinp2;

The source terminal of N7 is connected to the ground, the drain terminal of N7 is connected to the source terminal of N5 and the source terminal of N6, the gate terminal of N7 is connected to the substrate of N7, the gate terminal of N5, the substrate of N5, the gate terminal of N8, and the gate terminal of N8. The substrate of P10, the gate terminal of P10, the substrate of P10, the inverting input terminal Vinn2 are connected, the substrate of N7 is connected to the gate terminal of N7, the gate terminal of N5, the substrate of N5, the gate terminal of N8, the substrate of N8 , The gate terminal of P10, the substrate of P10, and the inverting input terminal Vinn2 are connected;

The source terminal of N8 is connected to the ground, the drain terminal of N8 is connected to the drain terminal of P8, the source terminal of P9, the drain terminal of P10, and the output terminal Vout2, the gate terminal of N8 is connected to the gate terminal of N5, the substrate of N5, and the terminal of N7. The gate terminal, the substrate of N7, the substrate of N8, the gate terminal of P10, the substrate of P10, the inverting input terminal Vinn2 are connected, the substrate of N8 is connected to the gate terminal of N5, the substrate of N5, the gate terminal of N7, The substrate of N7, the gate terminal of N8, the gate terminal of P10, the substrate of P10, and the inverting input terminal Vinn2 are connected;

Combined with Figure 1 and Figure 3, the working principle and implementation function of the dynamic threshold comparator 2 are as follows:

When VIN is greater than VAUX, the outputs of Comparator 1 and Comparator 2 are both low, MPS is turned on, and MNS is turned off. The input charges the load capacitance through the MPS and provides the output. When VIN is less than VAUX, the output of Comparator 1 is high and MPS is turned off. Two situations may occur in Comparator 2: 1) VIN is greater than zero, the output of Comparator 2 is still low, MNS is disconnected, CL discharges the load resistor to provide the output; 2) VIN is less than zero (VIN is usually caused by the bridge rectifier circuit. come, convert the AC signal into a half-wave signal, there is oscillation near the zero-crossing point of the input voltage, a negative value may appear, which can be considered as a noise signal, causing circuit instability), the output of comparator 2 becomes high, MNS Turn on, connect the input VIN to GND, improve the noise tolerance of the rectifier, eliminate the oscillation phenomenon near the zero-crossing point, reduce the problem of zero-crossing distortion, improve the limitation of harmonic current and frequency on the system, and improve the system stability .

3. Switch load circuit

Referring to Figure 4, it is mainly composed of a PMOS switch MPS, an NMOS switch MNS, a load capacitor CL and a load resistor RLOAD.

The source terminal of MPS is connected to the gate terminal of N1, the substrate of N1, the gate terminal of N3, the substrate of N3, the gate terminal of N4, the substrate of N4, the gate terminal of P5, the substrate of P5, the inverting input terminal Vinn1, MNS drain terminal, N5 gate terminal and N5 substrate, N7 gate terminal, N7 substrate, N8 gate terminal, N8 substrate, P10 gate terminal, P10 substrate, reverse input The terminal Vinn2 is commonly connected to the input terminal VIN of the interface circuit, the drain terminal of the MPS and the gate terminal of N2, the substrate of N2, the non-inverting input terminal Vinp1, one end of CL, and one end of RLOAD are jointly connected to the interface circuit output terminal VAUX, and the gate of MPS The terminal is connected to the drain terminal of N4, the drain terminal of P3, the source terminal of P4, the drain terminal of P5, and the output terminal Vout1, and the substrate of MPS is connected to the power supply VDD;

The source terminal of MNS, the gate terminal of N6 and the substrate of N6, the non-inverting input terminal Vinp2, one end of CL, and one end of RLOAD are connected to the ground in common. Bottom, gate terminal of N3, substrate of N3, gate terminal of N4, substrate of N4, gate terminal of P5, substrate of P5, inverting input terminal Vinn1, gate terminal of N5 and substrate of N5, substrate of N7 The gate terminal, the substrate of N7, the gate terminal of N8, the substrate of N8, the gate terminal of P10, the substrate of P10 and the reverse input terminal Vinn2 are commonly connected to the input terminal VIN of the interface circuit, the gate terminal of MNS and the drain of N8 terminal, the drain terminal of P8, the source terminal of P9, the drain terminal of P10, and the output terminal Vout2 are connected, and the substrate of MNS is connected to the ground;

One end of CL and one end of RLOAD, the drain end of MPS, the gate end of N2, the substrate of N2, and the non-inverting input Vinp1 are connected to the output end VAUX of the interface circuit, and the other end of CL is connected with the other end of RLOAD and the source end of MNS. , the gate terminal of N6, the substrate of N6, and the non-inverting input terminal Vinp2 are connected to the ground together;

One end of RLOAD and one end of CL, the drain end of MPS, the gate end of N2, the substrate of N2, the non-inverting input end Vinp1 are connected to the output end VAUX of the interface circuit, the other end of RLOAD and the other end of CL, the source of MNS The terminal, the gate terminal of N6, the substrate of N6, and the non-inverting input terminal Vinp2 are commonly connected to the ground.

By cross-connecting with dual dynamic threshold comparators, the switching load circuit obtains a good load driving capability without consuming excessive power consumption itself.

It can be seen that the dynamic threshold comparator interface circuit for micro-energy acquisition of the present invention not only has lower power consumption, but also has higher noise tolerance and system stability. works fine.

Example 3:

The invention also provides a rectifier and a wireless sensor. The components of the wireless sensor are packaged in a housing that includes a rectifier. The rectifier is a rectifying device whose main function is to convert alternating current (AC) into direct current (DC), and after filtering, charge energy storage elements such as supercapacitors or rechargeable batteries for use by loads. The rectifier of the present invention may include The low power consumption dynamic threshold comparator interface circuit 10 in the above embodiment.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (7)

1. A low power dynamic threshold comparator interface circuit (10), comprising: an input terminal (VIN), an output terminal (VAUX), a first comparator circuit (11), a second comparator circuit (13), a switch load circuit (15) and a ground terminal (GND); wherein,

the switch load circuit (15) comprises a first power switch (MPS), a second power switch (MNS), a load Capacitor (CL) and a load Resistor (RLOAD), wherein the first power switch (MPS) is electrically connected between the input terminal (VIN) and the output terminal (VAUX) and has a control terminal electrically connected to the output terminal (Vout1) of the first comparator circuit (11), the load Capacitor (CL) and the load Resistor (RLOAD) are connected in parallel and then connected in series between the output terminal (VAUX) and the ground terminal (GND), the second power switch (MNS) is electrically connected between the input terminal (VIN) and the ground terminal (GND) and has a control terminal electrically connected to the output terminal (Vout2) of the second comparator circuit (13);

a non-inverting input (Vinp1) of the first comparator circuit (11) is electrically connected to the output (VAUX) and an inverting input (Vinn1) is electrically connected to the input (VIN); the first comparator circuit (11) comprises a power supply end (VDD), a first positive voltage switch (P1), a second positive voltage switch (P2), a third positive voltage switch (P3), a fourth positive voltage switch (P4), a fifth positive voltage switch (P5), a first negative voltage switch (N1), a second negative voltage switch (N2), a third negative voltage switch (N3) and a fourth negative voltage switch (N4); wherein,

the first positive voltage switch (P1), the first negative voltage switch (N1) and the third negative voltage switch (N3) are electrically connected between the power supply terminal (VDD) and the ground terminal (GND) after being connected in series; the second positive voltage switch (P2) is connected in series with the second negative voltage switch (N2) and then is electrically connected between the power supply terminal (VDD) and a node (a1) formed by connecting the first negative voltage switch (N1) and the third negative voltage switch (N3) in series; the control terminal of the first positive pressure switch (P1) is electrically connected to the control terminal of the second positive pressure switch (P2); the control terminals of the first negative voltage switch (N1) and the third negative voltage switch (N3) are electrically connected to the inverting input terminal (Vinn1) of the first comparator circuit (11); the control terminal of the second negative voltage switch (N2) is electrically connected to the non-inverting input terminal (Vinp1) of the first comparator circuit (11);

the third positive voltage switch (P3) and the fourth positive voltage switch (P4) are connected in series and then are electrically connected between the power supply terminal (VDD) and a node (b1) formed by connecting the second positive voltage switch (P2) and the second negative voltage switch (N2) in series; the control ends of the third positive voltage switch (P3) and the fourth positive voltage switch (P4) are electrically connected to a node (b1) formed by the second positive voltage switch (P2) and the second negative voltage switch (N2) in series;

the fifth positive voltage switch (P5) and the fourth negative voltage switch (N4) are connected in series and then electrically connected between the power terminal (VDD) and the ground terminal (GND), and the control terminals of the fifth positive voltage switch (P5) and the fourth negative voltage switch (N4) are electrically connected to the inverting input terminal (Vinn1) of the first comparator circuit (11);

an output end (Vout1) of the first comparator circuit (11) is electrically connected to a node formed by the third positive voltage switch (P3) and the fourth positive voltage switch (P4) in series and a node formed by the fifth positive voltage switch (P5) and the fourth negative voltage switch (N4) in series respectively;

the non-inverting input (Vinp2) of the second comparator circuit (13) is electrically connected to the Ground (GND) and the inverting input (Vinn2) is electrically connected to the input (VIN).

2. Interface circuit (10) according to claim 1, wherein the second comparator circuit (13) comprises a power supply terminal (VDD), a sixth positive voltage switch (P6), a seventh positive voltage switch (P7), an eighth positive voltage switch (P8), a ninth positive voltage switch (P9), a tenth positive voltage switch (P10), a fifth negative voltage switch (N5), a sixth negative voltage switch (N6), a seventh negative voltage switch (N7), an eighth negative voltage switch (N8); wherein,

the sixth positive voltage switch (P6), the fifth negative voltage switch (N5) and the seventh negative voltage switch (N7) are electrically connected between the power supply terminal (VDD) and the ground terminal (GND) after being connected in series; the seventh positive voltage switch (P7) and the sixth negative voltage switch (N6) are connected in series and then electrically connected between the power supply terminal (VDD) and a node (a2) formed by connecting the fifth negative voltage switch (N5) and the seventh negative voltage switch (N7) in series; a control terminal of the sixth positive voltage switch (P6) is electrically connected to a control terminal of the seventh positive voltage switch (P7); the control terminals of the fifth negative-voltage switch (N5) and the seventh negative-voltage switch (N7) are electrically connected to the inverting input terminal (Vinn2) of the second comparator circuit (13); the control terminal of the sixth negative voltage switch (N6) is electrically connected to the non-inverting input terminal (Vinp2) of the second comparator circuit (13);

the eighth positive voltage switch (P8) is connected in series with the ninth positive voltage switch (P9) and then electrically connected between the power supply terminal (VDD) and a node (b2) formed by connecting the seventh positive voltage switch (P7) in series with the sixth negative voltage switch (N6); the control ends of the eighth positive voltage switch (P8) and the ninth positive voltage switch (P9) are electrically connected to a node (b2) formed by the seventh positive voltage switch (P7) and the sixth negative voltage switch (N6) in series;

the tenth positive voltage switch (P10) and the eighth negative voltage switch (N8) are connected in series and then electrically connected between the power terminal (VDD) and the ground terminal (GND), and the control terminals of the tenth positive voltage switch (P10) and the eighth negative voltage switch (N8) are electrically connected to the inverting input terminal (Vinn2) of the second comparator circuit (13);

an output end (Vout2) of the second comparator circuit (13) is electrically connected to a node formed by the eighth positive voltage switch (P8) and the ninth positive voltage switch (P9) in series and a node formed by the tenth positive voltage switch (P10) and the eighth negative voltage switch (N8) in series respectively.

3. The interface circuit (10) of claim 2, wherein the first positive voltage switch (P1), the second positive voltage switch (P2), the third positive voltage switch (P3), the fourth positive voltage switch (P4), the fifth positive voltage switch (P5), the sixth positive voltage switch (P6), the seventh positive voltage switch (P7), the eighth positive voltage switch (P8), the ninth positive voltage switch (P9), and the tenth positive voltage switch (P10) are PMOS transistors, and their control terminals are gates of PMOS transistors.

4. The interface circuit (10) according to claim 2, wherein the first negative voltage switch (N1), the second negative voltage switch (N2), the third negative voltage switch (N3), the fourth negative voltage switch (N4), the fifth negative voltage switch (N5), the sixth negative voltage switch (N6), the seventh negative voltage switch (N7), and the eighth negative voltage switch (N8) are all NMOS transistors, and their control terminals are all gates of the NMOS transistors.

5. The interface circuit (10) according to claim 1, wherein the first power switch (MPS) is a PMOS transistor and its control terminal is a gate of the PMOS transistor, and the second power switch (MNS) is an NMOS transistor and its control terminal is a gate of the NMOS transistor.

6. A rectifier, characterized in that it comprises an interface circuit (10) according to any one of claims 1 to 5.

7. A wireless sensor comprising a rectifier, characterized in that the rectifier comprises an interface circuit (10) according to any of claims 1 to 5.