CN106206638A - Single-photon avalanche diode dot structure and picture element array structure - Google Patents

Abstract

The present invention provides a single photon avalanche diode pixel structure and a pixel array structure. The single photon avalanche diode pixel structure includes: a single photon avalanche diode, including an anode and a cathode; the cathode of the single photon avalanche diode is connected to a bias voltage source; a pull-up tube connected to the power supply, reset signal and the anode of the single photon avalanche diode; a pull-down tube unit connected to the first pull-up tube and the anode of the single photon avalanche diode; a quenching unit connected to the power supply and the pull-down tube The unit is connected with the anode of the single photon avalanche diode; the output unit is connected with the quenching unit. The pixel structure of the single photon avalanche diode of the present invention can bias the voltage of the anode and cathode of the single photon avalanche diode below the critical avalanche voltage when it is not selected for exposure and readout without avalanche effect; the pixel array structure of the present invention The exposure of a single pixel structure can be realized, which is convenient for studying the crosstalk effect of a single pixel structure on an adjacent pixel structure.

Description

Single photon avalanche diode pixel structure and pixel array structure

technical field

The invention belongs to the field of electrical technology, and in particular relates to a single photon avalanche diode pixel structure and a pixel array structure.

Background technique

A single photon avalanche diode (SPAD) is a diode biased above a critical avalanche voltage, which can be used as a pixel unit of a 3D image sensor. The 3D image sensor based on SPAD can quickly acquire the 3D information of the object and realize 3D reconstruction. Dark count rate (DCR) is an important index to evaluate the performance of SPAD, especially the post-pulse and adjacent pixel crosstalk will greatly affect the working performance of SPAD array.

Cristiano Niclass published a 3D CMOS image sensor based on SPAD pixel structure in JOURNAL OF SOLID-STATE CIRCUITS in 2008. The pixel structure of SPAD is shown in Figure 1. In FIG. 1, the transistor M1 is controlled by the row selection control signal ROWSEL. When the transistor M1 is turned on, the avalanche current of the SAPD can be read out on the column readout line through the action of the transistor M2 and the transistor M7. The transistor M6 controlled by the QCH signal and the transistor M5 as a capacitor realize the quenching function of the pixel, and the transistor M3 controlled by the RCH signal can realize the recharging function of the SPAD to prepare for the next exposure.

The structure of this pixel is simple, less transistors are used, and the functions of passive quenching and active charging can be realized. However, on the entire SPAD pixel array, the voltage applied to each SPAD cathode is above the critical avalanche voltage. For pixels that are not affected by the row selection control signal ROWSEL, the transistor M1 is not turned on, and the SPAD anode is suspended. Under this condition The SPAD will still be stimulated to produce an avalanche effect, thereby generating an avalanche current. A large number of electron-hole pairs generated due to the avalanche effect will crosstalk into adjacent pixels, affecting the normal operation of adjacent SPADs. The post-pulse effect will also make the SPAD unable to detect the correct photon signal. In addition, because the ROWSEL signal is row-selected to achieve the exposure of the entire row, it is difficult to evaluate the dark count rate of a single pixel and the impact of an avalanche on adjacent pixels when measuring the dark count rate.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a single photon avalanche diode pixel structure and a pixel array structure, which are used to solve the problem of each single photon avalanche diode cathode in the prior art single photon avalanche diode array. The voltages are all above the critical avalanche voltage value, and the pixel structures that are not affected by the row selection control signal will still be stimulated to produce an avalanche effect, which will affect the normal operation of adjacent single photon avalanche diodes, so that the single photon avalanche diodes cannot be measured correctly. The problem of the photon signal, and because the exposure of the entire row is realized under the control of the row selection control signal, when measuring the dark count rate, it is difficult to evaluate the dark count rate of a single pixel structure and the impact on adjacent pixel structures after an avalanche of a single pixel structure problem of impact.

To achieve the above purpose and other related purposes, the present invention provides a single photon avalanche diode pixel structure, the single photon avalanche diode pixel structure includes:

A single photon avalanche diode, including an anode and a cathode; the cathode of the single photon avalanche diode is connected to a bias voltage source, and the bias voltage of the bias voltage source is VB+VE, wherein, VB is the single photon avalanche diode The critical avalanche voltage of the avalanche diode, VE, is less than the power supply voltage of the power supply;

The first pull-up tube is connected to the power supply, the reset signal, and the anode of the single photon avalanche diode, and is adapted to be turned on when the reset signal is at a low level, so that the bias between the anode and the cathode of the single photon avalanche diode is Setting the voltage lower than the critical avalanche voltage, so that the avalanche effect does not occur, to reset the single photon avalanche diode;

The pull-down tube unit is connected to the first pull-up tube and the anode of the single photon avalanche diode, and is adapted to pull down the anode of the single photon avalanche diode to a potential consistent with GND when it is turned on, so that the The bias voltage between the anode and the cathode of the single photon avalanche diode is higher than the critical avalanche voltage, so that the avalanche effect occurs;

The quenching unit is connected to the power supply, the pull-down tube unit and the anode of the single photon avalanche diode, and is suitable for quenching the single photon avalanche diode after the avalanche effect occurs in the single photon avalanche diode, so that The voltage of the single photon avalanche diode anode is biased on the power supply voltage of the power supply;

The output unit is connected with the quenching unit and is adapted to read and output the pulse signal generated by the avalanche effect of the single photon avalanche diode.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the first pull-up tube is a PMOS tube, the source of the first pull-up tube is connected to the power supply, and the first pull-up tube The gate of the pull-up transistor is connected to the reset signal, and the drain of the first pull-up transistor is connected to the anode of the single photon avalanche diode.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the pull-down tube unit includes a first pull-down tube group and a second pull-down tube group;

The first pull-down tube group includes a first pull-down tube and a second pull-down tube, both of which are NMOS tubes; the drain of the first pull-down tube and the second pull-down tube The anode of the single photon avalanche diode is connected, the source of the first pull-down tube is connected to the drain of the second pull-down tube, and the source of the second pull-down tube is grounded;

The second pull-down tube group includes a third pull-down tube and a fourth pull-down tube, both of which are NMOS tubes; the drain of the third pull-down tube is connected to the single photon tube The anodes of the avalanche diodes are connected, the source of the third pull-down transistor is connected with the drain of the fourth pull-down transistor, and the source of the fourth pull-down transistor is grounded.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the grid of the first pull-down transistor and the grid of the third pull-down transistor are all connected to the row selection control signal; The grid of the tube is connected to the column selection control signal; the grid of the fourth pull-down tube is connected to the single-selection control signal, and when the single-selection control signal is at a high level, the fourth pull-down tube is turned on. The row selection control signal implements a row exposure mode, and if the radio selection control signal is at a low level, only the pixel structure selected under the joint action of the row selection control signal and the column selection control signal can have an avalanche effect, This enables single-pixel exposure mode.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the quenching unit includes: an active resistance transistor, a switching transistor, an inverter and a quenching transistor;

The active resistance transistor is connected to the pull-down tube unit and the anode of the single photon avalanche diode; the switch transistor is connected to the active resistance transistor; the input terminal of the inverter is connected to the single photon avalanche diode The anode of the diode is connected to the active resistance transistor, the output terminal of the inverter is connected to the switching transistor; the quenching transistor is connected to the power supply, the anode of the single photon avalanche diode, the The active resistance transistor and the output terminal of the inverter are connected; when the pull-down tube unit is turned on, the switch transistor is turned on, and the switch transistor, the active resistance transistor and the inverter Working together, the voltage of the anode of the single photon avalanche diode is kept at the GND voltage value; when the avalanche effect occurs in the single photon avalanche diode, the avalanche current acts on the active resistance transistor to generate a voltage drop, and the inverter and The quenching transistors cooperate to quench the single photon avalanche diode.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the active resistance transistor is an NMOS transistor, and the drain of the active resistance transistor is connected to the anode of the single photon avalanche diode and the pull-down transistor unit The gate of the active resistance transistor is connected with the anode of the single photon avalanche diode and the input terminal of the inverter, and the source of the active resistance transistor is connected with the switch transistor.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the switch transistor is an NMOS tube, the drain of the switch transistor is connected to the active resistance transistor, and the source of the switch transistor is grounded. The gate of the switching transistor is connected with the output terminal of the inverter, the quenching transistor and the output unit.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the quenching transistor is a PMOS tube, the source of the quenching transistor is connected to the power supply, the gate of the quenching transistor is connected to the inverter The output terminal of the phase controller is connected with the switching transistor and the output unit, and the drain of the quenching transistor is connected with the anode of the single photon avalanche diode.

As a preferred solution of the single photon avalanche diode pixel structure of the present invention, the output unit includes a second pull-up transistor, a fifth pull-down transistor and an output switch transistor;

The second pull-up transistor is a PMOS transistor, the source of the second pull-up transistor is connected to the power supply, the gate of the second pull-up transistor is connected to the gate of the quenching transistor, the The output end of the inverter is connected to the gate of the switching transistor;

The fifth pull-down transistor is an NMOS transistor, the source of the fifth pull-down transistor is grounded, the gate of the fifth pull-down transistor is connected to the gate of the quenching transistor, the output terminal of the inverter, the The gate of the switching transistor is connected to the gate of the second pull-up transistor;

The output switch tube is a PMOS tube, the source of the output switch tube is connected to the drain of the second pull-up tube, and the drain of the output switch tube is connected to the drain of the fifth pull-down tube. Connected as the output end of the output unit, the gate of the output switching tube is connected to the row sharing signal, and is suitable for keeping conduction for a predetermined period of time before and after exposure, so as to cooperate with the second pull-up tube and the The fifth pull-down tube reads the pulse signal generated by the avalanche effect of the single photon avalanche diode.

The present invention also provides a pixel array structure, which includes: a plurality of single photon avalanche diode pixel structures as described in any of the above schemes, the single photon avalanche diode pixel structures are arranged in an array; The photonic avalanche diode pixel structures are all connected with the row selection control signal, the column selection control signal, the row sharing signal, the reset signal and the radio selection control signal.

As mentioned above, the single photon avalanche diode pixel structure and the pixel array structure of the present invention have the following beneficial effects: the single photon avalanche diode pixel structure of the present invention can connect the single photon avalanche diode anode and cathode when not selected for exposure and readout The voltage bias is below the critical avalanche voltage without avalanche effect; the pixel array structure of the present invention can realize the exposure of a single pixel structure, which is convenient for studying the crosstalk effect of a single pixel structure on adjacent pixel structures.

Description of drawings

FIG. 1 is a schematic circuit diagram of a single photon avalanche diode pixel structure in the prior art.

FIG. 2 is a schematic circuit diagram of the single photon avalanche diode pixel structure provided in Embodiment 1 of the present invention.

FIG. 3 shows a pixel timing diagram of the single photon avalanche diode pixel structure provided in Embodiment 1 of the present invention.

FIG. 4 is a schematic circuit diagram of a pixel array structure provided in Embodiment 2 of the present invention.

Fig. 5 shows the pixel timing diagram of the pixel array structure exposed row by row and the exposure of the single pixel structure provided in the second embodiment of the present invention; where (a) is the pixel timing diagram of the row by row exposure, (b) is the pixel timing diagram of the single pixel structure exposure Pixel Timing Diagram.

Component designation description

1 Single photon avalanche diode pixel structure

11 Single Photon Avalanche Diode

12 Pull down tube unit

13 Quenching unit

14 output unit

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 2 through 5. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

Please refer to FIG. 2 , the present invention provides a single photon avalanche diode pixel structure 1, the single photon avalanche diode pixel structure 1 includes: a single photon avalanche diode 11, and the single photon avalanche diode 11 includes an anode and a cathode, as shown in FIG. 2 Represent the anode of described single photon avalanche diode 11 with A, represent the cathode of described single photon avalanche diode 11 with K; The cathode of described single photon avalanche diode 11 is connected with a bias voltage source (not shown), so The bias voltage of the bias voltage source is VB+VE, wherein, VB is the critical avalanche voltage of the single photon avalanche diode 11, and VE is less than the power supply voltage VDD of the power supply; the first pull-up tube T1, the first The pull-up tube T1 is connected to the power supply (the power supply is not shown, and the power supply voltage VDD of the power supply is used as an illustration in FIG. The reset signal Rest is turned on when it is at a low level, so that the bias voltage of the anode and cathode of the single photon avalanche diode 11 is lower than the critical avalanche voltage, so that the avalanche effect does not occur, so as to reset the single photon avalanche diode 11; pull down Tube unit 12, the pull-down tube unit 12 is connected to the anode of the first pull-up tube T1 and the single photon avalanche diode 11, and is suitable for pulling down the anode of the single photon avalanche diode 11 to A potential consistent with GND, so that the bias voltage of the anode and cathode of the single photon avalanche diode 11 is higher than the critical avalanche voltage, so that an avalanche effect occurs; the quenching unit 13, the quenching unit 13 and the power supply, the pull-down The tube unit 12 is connected to the anode of the single photon avalanche diode 11, and is suitable for quenching the single photon avalanche diode 11 after the avalanche effect occurs in the single photon avalanche diode 11, so that the single photon avalanche diode anode 11 The voltage bias of the power supply is on the power supply voltage VDD of the power supply; the output unit 14, the output unit 14 is connected with the quenching unit 13, is suitable for reading and outputting the result of the avalanche effect of the single photon avalanche diode 11. generated pulse signal.

As an example, the first pull-up transistor T1 is a PMOS transistor, the source of the first pull-up transistor T1 is connected to the power supply, the gate of the first pull-up transistor T1 is connected to the reset signal Rest is connected, and the drain of the first pull-up transistor T1 is connected to the anode of the single photon avalanche diode 11 . When the reset signal Rest is at a low level, the first pull-up transistor T1 is turned on, the voltage of the anode of the single photon avalanche diode 11 is VDD, and the voltage of the cathode of the single photon avalanche diode 11 is VB +VE, at this time, the voltage difference between the two ends of the single photon avalanche diode 11 (that is, the voltage difference between the cathode and the anode) is VB+VE-VDD<VB, and the voltage difference between the two ends of the single photon avalanche diode 11 is less than the critical avalanche voltage , so that the avalanche effect does not occur, and the reset of the single photon avalanche diode 11 is realized. When the Rest is at a high level, the first pull-up transistor T1 is turned off and does not work.

As an example, the pull-down tube unit includes a first pull-down tube group and a second pull-down tube group; the first pull-down tube group includes a first pull-down tube T2 and a second pull-down tube T3, and the first pull-down tube Both the tube T2 and the second pull-down tube T3 are NMOS tubes; the drain of the first pull-down tube T2 is connected to the anode of the single photon avalanche diode 11, and the source of the first pull-down tube T2 It is connected with the drain of the second pull-down transistor T3, and the source of the second pull-down transistor T3 is grounded; the second pull-down transistor group includes a third pull-down transistor T4 and a fourth pull-down transistor T5, and the third pull-down transistor T5 Both the pull-down transistor T4 and the fourth pull-down transistor T5 are NMOS transistors; the drain of the third pull-down transistor T4 is connected to the anode of the single photon avalanche diode 11, and the source of the third pull-down transistor T4 is connected to the anode of the single photon avalanche diode 11. The drains of the fourth pull-down transistor T5 are connected, and the source of the fourth pull-down transistor T5 is grounded. The first pull-down tube group and the second pull-down tube group can respectively pull down the anode of the single photon avalanche diode 11 to a potential consistent with GND, that is, when the first pull-down tube T2 and the When the second pull-down transistor T3 is turned on or when the third pull-down transistor T4 and the fourth pull-down transistor T5 are turned on, the anode voltage of the single photon avalanche diode 11 is pulled to a voltage consistent with GND (ground voltage). value, that is, the anode of the single photon avalanche diode 11 will be pulled to a low level, at this time, the voltage difference between the anode and the cathode of the single photon avalanche diode 11 is VB+VE-0>VB, the single The voltage difference between the two ends of the photonic avalanche diode 11 is greater than the critical avalanche voltage, so that an avalanche effect occurs to detect incident photon (Photon) signals.

As an example, both the gate of the first pull-down transistor T2 and the gate of the third pull-down transistor T4 are connected to the row selection control signal Row, when multiple single photon avalanche diode pixel structures 11 form multiple rows In the case of a multi-column array, the row selection control signal Row is suitable for selecting the entire row of the single photon avalanche diode pixel structure 11 to be exposed; the gate of the second pull-down transistor T3 is connected to the column selection control signal Column, When a plurality of single photon avalanche diode pixel structures 11 form an array of multiple rows and multiple columns, the column selection control signal Column is suitable for selecting the entire column of single photon avalanche diode pixel structures 11 to be exposed; the fourth pull-down The gate of the tube T5 is connected to the single selection control signal Single, and when the single selection control signal Single is at a high level, the fourth pull-down tube T5 is turned on, and cooperates with the row selection control signal Row to realize the row exposure mode, namely When the single selection control signal Single and the row selection control signal Row are both high level, the voltage of the anode of the single photon avalanche diode 11 will be pulled to a voltage value consistent with GND, and the row exposure mode can be realized ; If the single selection control signal Single is low level, only under the joint action of the row selection control signal Row and the column selection control signal Column (that is, the row selection control signal Row and the column selection control signal The pixel structure selected by Column (both at high level) can produce an avalanche effect, thereby realizing the single-pixel exposure mode.

As an example, the quenching unit 13 includes: an active resistance transistor T6, a switch transistor T7, an inverter I1 and a quenching transistor T8; The anode is connected; the switching transistor T7 is connected with the active resistance transistor T6; the input terminal of the inverter I1 is connected with the anode of the single photon avalanche diode 11 and the active resistance transistor T6, The output terminal of the inverter I1 is connected to the switching transistor T7; the quenching transistor T8 is connected to the power supply, the anode of the single photon avalanche diode 11, the active resistance transistor T6 and the inverter. The output terminals of the phase device I1 are connected; when the pull-down tube unit 12 is turned on, the switching transistor T7 is turned on, and the switching transistor T7, the active resistance transistor T6 and the inverter I1 work together The voltage of the anode of the single photon avalanche diode 11 is kept at the GND voltage value; when the avalanche effect occurs in the single photon avalanche diode 11, the avalanche current acts on the active resistance transistor T6 to generate a voltage drop, and the inverter I1 works together with the quenching transistor T8 to quench the single photon avalanche diode 11 .

As an example, the active resistance transistor T6 is an NMOS transistor, and the drain of the active resistance transistor T6 is connected to the anode of the single photon avalanche diode 11 and the pull-down transistor unit 12. Specifically, the The drain of the source resistance transistor T6 is connected to the drain of the first pull-down tube T2, and the gate of the active resistance transistor T6 is connected to the anode of the single photon avalanche diode 11 and the inverter I1. The input terminals are connected, and the source of the active resistance transistor T6 is connected with the switching transistor T7.

As an example, the switching transistor T7 is an NMOS transistor, the drain of the switching transistor T7 is connected to the active resistance transistor T6, specifically, the drain of the switching transistor T7 is connected to the active resistance transistor T6 The source of the switching transistor T7 is connected to the ground, and the gate of the switching transistor T7 is connected to the output terminal of the inverter I1, the quenching transistor T8 and the output unit 14.

As an example, the quenching transistor T8 is a PMOS transistor, the source of the quenching transistor T8 is connected to the power supply, the gate of the quenching transistor T8 is connected to the output terminal of the inverter I1, the switch The transistor T7 is connected to the output unit 14, specifically, the gate of the quenching transistor T8 is connected to the output terminal of the inverter I1, the gate of the switching transistor T7 and the output unit 14, The drain of the quenching transistor T8 is connected to the anode of the single photon avalanche diode 11 .

Specifically, when the pull-down tube unit 12 is turned on, under the action of the pull-down tube unit 12, the anode voltage of the single photon avalanche diode 11 is biased on the GND voltage, that is, the single photon avalanche diode 11 The anode is at a low level, at this time, the input of the inverter I1 is at a low level, and the output is at a high level, at this time, the switching transistor T7 is turned on, so that the source of the active resistance transistor T6 is at low level, so that the voltage drop across the active resistance transistor T6 is 0, that is, keep the anode of the single photon avalanche diode 11 in a low voltage state. When the avalanche effect occurs in the single photon avalanche diode 11, the avalanche current acts on the active resistance transistor T6, and generates a large voltage drop on the active resistance transistor T6, and the inverter I1 The input is a high level, and the output is a low level. At this time, the quenching transistor T8 is turned on, so that the anode of the single photon avalanche diode 11 is connected to the power supply through the quenching transistor T8, so that the The anode of the single photon avalanche diode 11 is stably biased on the power supply voltage VDD.

As an example, the output unit 14 includes a second pull-up transistor T9, a fifth pull-down transistor T11, and an output switch transistor T10; the second pull-up transistor T9 is a PMOS transistor, and the source of the second pull-up transistor T9 Connected to the power supply, the gate of the second pull-up transistor T9 is connected to the gate of the quenching transistor T8, the output terminal of the inverter I1 and the gate of the switching transistor T7; The fifth pull-down transistor T11 is an NMOS transistor, the source of the fifth pull-down transistor T11 is grounded, and the gate of the fifth pull-down transistor T11 is connected to the gate of the quenching transistor T8 and the inverter I1. The output terminal, the gate of the switching transistor T7 and the gate of the second pull-up transistor T9 are connected; the output switching transistor T10 is a PMOS transistor, and the source of the output switching transistor T10 is connected to the second pull-up transistor T9. The drain of the pull-up transistor T9 is connected, the drain of the output switching transistor T10 is connected to the drain of the fifth pull-down transistor T11 as the output terminal of the output unit 14, and the gate of the output switching transistor T10 The pole is connected to the row sharing signal Rout, and is suitable for keeping on for a predetermined period of time before and after exposure, so as to cooperate with the second pull-up transistor T9 and the fifth pull-down transistor T11 to read the occurrence of the single photon avalanche diode 11. The pulse signal produced by the avalanche effect.

The timing configuration and simulation results of a single single photon avalanche diode pixel structure are shown in FIG. 3 , and it can be known from FIG. 3 that the functional characteristics of each transistor can be realized through the timing configuration and simulation results. Among them, in Figure 3, Photon is the photon arrival time set by the simulation, A signal is the voltage signal of the node where the anode of the single photon avalanche diode is located, and the out signal is the simulation structure of the output node.

The single photon avalanche diode pixel structure of the present invention can bias the voltage of the anode and cathode of the single photon avalanche diode below the critical avalanche voltage when not selected for exposure and readout without avalanche effect.

Embodiment two

Please refer to FIG. 4, the present invention also provides a pixel array structure, the pixel array structure includes: a plurality of single photon avalanche diode pixel structures 1 as described in any of the above schemes, the single photon avalanche diode pixel structure 1 Distributed in an array; the single photon avalanche diode pixel structure 1 is connected to the row selection control signal Row, the column selection control signal Column, the row sharing signal Rout, the reset signal Rest and the single selection control signal Single; all the single photon avalanche diodes The cathodes of the single photon avalanche diodes 11 in the diode pixel structure 1 are uniformly connected to a voltage whose voltage value is VE+VB, and all the single photon avalanche diode pixel structures 1 share a power supply voltage VDD and a ground voltage GND.

As an example, in FIG. 4 , the pixel array structure includes the single photon avalanche diode pixel structure 1 with N rows and M columns as an example, where M and N are both integers greater than or equal to 1.

When the pixel array structure needs to be exposed row by row, the reset signal Rest is at high level, the single selection control signal Single is at high level, and the column selection control signal Column of each column is at low level , at this time, the row selection control signal Row of each row exposes the single photon avalanche diode pixel structure in the pixel array structure row by row, and the row sharing control signal Rout makes the output out terminal read the avalanche diode pixel structure of each row Pulse signal.

When the pixel array structure needs to perform single-pixel exposure, the reset signal Rest is at a high level, the radio selection control signal Single is at a low level, and the column selection control signal Column of each column is at a high level. The row selection control signal Row of each row can select a single photon avalanche diode pixel structure corresponding to the row and column for exposure, and the row sharing control signal Rout makes the output out terminal output a corresponding avalanche pulse signal. At this time, other The single photon avalanche diode pixel structure achieves no output avalanche pulse signal generation but pixel exposure. The pixel array structure of the present invention can realize the exposure of a single pixel structure, and is convenient for studying the crosstalk influence of a single pixel structure on an adjacent pixel structure.

In summary, the present invention provides a single photon avalanche diode pixel structure and a pixel array structure. The single photon avalanche diode pixel structure includes: a single photon avalanche diode, including an anode and a cathode; A bias voltage source is connected, and the bias voltage of the bias voltage source is VB+VE, wherein, VB is the critical avalanche voltage of the single photon avalanche diode, and VE is less than the power supply voltage of the power supply; the first pull-up The tube is connected to the power supply, the reset signal and the anode of the single photon avalanche diode, and is adapted to be turned on when the reset signal is at a low level, so that the bias voltage between the anode and the cathode of the single photon avalanche diode is lower than Critical avalanche voltage, so that the avalanche effect does not occur, so as to reset the single photon avalanche diode; the pull-down tube unit is connected with the first pull-up tube and the anode of the single photon avalanche diode, and is suitable for conducting Pulling down the anode of the single photon avalanche diode to a potential consistent with GND, so that the bias voltage between the anode and the cathode of the single photon avalanche diode is higher than the critical avalanche voltage, so that an avalanche effect occurs; the quenching unit is connected with the power supply , the pull-down tube unit and the anode of the single photon avalanche diode are connected, suitable for quenching the single photon avalanche diode after the avalanche effect occurs in the single photon avalanche diode, so that the anode of the single photon avalanche diode The voltage is biased on the power supply voltage of the power supply; the output unit is connected with the quenching unit and is adapted to read and output the pulse signal generated by the avalanche effect of the single photon avalanche diode. The single photon avalanche diode pixel structure of the present invention can bias the voltage of the anode and cathode of the single photon avalanche diode below the critical avalanche voltage when not selected for exposure and readout without avalanche effect; the pixel array structure of the present invention The exposure of a single pixel structure can be realized, which is convenient for studying the crosstalk effect of a single pixel structure on an adjacent pixel structure.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (10)

1. A single photon avalanche diode pixel structure, characterized in that the single photon avalanche diode pixel structure comprises: A single photon avalanche diode, including an anode and a cathode; the cathode of the single photon avalanche diode is connected to a bias voltage source, and the bias voltage of the bias voltage source is VB+VE, wherein, VB is the single photon avalanche diode The critical avalanche voltage of the avalanche diode, VE, is less than the power supply voltage of the power supply; The first pull-up tube is connected to the power supply, the reset signal, and the anode of the single photon avalanche diode, and is adapted to be turned on when the reset signal is at a low level, so that the bias between the anode and the cathode of the single photon avalanche diode is Setting the voltage lower than the critical avalanche voltage, so that the avalanche effect does not occur, to reset the single photon avalanche diode; The pull-down tube unit is connected to the first pull-up tube and the anode of the single photon avalanche diode, and is adapted to pull down the anode of the single photon avalanche diode to a potential consistent with GND when it is turned on, so that the The bias voltage between the anode and the cathode of the single photon avalanche diode is higher than the critical avalanche voltage, so that the avalanche effect occurs; The quenching unit is connected to the power supply, the pull-down tube unit and the anode of the single photon avalanche diode, and is suitable for quenching the single photon avalanche diode after the avalanche effect occurs in the single photon avalanche diode, so that The voltage of the single photon avalanche diode anode is biased on the power supply voltage of the power supply; The output unit is connected with the quenching unit and is adapted to read and output the pulse signal generated by the avalanche effect of the single photon avalanche diode. 2. The single photon avalanche diode pixel structure according to claim 1, characterized in that: the first pull-up transistor is a PMOS transistor, and the source of the first pull-up transistor is connected to the power supply, so The gate of the first pull-up transistor is connected to the reset signal, and the drain of the first pull-up transistor is connected to the anode of the single photon avalanche diode. 3. The single photon avalanche diode pixel structure according to claim 1, wherein the pull-down tube unit comprises a first pull-down tube group and a second pull-down tube group; The first pull-down tube group includes a first pull-down tube and a second pull-down tube, both of which are NMOS tubes; the drain of the first pull-down tube and the second pull-down tube The anode of the single photon avalanche diode is connected, the source of the first pull-down tube is connected to the drain of the second pull-down tube, and the source of the second pull-down tube is grounded; The second pull-down tube group includes a third pull-down tube and a fourth pull-down tube, both of which are NMOS tubes; the drain of the third pull-down tube is connected to the single photon tube The anodes of the avalanche diodes are connected, the source of the third pull-down transistor is connected with the drain of the fourth pull-down transistor, and the source of the fourth pull-down transistor is grounded. 4. single photon avalanche diode pixel structure according to claim 3, is characterized in that: the grid of described first pull-down transistor and the grid of described 3rd pull-down transistor are all connected with row selection control signal; The grid of the second pull-down tube is connected to the column selection control signal; the grid of the fourth pull-down tube is connected to the single-selection control signal, and when the single-selection control signal is high, the fourth pull-down tube conduction, cooperate with the row selection control signal to realize the row exposure mode, if the radio selection control signal is at low level, only the pixel structure selected under the joint action of the row selection control signal and the column selection control signal can be An avalanche effect occurs, enabling a single-pixel exposure mode. 5. The single photon avalanche diode pixel structure according to claim 1, wherein the quenching unit comprises: an active resistance transistor, a switching transistor, an inverter and a quenching transistor; The active resistance transistor is connected to the pull-down tube unit and the anode of the single photon avalanche diode; the switch transistor is connected to the active resistance transistor; the input terminal of the inverter is connected to the single photon avalanche diode The anode of the diode is connected to the active resistance transistor, the output terminal of the inverter is connected to the switching transistor; the quenching transistor is connected to the power supply, the anode of the single photon avalanche diode, the The active resistance transistor and the output terminal of the inverter are connected; when the pull-down tube unit is turned on, the switch transistor is turned on, and the switch transistor, the active resistance transistor and the inverter Working together, the voltage of the anode of the single photon avalanche diode is kept at the GND voltage value; when the avalanche effect occurs in the single photon avalanche diode, the avalanche current acts on the active resistance transistor to generate a voltage drop, and the inverter and The quenching transistors cooperate to quench the single photon avalanche diode. 6. The single photon avalanche diode pixel structure according to claim 5, characterized in that: the active resistance transistor is an NMOS tube, the drain of the active resistance transistor is connected to the anode of the single photon avalanche diode and the The pull-down tube unit is connected, the gate of the active resistance transistor is connected with the anode of the single photon avalanche diode and the input terminal of the inverter, and the source of the active resistance transistor is connected with the switch The transistors are connected. 7. The single photon avalanche diode pixel structure according to claim 5, characterized in that: the switch transistor is an NMOS tube, the drain of the switch transistor is connected to the active resistance transistor, and the switch transistor The source is grounded, and the gate of the switching transistor is connected with the output terminal of the inverter, the quenching transistor and the output unit. 8. The single photon avalanche diode pixel structure according to claim 5, characterized in that: the quenching transistor is a PMOS transistor, the source of the quenching transistor is connected to the power supply, and the gate of the quenching transistor It is connected with the output terminal of the inverter, the switching transistor and the output unit, and the drain of the quenching transistor is connected with the anode of the single photon avalanche diode. 9. The single photon avalanche diode pixel structure according to claim 1, wherein the output unit comprises a second pull-up transistor, a fifth pull-down transistor and an output switch transistor; The second pull-up transistor is a PMOS transistor, the source of the second pull-up transistor is connected to the power supply, the gate of the second pull-up transistor is connected to the gate of the quenching transistor, the The output end of the inverter is connected to the gate of the switching transistor; The fifth pull-down transistor is an NMOS transistor, the source of the fifth pull-down transistor is grounded, the gate of the fifth pull-down transistor is connected to the gate of the quenching transistor, the output terminal of the inverter, the The gate of the switching transistor is connected to the gate of the second pull-up transistor; The output switch tube is a PMOS tube, the source of the output switch tube is connected to the drain of the second pull-up tube, and the drain of the output switch tube is connected to the drain of the fifth pull-down tube. Connected as the output end of the output unit, the gate of the output switching tube is connected to the row sharing signal, and is suitable for keeping conduction for a predetermined period of time before and after exposure, so as to cooperate with the second pull-up tube and the The fifth pull-down tube reads the pulse signal generated by the avalanche effect of the single photon avalanche diode. 10. A pixel array structure, characterized in that the pixel array structure comprises: a plurality of single photon avalanche diode pixel structures as claimed in any one of claims 1 to 9, wherein the single photon avalanche diode pixel structure is Array distribution; the single photon avalanche diode pixel structure is connected with row selection control signal, column selection control signal, row sharing signal, reset signal and radio selection control signal.