CN106163076B

CN106163076B - Selective segment via plating process and structure

Info

Publication number: CN106163076B
Application number: CN201510127856.XA
Authority: CN
Inventors: 余玛莉; 潘关
Original assignee: Multek Technologies Ltd
Current assignee: Multek Technologies Ltd
Priority date: 2015-03-23
Filing date: 2015-03-23
Publication date: 2020-10-16
Anticipated expiration: 2035-03-23
Also published as: CN106163076A

Abstract

A selective section via plating process for manufacturing circuit boards that selectively interconnect internal conductive layers as separate sections within the same via. The plating resist is plunged through the hole into the core and then stripped after the electroless plating process. This electroless plating stripping of the plating resist causes plating discontinuities on the via walls. During subsequent plating, the inner core layer cannot be plated due to such plating discontinuity. The resulting circuit board structure has a plurality of separate electrical interconnect segments within the via.

Description

Selective segment via plating process and structure

The invention belongs to the field of the following:

the present invention generally relates to printed circuit boards. More specifically, the present invention relates to printed circuit boards having selective section via plating.

Background of the invention:

a Printed Circuit Board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads, and other features etched from a conductive sheet (e.g., a copper sheet) laminated onto a non-conductive substrate. A multi-level printed circuit board is formed by stacking and laminating a plurality of such etched conductive sheet/non-conductive substrate laminates. The wires on the different layers are interconnected with plated through holes, called vias.

Fig. 1 shows a cut-out side view of a portion of a conventional printed circuit board. The printed circuit board 2 comprises a plurality of stacked layers made of a plurality of

non-conductive layers

4, 6 and a plurality of conductive layers 8. These non-conductive layers may be made of a prepreg or substrate that is part of the core structure or is the core only. Prepregs are fiber-reinforced materials that are impregnated or coated with a thermosetting resin binder and consolidated and cured into an intermediate-stage semi-solid product. The prepreg serves as an adhesive layer to bond a plurality of discrete layers of a multi-layer PCB structure, wherein the multi-layer PCB is composed of a plurality of conductive lines and alternating layers of a plurality of base materials bonded together, including at least one inner conductive layer. The substrate is an organic or inorganic material for supporting the pattern of conductor material. The core is a metal clad substrate wherein the substrate has integral metal wire material on one or both sides. A laminated stack is formed by stacking a plurality of core structures with prepregs interposed therebetween and then laminating the stack. The vias 10 are then formed by drilling holes through the laminated stack and plating the walls of the holes with a conductive material, such as copper. The resulting plating 12 interconnects these conductive layers 8.

In the exemplary application shown in fig. 1, the plating layer 12 extends uninterrupted through the entire thickness of the via 10, thereby providing a common interconnect with each conductive layer 8. In other applications, it may be desirable that only some of the conductive layers are commonly interconnected by plating within the vias. The common interconnect layer is referred to as a segment. Formation of the segments requires a break in the via wall plating, however, the electroplating process that forms the plating on the via walls is commonly applied to the entire wall surface. Thus, to form the desired plated breaks, the printed circuit boards are formed as individual component stacks that are laminated together. Each component laminate stack has the desired plated vias, but when laminated together, the plated vias from each component laminate stack are separated by a broken non-conductive material that forms a complete via wall plating. Fig. 2 shows a cut-out side view of a portion of two conventional component stacks to be subsequently used to form a printed circuit board. The component laminate stack 20 includes a plurality of

non-conductive layers

24, 26 and a plurality of conductive layers 28. The non-conductive layers 24 and the conductive layers 28 form a plurality of core structures that are laminated together with the non-conductive layer 26 (e.g., prepreg) in between. The vias 22 are formed by drilling through the laminated stack and plating the walls of the holes with a conductive material. The resulting plating interconnects these conductive layers 28. The second component laminate stack 30 is formed in a similar manner and includes a laminate stack of a plurality of non-conductive layers 34, 36 and a plurality of conductive layers 38 and plated vias 32. To form a complete printed circuit board, the two

components

20 and 30 are stacked such that the

respective vias

22 and 32 are aligned and laminated together with the non-conductive layer 40 in between, as shown in fig. 3. The non-conductive layer 40 provides a break in the conductive plating of the via 22 and the conductive plating of the via 32, thereby forming two separate sections in the printed circuit board of fig. 3.

The process shown in fig. 2 and 3 is known as progressive pressing. The problem with progressive pressing is that it is difficult to properly align the vias of the stacked components. As shown in fig. 3, the via centerline 42 of the via 22 in the component 20 is not properly aligned with the via centerline 44 of the via 32 in the component 30. This is referred to as layer-to-layer misalignment and can lead to performance problems.

In some applications, one or more of the conductive layers closest to the top or bottom surface of the printed circuit board are not designed to interconnect with the via plating. In order to cut off this connection of the one or more conductive layers, a backdrilling process is performed, wherein holes are drilled into the printed circuit board at the vias. The hole diameter is wider than the via diameter such that the drilled hole clears the wall plating and thereby the interconnect plating between the plurality of conductive layers. Fig. 4 shows a cut-out side view of a portion of a conventional printed circuit board with a via back drilled. The printed circuit board 52 is similar to the printed circuit board 2 of fig. 1, except that the hole 64 has been back drilled into the printed circuit board 52. The backdrilled holes 64 clear the corresponding portions of the plating 62 in the vias 60 that are in the same location as the several bottom layers of the printed circuit board 52. The remaining plating 62 provides interconnection to the conductive layers 58, however, the best conductive underlayer 58' is no longer interconnected to the conductive layers 58 because the interconnect plating 62 is removed in the holes 64. Importantly, the backdrilling process leaves the conductive layers 58 intact, which results in a via stub (stub)66 extending from the last interconnected conductive layer 58. A via stub is a conductive portion of a via that is not connected in series with a circuit. The longer the via stub, the greater the signal reflection and degradation. As such, it is desirable to minimize the length of the via stub. However, conventional backdrilling processes have high variability and it is difficult to control the length of the via stub. Furthermore, backdrilling is time consuming and expensive.

Summary of the invention:

various embodiments relate to a selective section via plating process for manufacturing circuit boards having selective inner layer connections as separate sections within the same via. The plating resist is plunged through the hole into the core and then stripped after an electroless plating process. This electroless plating of the plating resist causes plating discontinuities on the via walls. During subsequent plating, the inner core layer cannot be plated due to such plating discontinuity. The resulting circuit board structure has a plurality of separate electrical interconnect segments within the via. The selective segment via plating process uses a single lamination step.

In one aspect, a circuit board is disclosed. The circuit board includes a laminated stack including a plurality of non-conductive layers and a plurality of conductive layers. The laminate stack further includes an interposer layer having a plating resist layer. A via is formed through the laminate stack wherein walls of the via are plated with a conductive material except where the via passes through the interposer layer, thereby forming a via wall plating discontinuity. In some embodiments, each of these conductive layers is etched with a pattern. In some embodiments, the via is a single bore through the entirety of the laminate stack. In some embodiments, the via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. In some embodiments, the via wall plating includes a first plating stub extending from the first segment and a second plating stub extending from the second segment. In some embodiments, the first plating stub has a defined stub length equal to the thickness of the non-conductive layer between the first segment and the nearest surface of the plating resist layer. In some embodiments, the second plating stub has a defined stub length equal to the thickness of the non-conductive layer between the second segment and the nearest surface of the plating resist layer. In some embodiments, the interposer layer further comprises a non-conductive layer coupled to the plating resist layer. In some embodiments, the circuit board further includes a cavity extending from the via in the interposer layer.

In another aspect, another circuit board is disclosed. The circuit board includes a laminated stack including a plurality of non-conductive layers and a plurality of conductive layers. The laminate stack further includes an interposer layer having a plating resist layer. Vias are formed through the laminate stack, wherein walls of the vias are plated with a conductive material except where the vias pass through the interposer layer. A cavity extends from the via of the interposer layer, wherein the cavity forms a via wall plating discontinuity. The via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. The via wall plating includes a first plating stub extending from the first segment to the cavity and a second plating stub extending from the second segment to the cavity. In some embodiments, each of these conductive layers is etched with a pattern. In some embodiments, the via is a single bore through the entirety of the laminate stack. In some embodiments, the first plating stub has a defined stub length equal to the thickness of the non-conductive layer between the first segment and the nearest surface of the plating resist layer. In some embodiments, the second plating stub has a defined stub length equal to the thickness of the non-conductive layer between the second segment and the nearest surface of the plating resist layer. In some embodiments, the interposer layer further comprises a non-conductive layer coupled to the plating resist layer.

In yet another aspect, a multiple network architecture is disclosed. The structure includes a circuit board and a pin inserted in a through hole of the circuit board. The circuit board includes a laminated stack including a plurality of non-conductive layers and a plurality of conductive layers. The laminate stack further includes an interposer layer having a plating resist layer. The via is formed through the laminate stack wherein walls of the via are plated with conductive material except where the via passes through the interposer layer, thereby forming a via wall plating discontinuity. The via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. The pin is inserted within the via, wherein the pin is electrically coupled to each of the first and second segments to provide independent electrical connections from each of the first and second segments to the pin.

In yet another aspect, a method of manufacturing a circuit board is disclosed. The method includes forming a first via through the non-conductive layer and plugging the first via with a plating resist, thereby forming a plug assembly. The method also includes laminating a plurality of alternating non-conductive and conductive layers to the first and second surfaces of the plug assembly, thereby forming a laminated stack. The method also includes forming a second via through the laminate stack, wherein the second via passes through the plating resist in the first via, such that a portion of a second via wall includes plating resist at a layer coincident with the plug assembly within the laminate stack. The method also includes performing a electroless plating process to plate the second via wall such that a portion of the plating layer is formed on the portion of the second via wall that includes the plating-resistant resist. The method also includes stripping a portion of the plating formed on the portion of the second via wall that includes plating resist and stripping a portion of the plating resist to form a second via wall plating discontinuity on the second via wall that coincides with the plug assembly within the layer stack. The method also includes performing an electroplating process to further electroplate a remaining portion of the plating on the second via wall while maintaining the second via wall plating discontinuity. In certain embodiments, forming the plug assembly further comprises applying a first conductive layer on a first surface of the non-conductive layer and applying a second conductive layer on a second surface of the non-conductive layer. In some embodiments, the first conductive layer is patterned and the second conductive layer is patterned. In some embodiments, forming the plug assembly further comprises electroplating the first via prior to plugging the first via with the plating resist, thereby forming an electrical interconnection between the first conductive layer and the second conductive layer. In certain embodiments, the method further comprises etching a pattern into the conductive layers in the laminate stack. In some embodiments, the diameter of the first via is greater than the diameter of the second via. In some embodiments, stripping the portion of the plating and stripping the portion of the plating resist to form the second via wall plating discontinuity forms a cavity extending from the second via, wherein the cavity coincides with the plug assembly in the laminate stack. In some embodiments, the second via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the second via, and the second via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. In some embodiments, the second via wall plating includes a first plating stub extending from the first segment and a second plating stub extending from the second segment. In some embodiments, the first plated stub has a defined stub length equal to a thickness of a non-conductive layer between the first segment and the first surface of the plug assembly, and the second plated stub has a defined stub length equal to a thickness of a non-conductive layer between the second segment and the second surface of the plug assembly. In certain embodiments, performing the electroplating process includes applying electricity to the first section and to the second section. In some embodiments, forming the second via includes drilling a single bore through the entirety of the laminate stack.

Brief description of the drawings

Several example embodiments are described with reference to the drawings, wherein like components are provided with like reference numerals. These example embodiments are intended to illustrate, but not to limit, the invention. These drawings include the following figures:

fig. 1 shows a cut-out side view of a portion of a conventional printed circuit board.

Fig. 2 shows a cut-out side view of a portion of two conventional component stacks to be subsequently used to form a printed circuit board.

Fig. 3 illustrates a progressive pressing of the two component stacks of fig. 2.

Fig. 4 shows a cut-out side view of a portion of a conventional printed circuit board with a via back drilled.

Fig. 5 illustrates a cut-out side view of a portion of a printed circuit board according to an embodiment.

Fig. 6-13 illustrate various steps in a selective segment via plating process for manufacturing the printed circuit board of fig. 5.

Fig. 14 illustrates a cut-out side view of a portion of a printed circuit board according to another embodiment.

Fig. 15 illustrates a cut-out side view of a portion of a printed circuit board according to yet another embodiment.

Detailed description of the embodimentsThe following steps are described:

embodiments of the present application relate to a printed circuit board. Those skilled in the art will realize that the following detailed description of a printed circuit board is illustrative only and is not intended to be in any way limiting. Other embodiments of such printed circuit boards will readily suggest themselves to such skilled persons having the benefit of this disclosure.

Reference will now be made in detail to implementations of printed circuit boards as illustrated in the accompanying drawings. Throughout the drawings and the following detailed description, the same reference indicators will be used to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application-and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

Fig. 5 illustrates a cut-out side view of a portion of a printed circuit board according to an embodiment. The printed circuit board 102 is fabricated using a selective segment via plating process, an embodiment of which is described with respect to fig. 6-13. The printed circuit board 102 includes a plurality of stacked layers made of a plurality of

non-conductive layers

104, 106 and a plurality of conductive layers 108. These non-conductive layers may be made of a prepreg or substrate that is part of the core structure. Each exemplary core structure shown in the laminate stack of fig. 5 includes a non-conductive layer 104 (e.g., a substrate) and a conductive layer 108 on each surface of the non-conductive layer 104. It should be understood that alternative core structures may be used that include a conductive layer on only one surface of the non-conductive layer. Plug assembly 140 is a core structure that is plugged with a plating-resistant resist material. A laminated stack is formed by stacking a plurality of core structures with prepregs interposed therebetween and the plug assembly and then laminating the stack. Any conventional lamination technique may be used. The exemplary laminate stack shown in fig. 5 has a two-core structure. It should be understood that the laminate stack may be fabricated to have more or less than two core structures. The vias 110 are formed by drilling holes through the laminated stack and plating the walls of the holes with a conductive material, such as copper. The resulting plated layer 112 interconnects the plurality of selectively conductive layers 108. The plug assembly 140 is selectively positioned during the lamination stack formation process for separating the printed circuit board 102 into the

segments

120 and 130. The plug assembly 140 includes a plating resist 118 that resists formation of the plating layer 112 in the cavities or voids 114 during the plating process. As a result, the plating 112 in segment 120 is disconnected from the plating 112 in segment 130. This results in a via 110 having two electrically

isolated segments

120 and 130. A segment may also be referred to as a net, which is a sub-circuit. Each segment provides independent electrical connection to a pin inserted into the through hole. Thus, the printed circuit board having a plurality of segments is a multi-net structure.

In this embodiment, portions of the plating layer 112, referred to as stubs 116, are left extending from those conductive layers that are closest to the voids 114. These stubs 116 have a well-defined and short stub length SL, which is defined as the distance between the conductive layer 108 closest to the void 114 and the remaining plating resist 118.

The number of layers in PCB 102 and the location of plug assemblies 140 within the layer stack shown in fig. 5 are for exemplary purposes only. This selective segment via plating process allows freedom to interconnect each successive inner conductive layer as separate segments within the same via. In the exemplary configuration shown in fig. 5, the top three conductive layers are interconnected into one segment and the bottom three conductive layers are interconnected into another segment. It should be understood that not all segments need have the same number of interconnected conductive layers. It should also be understood that a segment may have more or less than three interconnected conductive segments. In the exemplary configuration shown in fig. 5, the individual plug assemblies 140 are interspersed within the printed circuit board 102. Alternatively, a plurality of such plugs may be interspersed within the printed circuit board. The inclusion of a plurality of additional plugs results in the formation of a plurality of additional segments.

Fig. 6-13 illustrate various steps in a selective segment via plating process for manufacturing the printed circuit board 102 of fig. 5. Each of fig. 6-13 shows a cut-out side view of a printed circuit board according to various process steps. In fig. 6, an exemplary core structure is shown. The core structure is a metal clad substrate comprising a non-conductive substrate layer 104 and a plurality of conductive layers 108 formed on two opposing surfaces. It should be understood that alternative core structures may be used that include a conductive layer on only one surface of the non-conductive layer.

In fig. 7, holes are drilled through the conductive layers 108 and the core layer 104 to form vias 122. In some embodiments, the walls of the vias 122 are plated, such as with copper. In fig. 8, these conductive layers 108 are etched with a pattern to form a plurality of conductive interconnects as desired. Alternatively, the conductive layers 108 have been etched with a pattern during the fabrication of the core structure in fig. 6. The vias 122 are then filled with plating resist 118 (e.g., liquid photo-sensitive plating resist). It should be understood that other types of plating resist that are resistant to subsequent via wall plating steps may be used. In some embodiments, a portion of the plating resist 118 overlaps portions of the conductive layers 108 around the vias 122. The resulting structure forms the basis of the plug assembly 140.

In fig. 9, a plurality of core structures are fabricated and the core structures and plug assemblies are stacked with a plurality of non-conductive layers 108 in between. In the exemplary configuration shown in fig. 9, additional conductive layers 108 and intervening non-conductive layers 106 are added to the top and bottom of the stack. A single lamination step produces the laminated stack shown in fig. 9. These additional conductive layers 108 on the top and bottom of the laminate stack are etched with a pattern.

In fig. 10, holes are drilled through the laminated stack of fig. 9 to form vias 110. The diameter of the via 110 is smaller than the diameter of the via 122 (fig. 7) plugged with plating resist 118. As a result, the formation of the via 110 leaves a layer of plating resist 118 on the sidewalls of the via 110 in the region of the plug assembly 140.

In fig. 11, a desmear process is performed to remove residue, such as residual particles generated by drilling of the via 110. Next, an electroless plating process is performed to form a plating layer 112' on the sidewalls of the via hole 110. In certain embodiments, copper is used as the plating material. It should be understood that other plating materials may be used. Plating layer 112' forms an interconnect with each conductive layer 108 except in the areas of plug assembly 140 where plating resist 118 provides a barrier. In this region of the plug assembly 140, a plating layer 112' is formed on the plating-resistant resist 118.

In fig. 12, a plating resist stripping resistant process is performed. During the plating resist stripping process, the plating 112' is removed from the region of the plug assembly 140 and a portion of the plating resist 118. The plating layer 112 'deposited during the electroless plating process of fig. 11 is not well deposited onto the plating resist 118, and thus the plating resist 118 is not completely covered with the plating layer 112'. Also, the adhesion between plating layer 112 'and plating resist 118 is less strong than the adhesion between plating layer 112' and other layers exposed within the via. As such, during the plating resist stripping process, the stripping chemistry attacks the plating resist 118 at locations that lack coverage by the plating layer 112'. As the plating resist 118 dissolves, there is no support for the portion of the plating layer 112 'deposited on the plating resist 118, and this portion of the plating layer 112' is removed. The amount of plating resist 118 remaining is left after this plating resist stripping step. The stripping of the portion of plating layer 112 'in plug assembly 140 creates a cavity around the via and a void 114 within plating layer 112'. This discontinuity in the plating 112 'causes the formation of a plurality of plating stubs 116'. However, the stubs 116' are disconnected from the conductive layers 108 in the plug assembly 140, as shown in fig. 12. These conductive layers 108 within the plug assembly 140 are recessed from the vias 110.

In fig. 13, an electroplating process is performed to produce a thicker plating 112 on the sidewalls of the via 110. In certain embodiments, copper is used as the plating material. When the exposed surfaces in void 114 are not electrically connected, there is no plating on the surfaces exposed during the electroplating process, thereby creating electrically

isolated segments

120 and 130.

In some embodiments, the plug is formed without a conductive layer. In this case, a via is drilled into a layer of the core structure non-conductive layer and the via is plugged with the plating resist. A portion of the plating resist may or may not overlap with the non-conductive layer of the core structure around the via. Fig. 14 illustrates a cut-out side view of a portion of a printed circuit board according to another embodiment. The printed circuit board 202 includes a plurality of stacked layers made of a plurality of

non-conductive layers

204, 206 and a plurality of conductive layers 208 laminated into plugs 240 to form a laminated stack with plated vias 210 in a manner similar to that previously described. In contrast to the previous embodiments, the plug 240 is formed without coupling the plurality of conductive layers to either of the opposing surfaces of the non-conductive layers of the core structure. The plugs 240 are formed in a similar manner as the plug assemblies 140 of fig. 6-8, but do not include these conductive layers. The resulting plug 240 is a non-conductive layer of the core structure with a plating resist filled via. In the exemplary embodiment shown in fig. 14, this plating resist stripping step does not completely remove all of the plating resist 218, just enough to form a plurality of voids 214. As a result, the plating layer 212 is not formed in the recessed areas of the voids 214 during the subsequent plating step.

Fig. 14 also demonstrates additional functionality in which the plug is selectively positioned toward the "back side" of the printed circuit board, thereby effectively insulating a selected number of conductive layers (e.g., segment 230) at the back side from segment 220 in a manner similar to backdrilling. However, in the case of a selective segment via electroplating process, the length of the resulting stub 216 is strictly defined and greatly minimized in length relative to the backdrilling process.

As mentioned above, the plug assembly may be configured to include a plating on sidewalls of the via. In this embodiment, the plug may act as a separate segment. Fig. 15 illustrates a cut-out side view of a portion of a printed circuit board according to yet another embodiment. The printed circuit board 302 includes a plurality of stacked layers made of a plurality of

non-conductive layers

304, 306 and a plurality of conductive layers 308 laminated into plugs 340 to form a laminated stack with plated vias 310 in a similar manner as previously described. In this embodiment, the plug is formed in a manner similar to plug assembly 140 of fig. 6-8, except that the via within plug 340 is first plated before being plugged with plating resist. The resulting plug 340 includes a plating layer 313 that forms an interconnect with the conductive layers 308 of the plug 340. This plating resist stripping step does not completely remove all of the plating resist 318, but is sufficient to form a plurality of voids 314. As a result, during the subsequent electroplating step, the plating layer 312 is not formed in the recessed areas of the voids 314, and thus the electrically insulating

segments

320 and 330 are formed. Also, since the conductive layers 308 in the area of the plug 340 are electrically interconnected by the plating 313, the conductive layers in the plug 340 form electrically isolated segments.

It should be understood that the various structural configurations and locations of the plugs shown in the embodiments of fig. 6-15 may be interchanged depending on the particular application and requirements of the application.

The selective segmented via plating process allows for free connection of the inner layers as separate segments within the same via. The selective segment via plating process can replace backdrilling and progressive pressing methods, while achieving the same design as both processes. This saves running costs and shortens PCB processing time. The selective segment via plating process provides a controlled and reproducible stub length that is important to signal transmission integrity, as compared to the uncontrollable stub lengths in conventional backdrilling processes. Plated stubs are conductive portions of the vias that are not connected in series with the circuit. By making it shorter, signal reflection and degradation can be minimized as the signal travels along the via. The elimination of the backdrilling step also conserves unusable real estate on the printed circuit board when the physical size of the drill bit requires increased spacing of adjacent boreholes. This selective segment via plating process requires a single assembly lamination, which gives just via alignment through the entire thickness of the printed circuit board, which provides better overall layer-to-layer registration and thus more room for circuit routing, compared to the progressive lamination method. The selective segment via plating process also supports a one-time drilling step.

The present application has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of flexible printed circuits to which rigid components are attached. Many of the components shown and described in the various figures can be interchanged to achieve the results desired, and this description should be read to include such interchange as well. As such, references herein to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the application.

Claims

1. A circuit board, comprising:

a. a laminate stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminate stack further comprises an interposer plug assembly comprising plating resist, the interposer plug assembly being stacked within an interior of the laminate stack;

b. a via formed through the laminate stack, wherein a via sidewall defined by a surface of the non-conductive layer of the laminate stack defines a via diameter, the via sidewall being plated with a conductive material except where the via passes through the interposer plug assembly, thereby forming a via sidewall plating discontinuity, wherein a surface of the via sidewall plating facing into the via defines a plated via diameter that is less than the via diameter; and

c. a cavity extending laterally from a longitudinal axis of the via at the same layer within the laminate stack as the interposer plug assembly, the cavity defined by cavity sidewalls comprising plating resist and top and bottom surfaces corresponding to layers of the laminate stack adjacently laminated to both sides of the interposer plug assembly, wherein a surface of the plating resist facing the via is recessed from the via sidewalls.

2. The circuit board of claim 1, wherein each of the conductive layers is patterned.

3. The circuit board of claim 1, wherein the via comprises a single bore through the entirety of the laminate stack.

4. The circuit board of claim 1, wherein the via sidewall plating forms a plurality of electrical interconnects with a plurality of conductive layers intersecting the via, and the via sidewall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment.

5. The circuit board of claim 4, wherein the via sidewall plating comprises a first plated stub extending from the first electrical interconnect conductive layer segment and a second plated stub extending from the second electrical interconnect conductive layer segment.

6. The circuit board of claim 5, wherein the first plated stub has a defined stub length equal to a thickness of a non-conductive layer between the first electrically interconnected conductive layer segment and a nearest surface of the interposer plug assembly.

7. The circuit board of claim 5, wherein the second plated stub has a defined stub length equal to a thickness of a non-conductive layer between the second electrically interconnected conductive layer segment and a nearest surface of the interposer plug assembly.

8. The circuit board of claim 1, wherein the interposer plug assembly includes a first surface and a second surface opposite the first surface, an interposer plug assembly via extending from the first surface to the second surface, and the interposer plug assembly via is completely filled with a plating resist, wherein the interposer plug assembly via has a diameter greater than the via diameter, and a via through a printed circuit board is aligned within the interposer plug assembly via diameter.

9. The circuit board of claim 8, wherein a first surface of the interposer plug assembly is laminated to a first non-conductive layer in the laminate stack and a second surface of the interposer plug assembly is laminated to a second non-conductive layer in the laminate stack.

10. A circuit board, comprising:

b. a via formed through the laminate stack, wherein a via sidewall defined by a surface of the non-conductive layer of the laminate stack defines a via diameter, the via sidewall being plated with a conductive material except where the via passes through the interposer plug assembly, wherein a surface of the via sidewall plating facing into the via defines a plated via diameter that is less than the via diameter; and

c. a cavity extending laterally from a longitudinal axis of the via at the same layer within the laminate stack as the interposer plug assembly, the cavity defined by a cavity sidewall comprising plating resist and top and bottom surfaces corresponding to layers of the laminate stack adjacently laminated to both sides of the interposer plug assembly, wherein a surface of the plating resist facing the via is recessed from the via sidewall, wherein the cavity forms a via sidewall plating discontinuity, further wherein the via sidewall plating forms a plurality of electrical interconnects with a plurality of conductive layers intersecting the via and the via sidewall plating discontinuity electrically insulates a first electrical interconnect conductive layer from a second electrical interconnect conductive layer segment, wherein the via sidewall plating comprises a first plating stub extending from the first electrical interconnect conductive layer segment to the cavity and a second plating stub extending from the second electrical interconnect conductive layer segment to the cavity A wire.

11. The circuit board of claim 10, wherein each of the conductive layers is patterned.

12. The circuit board of claim 10, wherein the via comprises a single bore through the entirety of the laminate stack.

13. The circuit board of claim 10, wherein the first plated stub has a defined stub length equal to a thickness of a non-conductive layer between the first electrically interconnected conductive layer segment and a nearest surface of the interposer plug assembly.

14. The circuit board of claim 10, wherein the second plated stub has a defined stub length equal to a thickness of a non-conductive layer between the second electrically interconnected conductive layer segment and a nearest surface of the interposer plug assembly.

15. The circuit board of claim 10, wherein the interposer plug assembly includes a first surface and a second surface opposite the first surface, an interposer plug assembly via extending from the first surface to the second surface, and the interposer plug assembly via is completely filled with a plating resist, wherein the interposer plug assembly via has a diameter greater than the via diameter, and a via through a printed circuit board is aligned within the interposer plug assembly via diameter.

16. The circuit board of claim 15, wherein a first surface of the interposer plug assembly is laminated to a first non-conductive layer in the laminate stack and a second surface of the interposer plug assembly is laminated to a second non-conductive layer in the laminate stack.

17. A multiple network architecture comprising:

a. a circuit board, the circuit board comprising:

i. a laminate stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminate stack further comprises an interposer plug assembly comprising plating resist, the interposer plug assembly being stacked within an interior of the laminate stack;

a via formed through the laminate stack, wherein a via sidewall defined by a surface of a non-conductive layer of the laminate stack defines a via diameter, the via sidewall being plated with a conductive material except where the via passes through the interposer plug assembly, thereby forming a via sidewall plating discontinuity, wherein a surface of the via sidewall plating facing into the via defines a plated via diameter that is less than the via diameter, further wherein the via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers intersecting the via, and the via wall plating discontinuity electrically insulates a first electrical interconnect conductive layer segment from a second electrical interconnect conductive layer segment; and

a cavity extending laterally from a longitudinal axis of the via at the same layer within the laminate stack as the interposer plug assembly, the cavity defined by cavity sidewalls comprising plating resist and top and bottom surfaces corresponding to layers of the laminate stack adjacently laminated to both sides of the interposer plug assembly, wherein a surface of the plating resist facing the via is recessed from the via sidewalls; and

b. a pin inserted within the via, wherein the pin is electrically coupled to each of the first and second electrically interconnected conductive layer segments to provide independent electrical connections from each of the first and second electrically interconnected conductive layer segments to the pin.

18. A method of manufacturing a circuit board, the method comprising:

a. forming a first via through the non-conductive layer and plugging the first via with a plating resist, thereby forming a plug assembly;

b. laminating a plurality of alternating non-conductive and conductive layers to the first and second surfaces of the plug assembly, thereby forming a laminated stack;

c. forming a second via through the laminate stack, wherein the second via passes through the plating resist in the first via, such that a portion of a second via wall includes plating resist at a layer coincident with the plug assembly within the laminate stack;

d. performing an electroless plating process to plate the second via wall such that a portion of the plating thus obtained is formed on the portion of the second via wall comprising the plating-resistant resist;

e. stripping the portion of the plating formed on the portion of the second via wall that includes plating resist and stripping a portion of the plating resist to form a second via wall plating discontinuity on the second via wall that coincides with the plug assembly within the laminate stack; and

f. an electroplating process is performed to further electroplate the remaining portion of the plating on the second via wall while maintaining the second via wall plating discontinuity.

19. The method of claim 18, wherein forming the plug assembly further comprises applying a first conductive layer on a first surface of the non-conductive layer and applying a second conductive layer on a second surface of the non-conductive layer.

20. The method of claim 19, wherein the first conductive layer is patterned and the second conductive layer is patterned.

21. The method of claim 20, wherein forming said plug assembly further comprises electroplating said first via prior to plugging said first via with said plating resist, thereby forming an electrical interconnection between said first conductive layer and said second conductive layer.

22. The method of claim 18, further comprising etching a pattern to the conductive layers in the laminate stack.

23. The method of claim 18, wherein a diameter of the first via is larger than a diameter of the second via.

24. The method of claim 18, wherein stripping the portion of the plating and stripping the portion of the plating resist to form the second via wall plating discontinuity forms a cavity extending from the second via, wherein the cavity coincides with the plug element in the laminate stack.

25. The method of claim 18, wherein the second via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the second via, and the second via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment.

26. The method of claim 25, wherein the second via wall plating comprises a first plating stub extending from the first electrically interconnect conductive layer segment and a second plating stub extending from the second electrically interconnect conductive layer segment.

27. The method of claim 26, the first plated stub having a defined stub length equal to a thickness of a non-conductive layer between the first electrically interconnected conductive layer segment and the first surface of the plug assembly, and the second plated stub having a defined stub length equal to a thickness of a non-conductive layer between the second electrically interconnected conductive layer segment and the second surface of the plug assembly.

28. The method of claim 25, wherein performing the electroplating process comprises applying an electrical current to the first electrical interconnect conductive layer segment and to the second electrical interconnect conductive layer segment.

29. The method of claim 18, wherein forming the second via comprises drilling a single bore through the entirety of the laminate stack.