CN106159082B - The forming method of resistor type random access memory - Google Patents
The forming method of resistor type random access memory Download PDFInfo
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- CN106159082B CN106159082B CN201510131863.7A CN201510131863A CN106159082B CN 106159082 B CN106159082 B CN 106159082B CN 201510131863 A CN201510131863 A CN 201510131863A CN 106159082 B CN106159082 B CN 106159082B
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Abstract
A kind of forming method of resistor type random access memory, comprising: to have the hard mask layer of opening as exposure mask, upper electrode layer is etched using the first dry etch process, until exposing dielectric material layer surface, the etching gas of first dry etch process is CH4；Continue to have the hard mask layer of opening as exposure mask, using the second dry etch process etch dielectric materials layer, until exposing lower electrode layer surface, the etching gas of second dry etch process is H2.The present invention avoids etching technics from causing etching to pollute upper electrode layer and dielectric materials layer, so that upper electrode layer side wall and the cleaning of dielectric materials layer side wall after etching, and then improve the electric property of the resistor type random access memory formed.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, in particular to a kind of forming method of resistor type random access memory.
Background technique
Non- liability memory has the advantages that in non-transformer for remaining to keep data information at once, in area information storage
One of research hotspot with very important status and current information memory technology.It is deposited however, current mainstream is non-volatile
There is the problems such as operation voltage is high, speed is slow, endurance is poor in reservoir flash memory (flash).Resistor type random access memory (RRAM,
Resistance Random Access Memory) show that operating rate is fast, storage density is high, data hold time
Long, the advantages that endurance is strong, be the strong candidate of generation semiconductor memory.
The basic unit of storage of resistor type random access memory includes metal-insulator-metal type (MIM, a Metal-
Insulation-Metal) structural unit.By voltage or current impulse, the resistance of mim structure unit can be made in height electricity
It is converted between resistance state, to realize the write-in and erasing of data.The key of RRAM work is electric resistance changing and the memory of certain materials
Effect, the resistance of these materials can send reversible, huge change under voltage or the function of current.
However, the electric property for the resistor type random access memory that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of resistor type random access memory, solves etching technics to upper
The problem of electrode layer side wall causes etching to pollute, to improve the electric property of resistor type random access memory.
To solve the above problems, the present invention provides a kind of forming method of resistor type random access memory, comprising: provide base
Bottom, the substrate is interior to have lower electrode layer, flushes at the top of the lower electrode layer with substrate surface；In the substrate surface and lower electricity
Pole layer surface forms dielectric materials layer；Upper electrode layer is formed in the dielectric material layer surface；In upper electrode layer surface shape
At hard mask layer；The graphical hard mask layer, forms the opening for exposing upper electrode layer in the hard mask layer；With described
Hard mask layer with opening is exposure mask, the upper electrode layer is etched using the first dry etch process, until exposing dielectric
Material surface, the etching gas of first dry etch process are CH4；It is to cover with the hard mask layer with opening
Film etches the dielectric materials layer using the second dry etch process, until exposing lower electrode layer surface, second dry method
The etching gas of etching technics is H2；The removal hard mask layer with opening.
Optionally, the material of the upper electrode layer is one or more of Ag, W, Pt or Au；The dielectric materials layer
Material is amorphous silicon or polysilicon.
Optionally, the etching cavity temperature of first dry etch process is lower than the etch chamber of the second dry etch process
Room temperature.
Optionally, the etching cavity temperature of first dry etch process is subzero 20 degrees Celsius to 50 degrees Celsius；Institute
The etching cavity temperature for stating the second dry etch process is 60 degrees Celsius to 100 degrees Celsius.
Optionally, the technological parameter of first dry etch process are as follows: CH4Flow is 10sccm to 200sccm, Ar stream
Amount is 10sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 500 millitorrs, and providing source power is 100 watts to 1000 watts, is mentioned
It is 0 watt to 200 watts for bias power, etching cavity temperature is subzero 20 degrees Celsius to 50 degrees Celsius.
Optionally, the technological parameter of second dry etch process are as follows: H2Flow is 50sccm to 500sccm, Ar stream
Amount is 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts,
Etching cavity temperature is 60 degrees Celsius to 100 degrees Celsius.
Optionally, the hard mask layer includes metal hard mask layer and hard positioned at the dielectric layer of metal hard mask layer surface
Mask layer.
Optionally, the metal hard mask layer includes tantalum nitride layer and the titanium nitride layer positioned at tantalum nitride layer surface.
Optionally, the processing step of the graphical hard mask layer includes: using described in third dry etch process etching
The etching gas of dielectric hard mask layer, the third dry etch process includes H2；Institute is etched using the 4th dry etch process
Titanium nitride layer is stated, the etching gas of the 4th dry etch process includes H2；Using described in the 5th dry etch process etching
The etching gas of tantalum nitride layer, the 5th dry etch process includes H2。
Optionally, the material of the medium mask layer is silica；The technological parameter of third dry etch process are as follows: etching
Gas includes H2, CH is also passed through into etching cavity2H2、CHF3And N2, wherein H2Flow is 50sccm to 500sccm, N2Flow
For 10sccm to 500sccm, CH2F2Flow is 10sccm to 100sccm, CHF3Flow is 10sccm to 100sccm, etch chamber
Chamber pressure is 10 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts, and providing bias power is 0 watt to 200 watts.
Optionally, the 4th dry etch process is lock-out pulse etching technics, the technique of lock-out pulse etching technics
Parameter are as follows: H2Flow be 50sccm to 500sccm, Ar flow be 100sccm to 500sccm, etching cavity pressure be 5 millitorrs extremely
200 millitorrs, providing source power is 200 watts to 1000 watts, and the duty ratio of source power is 10% to 90%, and providing bias power is 0
Watt to 200 watts, the duty ratio of bias power is 10% to 90%, and the frequency of source power is 0.1kHz to 100kHz.
Optionally, the technological parameter of the 5th dry etch process are as follows: H2Flow is 50sccm to 500sccm, Ar stream
Amount is 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts,
There is provided bias power is 0 watt to 200 watts.
Optionally, the substrate includes substrate and the etching stop layer positioned at substrate surface, and the lower electrode layer includes:
Bottom metal layer in substrate and the metal barrier positioned at underlying metal layer surface, wherein metal barrier is located at
In etching stop layer, and flushed at the top of metal barrier with etching stopping layer surface.
Optionally, the material of the etching stop layer is silicon nitride, silicon nitride or the silicon carbide of carbon dope.
Optionally, the material of the bottom metal layer is Cu, Al or W；The material of the metal barrier is Ta, Ti, TaN
Or TiN.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of resistor type random access memory provided by the invention, in substrate surface and lower electrode
Layer surface forms dielectric materials layer, forms upper electrode layer, in upper electrode layer surface formation hard mask layer in dielectric material layer surface
Afterwards, the graphical hard mask layer, forms the opening for exposing upper electrode layer in the hard mask layer；There is opening with described
Hard mask layer be exposure mask, upper electrode layer, and quarter of first dry etch process are etched using the first dry etch process
Erosion gas is CH4.During the first dry etch process, the material and CH of upper electrode layer4Chemical reaction occurs to form reaction
By-product, gas (such as CH of the byproduct of reaction in mobility4, gaseous byproduct of reaction) drive under leave etch chamber
Room avoids the upper electrode layer sidewall surfaces of the byproduct of reaction attachment after etching, so that the upper electrode layer after etching has
Clean sidewall surfaces, while the byproduct of reaction being avoided to be attached to dielectric material layer surface.
Likewise, during etch dielectric materials layer, the material and H of dielectric materials layer2It reacts to form reaction
By-product, the byproduct of reaction will also leave in etching cavity, avoid the upper electrode layer of byproduct of reaction attachment after etching
With dielectric materials layer sidewall surfaces.For this purpose, the present invention avoid to after etching upper electrode layer and dielectric materials layer cause to etch
Pollution so that the upper electrode layer and dielectric materials layer after etching have clean sidewall surfaces, thus improve the resistance-type of formation with
The electric property of machine memory.
Further, the etching cavity temperature of the first dry etch process is lower, is subzero 20 degrees Celsius to 50 degrees Celsius, keeps away
Exempt from the first dry etch process dielectric materials layer is caused to etch, to improve the first dry etch process to upper electrode layer and Jie
Etching selection ratio between the material of material layer, so that the first upper electrode layer after etching has good side wall pattern.
Further, the etching cavity temperature of the second dry etch process is higher, is 60 degrees Celsius to 100 degrees Celsius, makes
The etch period for obtaining the second dry etch process is shorter, avoids the second dry etch process from causing etching stop layer unnecessary
Etching, and then lower electrode layer is prevented to be exposed.
Detailed description of the invention
Fig. 1 to Figure 11 is the cross-section structure signal for the resistor type random access memory forming process that one embodiment of the invention provides
Figure.
Specific embodiment
It can be seen from background technology that the electric property for the resistor type random access memory that the prior art is formed is to be improved.
It has been investigated that the prior art generallys use after formation is covered in the upper electrode layer of dielectric material layer surface
The method of physical sputtering bombardment, with the graphical upper electrode layer and dielectric materials layer, the bombardment of the physical sputtering bombardment
Source is Ar plasma, forms opening in upper electrode layer and dielectric materials layer under Ar plasma bombardment.However, due to
Under the physical sputtering bombardment, metal ion or the metal ion group of upper electrode layer are detached from upper electrode layer, Jie of dielectric materials layer
Matter ion or medium ionic group are detached from dielectric materials layer；Due to lacking the gas of mobility in the etching cavity of physical sputtering bombardment
Body, the metal ion, metal ion group, medium ionic or medium ionic group are difficult to leave etch chamber by mobility gas
Room causes the ion or ion cluster to be easy to fall upper electrode layer and dielectric materials layer sidewall surfaces after etching.Also, by
There is relatively large quality, under the effect of gravity, the metal ion or metal in usual metal ion or metal ion group
Ion cluster is more difficult to leave etching cavity, so that a large amount of metal ion or metal ion group fall powering on after etching
Pole layer and dielectric materials layer side wall, to after etching upper electrode layer and dielectric materials layer side wall pollute.
Simultaneously as during etch dielectric materials layer, dielectric material layer surface be easy to be populated with metal ion or
Metal ion group, the metal ion or metal ion group will affect the etching to dielectric materials layer, further to dielectric material
Layer pollutes, and the electric property so as to cause the resistor type random access memory of formation is low.
To solve the above problems, the present invention provides a kind of forming method of resistor type random access memory, with what is be specifically open
Hard mask layer is exposure mask, etches upper electrode layer using the first dry etch process, etching gas includes CH4, in etching process
The material and CH of upper electrode layer4It reacts to form byproduct of reaction, the byproduct of reaction is as etching gas is in etch chamber
It is indoor flowing and leave etching cavity, avoid polluting the upper electrode layer side wall after etching, avoid to dielectric materials layer
It pollutes；Then the second dry etch process etch dielectric materials layer is used, etching gas includes H2, the material of dielectric materials layer
Material and H2It reacts to form byproduct of reaction, the byproduct of reaction also will be as etching gas be in the indoor flowing of etch chamber
And etching cavity is left, it avoids polluting the dielectric materials layer side wall after etching.For this purpose, powering on after being etched in the present invention
The side wall pollution of pole layer and dielectric materials layer is few, so that the upper electrode layer and dielectric materials layer after etching keep higher property
Can, to improve the electric property of the resistor type random access memory of formation.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 11 is the cross-section structure signal for the resistor type random access memory forming process that one embodiment of the invention provides
Figure.
Referring to FIG. 1, providing substrate 100, bottom metal layer 101 is formed in the substrate 100.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium；The substrate 100 may be used also
Think the silicon substrate on insulator.
In the present embodiment, the material of the substrate 100 is silicon.
As a specific embodiment, the processing step for forming bottom metal layer 101 includes: offer initial substrate；Institute
It states initial substrate surface and forms patterned mask layer；Using the patterned mask layer as exposure mask, in the initial substrate
Damascus opening is formed, the substrate 100 with Damascus opening is formed；Form the bottom of the full Damascus opening of filling
Layer metal film, the underlying metal film are also covered in 100 surface of substrate；Grinding removal is located at the underlying metal on 100 surface of substrate
Film, forms the bottom metal layer 101 for filling full Damascus opening, and 101 top of bottom metal layer is neat with 100 surface of substrate
It is flat.
Damascus opening is single Damascus opening or dual damascene openings；The present embodiment is with the damascene
Leather opening is exemplary illustrated to do for dual damascene openings.
The material of the bottom metal layer 101 is Cu, Al or W.The material of bottom metal layer 101 described in the present embodiment is
Cu。
In the present embodiment, during forming bottom metal layer 101, conduction can also be formed in substrate 100
Metal layer 121, the conductive metal layer 121 is formed simultaneously with bottom metal layer 101 and material is identical.
Referring to FIG. 2, forming etching stop layer 102 on 100 surface of substrate, formed in the etching stop layer 102
There is metal barrier 103, and 103 top of the metal barrier is flushed with 102 surface of etching stop layer.
In the present embodiment, substrate is provided, there is lower electrode layer, the lower electrode layer top and substrate surface in the substrate
It flushes, wherein substrate includes substrate 100 and the etching stop layer 102 positioned at 100 surface of substrate, the lower electrode layer include:
Bottom metal layer 101 in substrate 100 and the metal barrier 103 positioned at 101 surface of bottom metal layer, wherein gold
Belong to barrier layer 103 to be located in etching stop layer 102, and 103 top of metal barrier is flushed with 102 surface of etching stop layer.?
In other embodiments, lower electrode layer can also only include bottom metal layer, and substrate only includes substrate.
The material of the etching stop layer 102 is silicon nitride (NDC), silicon nitride or the silicon carbide of carbon dope；In the present embodiment
The material of etching stop layer 102 is the silicon nitride of carbon dope.
On the one hand, etching stop layer 102 is avoided that subsequent etching processes cause unnecessary quarter to conductive metal layer 121
Erosion；Another party, the etching stop layer 102 are to form metal barrier 103 to provide Process ba- sis, formation and bottom metal layer
The metal barrier 103 of 101 electrical connections, the bottom metal layer 101 and the metal barrier positioned at 101 surface of bottom metal layer
103 are used as lower electrode layer.
The material of the metal barrier 103 is Ti, Ta, TiN or TaN.The metal barrier 103, which plays, prevents bottom
Metal ion in metal layer 101 diffuses to the effect in the dielectric materials layer being subsequently formed, so that the dielectric material being subsequently formed
The bed of material keeps good performance, and then improves the electric property of the resistor type random access memory formed.
In one embodiment, the processing step for forming the metal barrier 103 includes: to be covered in substrate in formation
After the etching stop layer 102 on 100 surfaces, patterned mask layer is formed on 102 surface of etching stop layer；With the figure
The mask layer of shape is exposure mask, etches the etching stop layer 102 1 and forms the groove for exposing 101 surface of bottom metal layer；
The metal barrier film for filling the full groove is formed, the metal barrier film is also covered in 102 surface of etching stop layer；Planarization
Removal is located at the metal barrier film on 102 surface of etching stop layer, forms the metal barrier 103 for filling full groove.
The metal barrier 103 is formed using Metallo-Organic Chemical Vapor deposition or physical gas-phase deposition.This reality
The material for applying metal barrier 103 described in example is TiN.
Referring to FIG. 3, forming dielectric materials layer 104 in the substrate surface and lower electrode layer surface；In the dielectric material
104 surface of the bed of material forms upper electrode layer 105.
The insulating medium layer that the dielectric materials layer 104 plays lower electrode layer between the upper electrode layer 105 that is subsequently formed
Effect, the material of the dielectric materials layer 104 is the material with electricity induction resistive characteristic, and so-called electricity induction refers to material
Resistance can change under specific external signal, and will not restore because of removing for electric signal after material change in resistance；
And the resistance of material is reversible, and applying a form of electric signal can make the resistance of material become smaller, and applies another shape
The electric signal of formula can make resistance value become larger to be restored to high resistant again.
The material of the dielectric materials layer 104 is amorphous silicon, polysilicon, copper oxide, aluminium oxide, titanium oxide, five oxidations two
Niobium or zirconium oxide.In the present embodiment, the material of the dielectric materials layer 104 is amorphous silicon.
The dielectric materials layer 104 is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.
The material of the upper electrode layer 105 is one or more of Ag, Au, W or Pt, using Metallo-Organic Chemical Vapor
Deposition or physical gas-phase deposition form the upper electrode layer 105.
The material of upper electrode layer 105 described in the present embodiment is Ag, is formed using Metallo-Organic Chemical Vapor depositing operation
The upper electrode layer 105.
Referring to FIG. 4, forming hard mask layer on 105 surface of upper electrode layer.
The hard mask layer is single layer structure or laminated construction.In order to improve improve subsequent etching after upper electrode layer and
Dielectric materials layer sidewall profile, hard mask layer is laminated construction in the present embodiment, and the hard mask layer includes metal hard mask layer
And the dielectric hard mask layer 108 positioned at metal hard mask layer surface.
The material of the dielectric hard mask layer 108 is silica, silicon nitride or silicon oxynitride.Medium described in the present embodiment
The material of hard mask layer 108 is silica.
The metal hard mask layer is single layer structure or laminated construction, and metal hard mask layer described in the present embodiment includes nitrogen
Change tantalum layer 106 and the titanium nitride layer 107 positioned at 106 surface of tantalum nitride layer.The advantages of this arrangement are as follows:
On the one hand, subsequent in the technical process of etch media hard mask layer 108, the etching technics is to silica and nitrogen
Changing titanium has very high etching selection ratio, so that the dielectric hard mask layer 108 after etching has good etch topography.
On the other hand, due to usually in the technical process of etch nitride titanium, the etching gas of the etching technics includes
O2, and O2It is easy to react with the materials from oxidizing of upper electrode layer 105, if being in contact with titanium nitride layer 107 is upper electrode layer
105, then the material of upper electrode layer 105 will be easily oxidized；And the present embodiment is in titanium nitride layer 107 and upper electrode layer 105
Between there is tantalum nitride layer 106, the tantalum nitride layer 106 avoids O2It is in contact with upper electrode layer 105；Simultaneously as it is subsequent
In the etching process of etch nitride tantalum layer 106, the etching gas of the etching technics is H2, H2It will not be to upper electrode layer 105
Cause oxidation corrosion.
In a specific embodiment, the titanium nitride layer 107 with a thickness of 100 angstroms to 500 angstroms, the tantalum nitride layer
106 with a thickness of 50 angstroms to 250 angstroms.
Referring to FIG. 5, forming patterned photoresist layer 109 on the hard mask layer surface.
Specifically, forming photoresist film on the hard mask layer surface；To the photoresist film be exposed processing and
Development treatment, to form patterned photoresist layer 109 on the hard mask layer surface.The patterned photoresist layer 109
Positioned at the surface of subsequent resistor type random access memory to be formed, and the medium exposed above bottom conductive layer 121 is hard
Mask layer 108.
In order to improve formation patterned photoresist layer 109 pattern, between the hard mask layer and photoresist film
It can also be formed with bottom anti-reflective figure layer, top anti-reflective figure layer can also be formed on the photoresist film surface.
Referring to FIG. 6, with the patterned photoresist layer 109 (referring to Fig. 5) for exposure mask, using third dry etching work
Skill etches the dielectric hard mask layer 108, is formed in the dielectric hard mask layer 108 and exposes metal hard mask layer surface
First opening 110.
First 110 bottom-exposeds of opening described in the present embodiment go out 107 surface of titanium nitride layer, the medium mask layer 108
Material be silica.Since third dry etch process is to etching selection ratio with higher between silica and titanium nitride,
Therefore the third dry etch process is very small to the etching injury on 107 surface of titanium nitride layer, and the first opening 110 formed
With good pattern.
The etching gas of the third dry etch process is H2.As a specific embodiment, third dry etching work
The technological parameter of skill are as follows: etching gas includes H2, CH is also passed through into etching cavity2H2、CHF3And N2, wherein H2Flow is
50sccm to 500sccm, N2Flow is 10sccm to 500sccm, CH2F2Flow is 10sccm to 100sccm, CHF3Flow is
10sccm to 100sccm, etching cavity pressure are 10 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts, are provided
Bias power is 0 watt to 200 watts.
Referring to FIG. 7, being used with the dielectric hard mask layer 108 with the first opening 110 (with reference to Fig. 6) for exposure mask
4th dry etch process etches the titanium nitride layer 107, is formed in the titanium nitride layer 107 and exposes tantalum nitride layer 106
Second opening 111 on surface.
In the present embodiment, the etching gas of the 4th dry etch process is H2.4th dry etch process is to titanium nitride layer
107 etch rate is greater than the etch rate to tantalum nitride layer 106, and the 4th dry etch process is avoided to make tantalum nitride layer 106
At over etching, so that the upper electrode layer 105 for being located at 106 lower section of tantalum nitride layer be prevented to be exposed.
In order to improve the 4th dry etch process to the etching selection ratio between titanium nitride layer 107 and 106 layers of tantalum nitride, originally
In embodiment, the 4th dry etch process is lock-out pulse etching.
As a specific embodiment, the technological parameter of the 4th dry etch process are as follows: H2Flow be 50sccm extremely
500sccm, Ar flow are 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200
Watt to 1000 watts, the duty ratio of source power is 10% to 90%, and providing bias power is 0 watt to 200 watts, the duty of bias power
Than being 10% to 90%, the frequency of source power is 0.1kHz to 100kHz.
Referring to FIG. 8, with the titanium nitride layer 107 with the second opening 111 (with reference to Fig. 7) for exposure mask, using the 5th
Dry etch process etches the tantalum nitride layer 106, is formed in the tantalum nitride layer 106 and exposes 105 surface of upper electrode layer
Third opening 112.
The etching gas of 5th dry etch process is H2, can also be to quarter during five dry etch process
Diluent gas is passed through in erosion chamber, the diluent gas is He or Ar.
As a specific embodiment, the technological parameter of the 5th dry etch process are as follows: H2Flow be 50sccm extremely
500sccm, Ar flow are 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200
Watt to 1000 watts, providing bias power is 0 watt to 200 watts.
In the present embodiment, graphical hard mask layer forms in the hard mask layer and exposes opening for upper electrode layer 105
Mouthful, the opening includes the first opening 110 (referring to Fig. 6), the second opening 111 (referring to Fig. 7) and third opening 112.
Since the etching gas of the 5th dry etch process is H2, the H2Upper electrode layer 105 will not be caused to aoxidize, and
And the material of H2 and tantalum nitride layer 106 reacts and forms byproduct of reaction, the byproduct of reaction is with H2 in etching cavity
Interior flowing and be carried over etching cavity, so that etch product be avoided to remain in 105 surface of upper electrode layer, avoid subsequent quarter
The technology difficulty for losing upper electrode layer 105 increases, while preventing from causing upper electrode layer 105 etching to pollute.
Also, third dry etch process, the 4th dry etch process and the 5th dry etch process in the present embodiment
Etching gas be H2, by adjusting H2The process conditions such as gas flow, etching cavity pressure, etching cavity temperature
Third dry etch process, the 4th dry etch process and the 5th dry etch process are completed, so that the shape of semiconductor devices
It is more simple at technique.
Referring to FIG. 9, using the hard mask layer with opening as exposure mask, using described in the first dry etch process etching
Upper electrode layer 105 forms the 4th opening 113 for exposing dielectric materials layer 104 in the upper electrode layer 105.
In the present embodiment, the etching gas of first dry etch process is CH4, can also be to the first dry etching work
The strong interior of the etching of skill is passed through diluent gas, and the diluent gas is one or both of Ar or He.
During the first dry etch process, CH4It can be generated with 105 material of upper electrode layer of etching and react formation reaction
By-product；And the gas (such as etching gas, diluent gas, gaseous byproduct of reaction) flowed in etching process can incite somebody to action
The byproduct of reaction takes etching cavity out of, and byproduct of reaction is avoided to fall in etching cavity, to avoid anti-after etching
105 side wall of upper electrode layer of by-product attachment after etching is answered, so that the sidewall profile of the upper electrode layer 105 after etching is improved,
Optimize the electric property of resistor type random access memory；And it can be avoided byproduct of reaction and be attached to 104 surface of dielectric materials layer,
It improves so that dielectric materials layer 104 keeps good performance, avoids polluting dielectric materials layer 104.
If directlying adopt the method that Ar carries out physical bombardment to upper electrode layer, when forming the 4th opening in upper electrode layer,
Metal ion or the metal ion group of upper electrode layer by physical bombardment can be detached from from upper electrode layer；And due to metal ion or
The quality of metal ion group is larger, and metal ion or metal ion group majority are on-gaseous, and there is no streams in etching cavity
Dynamic gas, therefore the metal ion or metal ion group would become hard to escape out of etching cavity, finally under the effect of gravity,
The metal ion or metal ion group will fall off the upper electrode layer sidewall surfaces of attachment after etching, to the top electrode after etching
Layer pollutes.Also, since metal ion or metal ion group would also adhere to dielectric material layer surface, these metal ions
Or metal ion group can also pollute dielectric materials layer.
It is amorphous silicon, CH due to being located at the material of dielectric materials layer 104 of 105 lower section of upper electrode layer in the present embodiment4It is right
Amorphous silicon will also result in certain etching；If the etching cavity temperature of the first dry etch process is excessively high, then described first is dry
Method etching technics also will be bigger to the etch rate of dielectric materials layer 104, so that the first dry etch process is to upper electrode layer
Etch selectivity between 105 and 104 material of dielectric materials layer is poor, the quarter of the upper electrode layer 105 after be easy to causeing etching
It is poor to lose pattern.
The first dry etch process described in the present embodiment has lower etching cavity temperature thus, so that the dry method
Etching technics is to etching selection ratio with higher between 104 material of 105 material of upper electrode layer and dielectric materials layer, so that first
Dry etch process to the etch rate of dielectric materials layer 104 as far as possible small, upper electrode layer 105 after further increasing etching
Pattern.The etching cavity temperature of first dry etch process is subzero 20 degrees Celsius to 50 degrees Celsius.Also, due to this reality
It applies in example, the etching gas of the first dry etch process is CH4, under lower etching cavity temperature environment, CH4Still to upper
Electrode layer 105 has sufficiently large etch rate, to effectively improve the production efficiency of semiconductor devices.
In a specific embodiment, the technological parameter of first dry etch process are as follows: CH4Flow be 10sccm extremely
200sccm, Ar flow are 10sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 500 millitorrs, and providing source power is 100
Watt to 1000 watts, providing bias power is 0 watt to 200 watts, and etching cavity temperature is subzero 20 degrees Celsius to 50 degrees Celsius.
Diluent gas can also be passed through into etching cavity, diluent gas is one or both of He or Ar.
Referring to FIG. 10, continuing to carve using the hard mask layer with opening as exposure mask using the second dry etch process
The dielectric materials layer 104 is lost, forms the 5th opening for exposing etching stop layer 102 in the dielectric materials layer 104
114。
The etching gas of the second dry etch process of the present embodiment is H2, can also be to the etching of the second dry etch process
Chamber is passed through diluent gas within doors, and the diluent gas is one or both of Ar or He.In the second dry etch process mistake
Cheng Zhong, H2It can react to form byproduct of reaction with 104 material of dielectric materials layer of etching, the byproduct of reaction is carried over
In etching cavity, byproduct of reaction is avoided to pollute dielectric materials layer 104, so that the dielectric materials layer 104 after etching is still
It is with good performance.
In the present embodiment, the etching cavity temperature of the second dry etch process is greater than the etch chamber of the first dry etch process
Room temperature.This is because: the etching technics also can be to etching stop layer in the technical process of etch dielectric materials layer 104
102 cause to etch；If the etching cavity temperature of the second dry etch process is too low, then the etching technics etch dielectric materials
Time needed for layer 104 will be long, is easy to cause over etching to etching stop layer 102.Also, the second dry etch process
When etching cavity temperature is higher, the etching technics selects the etching between 102 material of dielectric materials layer 104 and etching stop layer
Selecting will be bigger than also, also can be avoided and causes over etching to etching stop layer 102.
The etching cavity temperature of second dry etch process is 60 degrees Celsius to 100 degrees Celsius.
As a specific embodiment, the technological parameter of second dry etch process are as follows: H2Flow be 50sccm extremely
500sccm, Ar flow are 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200
Watt to 1000 watts, etching cavity temperature is 60 degrees Celsius to 100 degrees Celsius.
Diluent gas can also be passed through into etching cavity, the diluent gas is one or both of He or Ar.
Figure 11 is please referred to, after etching the upper electrode layer 105 and dielectric materials layer 104, the medium is removed and covers
Film layer 108 (referring to Figure 10), titanium nitride layer 107 (referring to Figure 10) and tantalum nitride layer 106 (referring to Figure 10).
In one embodiment, the medium mask layer 108, titanium nitride layer 107 are removed using wet-etching technology etching
And tantalum nitride layer 106.
Since the present embodiment avoids physical sputtering bombardment to pollution caused by upper electrode layer 105 and dielectric materials layer 104,
So that the upper electrode layer 105 and 104 side wall cleannes of dielectric materials layer after etching are high, upper electrode layer 105 and Jie after etching
Material layer 104 has good pattern, so that the electric property of the resistor type random access memory formed is excellent.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of resistor type random access memory characterized by comprising
Substrate is provided, there is lower electrode layer in the substrate, flushed at the top of the lower electrode layer with substrate surface；
Dielectric materials layer is formed in the substrate surface and lower electrode layer surface；
Upper electrode layer is formed in the dielectric material layer surface；
Hard mask layer is formed on the upper electrode layer surface；
The graphical hard mask layer, forms the opening for exposing upper electrode layer in the hard mask layer；
Using the hard mask layer with opening as exposure mask, the upper electrode layer is etched using the first dry etch process, until
Dielectric material layer surface is exposed, the etching gas of first dry etch process is CH4；
Using the hard mask layer with opening as exposure mask, the dielectric materials layer is etched using the second dry etch process, directly
To lower electrode layer surface is exposed, the etching gas of second dry etch process is H2；
The removal hard mask layer with opening.
2. the forming method of resistor type random access memory according to claim 1, which is characterized in that the upper electrode layer
Material is one or more of Ag, W, Pt or Au；The material of the dielectric materials layer is amorphous silicon or polysilicon.
3. the forming method of resistor type random access memory according to claim 1 or 2, which is characterized in that described first is dry
The etching cavity temperature of method etching technics is lower than the etching cavity temperature of the second dry etch process.
4. the forming method of resistor type random access memory according to claim 3, which is characterized in that first dry method is carved
The etching cavity temperature of etching technique is subzero 20 degrees Celsius to 50 degrees Celsius；The etch chamber room temperature of second dry etch process
Degree is 60 degrees Celsius to 100 degrees Celsius.
5. the forming method of resistor type random access memory according to claim 3, which is characterized in that first dry method is carved
The technological parameter of etching technique are as follows: CH4Flow is 10sccm to 200sccm, and Ar flow is 10sccm to 500sccm, etching cavity
Pressure is 5 millitorrs to 500 millitorrs, and providing source power is 100 watts to 1000 watts, and providing bias power is 0 watt to 200 watts, etching
Chamber temp is subzero 20 degrees Celsius to 50 degrees Celsius.
6. the forming method of resistor type random access memory according to claim 3, which is characterized in that second dry method is carved
The technological parameter of etching technique are as follows: H2Flow is 50sccm to 500sccm, and Ar flow is 100sccm to 500sccm, etching cavity
Pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts, and etching cavity temperature is 60 degrees Celsius to 100 and takes the photograph
Family name's degree.
7. the forming method of resistor type random access memory according to claim 1, which is characterized in that the hard mask layer packet
Include metal hard mask layer and the dielectric layer hard mask layer positioned at metal hard mask layer surface.
8. the forming method of resistor type random access memory according to claim 7, which is characterized in that the metal hard mask
Layer includes tantalum nitride layer and the titanium nitride layer positioned at tantalum nitride layer surface.
9. the forming method of resistor type random access memory according to claim 8, which is characterized in that graphically described to cover firmly
The processing step of film layer includes: to etch the dielectric hard mask layer, the third dry etching using third dry etch process
The etching gas of technique includes H2；The titanium nitride layer, the 4th dry etching work are etched using the 4th dry etch process
The etching gas of skill includes H2；The tantalum nitride layer, the 5th dry etch process are etched using the 5th dry etch process
Etching gas include H2。
10. the forming method of resistor type random access memory according to claim 9, which is characterized in that the medium exposure mask
The material of layer is silica；The technological parameter of third dry etch process are as follows: etching gas includes H2, lead to also into etching cavity
Enter CH2H2、CHF3And N2, wherein H2Flow is 50sccm to 500sccm, N2Flow is 10sccm to 500sccm, CH2F2Flow
For 10sccm to 100sccm, CHF3Flow is 10sccm to 100sccm, and etching cavity pressure is 10 millitorrs to 200 millitorrs, is mentioned
It is 200 watts to 1000 watts for source power, providing bias power is 0 watt to 200 watts.
11. the forming method of resistor type random access memory according to claim 9, which is characterized in that the 4th dry method
Etching technics is lock-out pulse etching technics, the technological parameter of lock-out pulse etching technics are as follows: H2Flow be 50sccm extremely
500sccm, Ar flow are 100sccm to 500sccm, and etching cavity pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200
Watt to 1000 watts, the duty ratio of source power is 10% to 90%, and providing bias power is 0 watt to 200 watts, the duty of bias power
Than being 10% to 90%, the frequency of source power is 0.1kHz to 100kHz.
12. the forming method of resistor type random access memory according to claim 9, which is characterized in that the 5th dry method
The technological parameter of etching technics are as follows: H2Flow is 50sccm to 500sccm, and Ar flow is 100sccm to 500sccm, etch chamber
Chamber pressure is 5 millitorrs to 200 millitorrs, and providing source power is 200 watts to 1000 watts, and providing bias power is 0 watt to 200 watts.
13. the forming method of resistor type random access memory according to claim 1, which is characterized in that the substrate includes
Substrate and etching stop layer positioned at substrate surface, the lower electrode layer include: bottom metal layer in substrate and
Positioned at the metal barrier of underlying metal layer surface, wherein metal barrier is located in etching stop layer, and metal barrier top
Portion is flushed with etching stopping layer surface.
14. the forming method of resistor type random access memory according to claim 13, which is characterized in that the etching stopping
The material of layer is silicon nitride, silicon nitride or the silicon carbide of carbon dope.
15. the forming method of resistor type random access memory according to claim 13, which is characterized in that the underlying metal
The material of layer is Cu, Al or W；The material of the metal barrier is Ta, Ti, TaN or TiN.
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| CN101901868A (en) * | 2009-05-27 | 2010-12-01 | 佳能安内华股份有限公司 | Method and apparatus for fabricating magnetic devices |
| CN102315385A (en) * | 2010-07-06 | 2012-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method for making storage unit of phase-change random access memory |
| CN102751437A (en) * | 2012-07-03 | 2012-10-24 | 北京有色金属研究总院 | Electric-activation-free resistive random access memory and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101901868A (en) * | 2009-05-27 | 2010-12-01 | 佳能安内华股份有限公司 | Method and apparatus for fabricating magnetic devices |
| CN102315385A (en) * | 2010-07-06 | 2012-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method for making storage unit of phase-change random access memory |
| CN102751437A (en) * | 2012-07-03 | 2012-10-24 | 北京有色金属研究总院 | Electric-activation-free resistive random access memory and preparation method thereof |
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