CN106129126A - A kind of trench schottky diode and preparation method thereof - Google Patents
A kind of trench schottky diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 6
- 238000002513 implantation Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 230000000873 masking effect Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 239000013049 sediment Substances 0.000 claims 10
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000001259 photo etching Methods 0.000 claims 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims 1
- 241000446313 Lamella Species 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000003292 glue Substances 0.000 claims 1
- 238000001459 lithography Methods 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical group C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 abstract description 20
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000543 intermediate Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
- H10D8/605—Schottky-barrier diodes of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/051—Manufacture or treatment of Schottky diodes
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Abstract
本发明公开了一种沟槽肖特基二极管，包括沟槽，且所述沟槽的侧壁外侧设有N型注入区，且所述沟槽的底部设有P型注入区。发明给出了一种沟槽肖特基二极管(TMBS)结构及其制造方法。相对于常规TMBS：其提高了耐压、减小了正向压降、提高了开关速度、减小了反向电容。
The invention discloses a trench Schottky diode, which comprises a trench, and an N-type implantation region is arranged outside the side wall of the trench, and a P-type implantation region is arranged at the bottom of the trench. The invention provides a trench Schottky diode (TMBS) structure and a manufacturing method thereof. Compared with conventional TMBS: It improves the withstand voltage, reduces the forward voltage drop, improves the switching speed, and reduces the reverse capacitance.
Description
技术领域technical field
本发明涉及半导体领域，更确切地说是一种沟槽肖特基二极管及其制备方法。The invention relates to the field of semiconductors, more specifically a trench Schottky diode and a preparation method thereof.
背景技术Background technique
常规TMBS的结构，在反向偏置时，沟槽处的耗尽层宽度展宽使相邻的沟槽间的耗尽层连接在一起，使得在纵向方向上的耗尽层宽度大大增加，增大TMBS的反向击穿。但该结构在沟槽底部的耗尽层没有横向耗尽层展宽带来的耗尽层宽度增加的效果，所以在沟槽底部存在大电场，常规沟槽TMBS结构的反向击穿通常都发生在这个位置。In the conventional TMBS structure, when the reverse bias is applied, the width of the depletion layer at the trench widens to connect the depletion layers between adjacent trenches, so that the width of the depletion layer in the longitudinal direction is greatly increased, increasing Reverse breakdown of large TMBS. However, the depletion layer at the bottom of the trench does not have the effect of increasing the width of the depletion layer caused by the widening of the lateral depletion layer, so there is a large electric field at the bottom of the trench, and the reverse breakdown of the conventional trench TMBS structure usually occurs in this position.
传统TMBS的问题，就是在沟槽底部存在电场集中效应，限制器件的反向击穿电压的进一步提升The problem with traditional TMBS is that there is an electric field concentration effect at the bottom of the trench, which limits the further improvement of the reverse breakdown voltage of the device.
发明内容Contents of the invention
本发明的目的是提供一种沟槽肖特基二极管及其制备方法，其可以解决现有技术中反向击穿电压差的缺点。The purpose of the present invention is to provide a trench Schottky diode and its preparation method, which can solve the disadvantage of reverse breakdown voltage difference in the prior art.
本发明采用以下技术方案：The present invention adopts following technical scheme:
一种沟槽肖特基二极管，包括沟槽，且所述沟槽的侧壁外侧设有N型注入区，且所述沟槽的底部设有P型注入区。A trench Schottky diode comprises a trench, and an N-type implantation region is provided outside the sidewall of the trench, and a P-type implantation region is provided at the bottom of the trench.
还包括一基片层，且所述基片层的一侧设有一外延层，所述沟槽设于所述外延层内。It also includes a substrate layer, and one side of the substrate layer is provided with an epitaxial layer, and the groove is arranged in the epitaxial layer.
所述沟槽包括若干第一沟槽及终端区沟槽，且所述终端区沟槽设于所述外延层的边缘。The trenches include a plurality of first trenches and terminal zone trenches, and the terminal zone trenches are arranged on the edge of the epitaxial layer.
所述第一沟槽内生长有栅氧化层及淀设有多晶硅，且多晶硅将第一沟槽淀设满，栅氧化层生长于第一沟槽的侧壁和底部。A gate oxide layer is grown in the first trench and polysilicon is deposited, and the polysilicon is deposited to fill the first trench, and the gate oxide layer is grown on the sidewall and bottom of the first trench.
所述终端区沟槽的侧壁和底部生长有栅氧化层，所述栅氧化层上淀设有多晶硅栅，且多晶硅栅淀设于所述终端区沟槽的侧壁及底部外围上；一氧化物层淀设于多晶硅栅上，且氧化物层淀设于终端区沟槽的侧壁及底部外围，且未淀设满所述沟端区沟槽。A gate oxide layer is grown on the sidewall and bottom of the trench in the termination region, and a polysilicon gate is deposited on the gate oxide layer, and the polysilicon gate is deposited on the sidewall and bottom periphery of the trench in the termination region; The oxide layer is deposited on the polysilicon gate, and the oxide layer is deposited on the sidewall and the bottom periphery of the trench in the terminal region, and the trench in the terminal region is not deposited.
所述栅氧化层还淀设于所述边缘部分的外延层上，所述氧化物层淀设于终端区的多晶硅和栅氧化层的上方。The gate oxide layer is also deposited on the epitaxial layer in the edge portion, and the oxide layer is deposited over the polysilicon and gate oxide layer in the termination region.
还包括第一金属层，其淀设于外延层、所述第一沟槽上，且终端区的氧化物层上，且第一金属层淀设于所述终端区沟槽的侧壁及底部一半。It also includes a first metal layer deposited on the epitaxial layer, on the first trench, and on the oxide layer in the termination region, and the first metal layer is deposited on the sidewall and bottom of the trench in the termination region half.
还包括一第二金属层，其淀设于所述第一金属层上。It also includes a second metal layer deposited on the first metal layer.
一种沟槽肖特基二极管的制备方法，包括以下步骤:A preparation method of trench Schottky diode, comprising the following steps:
在基片上生长外延；growing epitaxy on the substrate;
在外延层表面淀积一层氧化层，并进行光刻，留出沟槽刻蚀的窗口，留下的氧化层作为沟槽刻蚀的掩蔽层，去除光刻胶；Deposit an oxide layer on the surface of the epitaxial layer, and perform photolithography to leave a window for trench etching, and the remaining oxide layer is used as a mask layer for trench etching to remove the photoresist;
沟槽刻蚀；Trench etching;
生长牺牲氧化层；Growth of a sacrificial oxide layer;
硅片倾斜注入，形成N型注入区；The silicon wafer is implanted obliquely to form an N-type implanted region;
硅片垂直注入，注入浓度大于倾斜注入，硅片退火，形成P型注入区；The silicon wafer is implanted vertically, the implant concentration is higher than that of the oblique implant, and the silicon wafer is annealed to form a P-type implant region;
牺牲氧化层及掩蔽层移除；Sacrificial oxide layer and mask layer removal;
生长一层合适的氧化层；grow a suitable oxide layer;
多晶硅淀积；polysilicon deposition;
多晶硅刻蚀；Polysilicon etching;
淀积一层氧化层介质，对器件边缘的表面和多晶硅表面形成保护，然后光刻，再接触刻蚀，将外延硅表面和多晶硅表面的氧化层去除；留下终端区被光刻胶保护住的氧化层介质。Deposit a layer of oxide layer dielectric to protect the surface of the edge of the device and the polysilicon surface, then photolithography, and then contact etching to remove the oxide layer on the epitaxial silicon surface and polysilicon surface; leaving the terminal area protected by photoresist oxide medium.
肖特基金属淀积，淀积第一金属；Schottky metal deposition, depositing the first metal;
前端金属淀积，淀积第二金属；Front-end metal deposition, depositing the second metal;
金属层光刻，在光刻胶的掩蔽作用下，刻蚀掉终端大沟槽的金属及肖特基金属；Metal layer photolithography, under the masking effect of photoresist, etch away the metal and Schottky metal of the terminal large trench;
背面金属淀积。Metal deposition on the backside.
本发明的优点是：发明给出了一种沟槽肖特基二极管(TMBS)结构及其制造方法。相对于常规TMBS：其提高了耐压、减小了正向压降、提高了开关速度、减小了反向电容。The invention has the advantages that: the invention provides a trench Schottky diode (TMBS) structure and a manufacturing method thereof. Compared with conventional TMBS: It improves the withstand voltage, reduces the forward voltage drop, improves the switching speed, and reduces the reverse capacitance.
附图说明Description of drawings
下面结合实施例和附图对本发明进行详细说明，其中：The present invention is described in detail below in conjunction with embodiment and accompanying drawing, wherein:
图1是本发明的结构示意图。Fig. 1 is a structural schematic diagram of the present invention.
图2至图17是本发明的中间体的结构示意图。2 to 17 are schematic structural views of the intermediates of the present invention.
具体实施方式detailed description
下面结合附图进一步阐述本发明的具体实施方式：Further set forth the specific embodiment of the present invention below in conjunction with accompanying drawing:
如图1所示，一种沟槽肖特基二极管，包括沟槽，且所述沟槽的侧壁外侧设有N型注入区100，且所述沟槽的底部设有P型注入区110。As shown in Figure 1, a trench Schottky diode includes a trench, and an N-type implantation region 100 is provided outside the sidewall of the trench, and a P-type implantation region 110 is provided at the bottom of the trench. .
本发明还包括一基片层10，且所述基片层10的一侧设有一外延层20，所述沟槽设于所述外延层20内。The present invention also includes a substrate layer 10 , and one side of the substrate layer 10 is provided with an epitaxial layer 20 , and the trench is provided in the epitaxial layer 20 .
本发明所述沟槽包括若干第一沟槽23及终端区沟槽24，且所述终端区沟槽24设于所述外延层20的边缘。The trenches of the present invention include a plurality of first trenches 23 and a termination region trench 24 , and the termination region trenches 24 are disposed on the edge of the epitaxial layer 20 .
第一沟槽23内生长有栅氧化层30及淀设有多晶硅40，且多晶硅40将第一沟槽23淀设满，栅氧化层30淀设于第一沟槽23的侧壁和底部。所述终端区沟槽24的侧壁和底部生长有栅氧化层30，所述栅氧化层30上淀设有多晶硅栅40，且多晶硅栅40淀设于所述终端区沟槽23的侧壁及底部外围上；一氧化物层50淀设于多晶硅栅40上，且氧化物层50淀设于终端区沟槽24的侧壁及底部外围，且未淀设满所述沟端区沟槽。所述栅氧化层30还淀设于所述边缘部分的外延层20上，所述氧化物层50淀设于终端区的多晶硅40和栅氧化层30的上方。A gate oxide layer 30 is grown in the first trench 23 and polysilicon 40 is deposited, and the polysilicon 40 is deposited to fill the first trench 23 , and the gate oxide layer 30 is deposited on the sidewall and bottom of the first trench 23 . A gate oxide layer 30 is grown on the sidewall and bottom of the trench 24 in the termination region, a polysilicon gate 40 is deposited on the gate oxide layer 30, and the polysilicon gate 40 is deposited on the sidewall of the trench 23 in the termination region and on the periphery of the bottom; an oxide layer 50 is deposited on the polysilicon gate 40, and the oxide layer 50 is deposited on the sidewall and the periphery of the bottom of the trench 24 in the terminal region, and the trench in the terminal region is not deposited. . The gate oxide layer 30 is also deposited on the epitaxial layer 20 at the edge portion, and the oxide layer 50 is deposited on the polysilicon 40 and the gate oxide layer 30 in the terminal area.
本发明还包括第一金属层70，其淀设于外延层20、所述第一沟槽23上，且终端区的氧化物层50上，且第一金属层70淀设于所述终端区沟槽24的侧壁及底部一半。还包括一第二金属层80，其淀设于所述第一金属层70上。The present invention also includes a first metal layer 70, which is deposited on the epitaxial layer 20, the first trench 23, and on the oxide layer 50 in the termination region, and the first metal layer 70 is deposited on the termination region The sidewall and half of the bottom of the trench 24 . It also includes a second metal layer 80 deposited on the first metal layer 70 .
一种沟槽肖特基二极管的制备方法，包括以下步骤:A preparation method of trench Schottky diode, comprising the following steps:
在基片上生长外延；如图2所示，在合适的N型基片上生长一层符合要求的外延层。Growth epitaxy on the substrate; as shown in Figure 2, grow an epitaxial layer meeting the requirements on a suitable N-type substrate.
在外延层表面淀积一层氧化层，并进行光刻，留出沟槽刻蚀的窗口，留下的氧化层作为沟槽刻蚀的掩蔽层，去除光刻胶；在外延层表面生长一层氧化层，并进行光刻，留出沟槽刻蚀的窗口，留下的氧化层作为沟槽刻蚀的掩蔽层，去除光刻胶，如图3所示。Deposit a layer of oxide layer on the surface of the epitaxial layer, and perform photolithography to leave a window for trench etching, and the remaining oxide layer is used as a mask layer for trench etching to remove the photoresist; grow a layer on the surface of the epitaxial layer layer oxide layer, and perform photolithography to leave a window for trench etching, and the remaining oxide layer is used as a mask layer for trench etching to remove the photoresist, as shown in Figure 3.
沟槽刻蚀；进行沟槽刻蚀，在掩蔽层的掩蔽作用下刻蚀出沟槽，保留掩蔽层作为后面两次注入的阻挡层，如图4所示。Groove etching: groove etching is performed, a groove is etched under the masking effect of the masking layer, and the masking layer is reserved as a barrier layer for the next two implants, as shown in FIG. 4 .
生长牺牲氧化层；根据设计要求，在硅片表面生长一层合适厚度的牺牲氧化层，如图5所示。Growing a sacrificial oxide layer; according to design requirements, grow a layer of sacrificial oxide layer with an appropriate thickness on the surface of the silicon wafer, as shown in Figure 5.
硅片倾斜注入，形成N型注入区；对硅片进行倾斜角度注入，注入角度视具体设计而定；注入杂质为N型，在沟槽侧壁形成N+注入区，这会使得沟槽侧壁区域的外延电阻率下降，因而可以降低器件的正向压降VF，提高器件开关速度，如图6所示。The silicon wafer is implanted obliquely to form an N-type implantation region; the silicon wafer is implanted at an oblique angle, and the implantation angle depends on the specific design; the implanted impurity is N-type, and an N+ implantation region is formed on the side wall of the trench, which will make the side wall of the trench The epitaxial resistivity of the area decreases, so the forward voltage drop VF of the device can be reduced, and the switching speed of the device can be improved, as shown in Figure 6.
硅片垂直注入，注入浓度大于倾斜注入，硅片退火，形成P型注入区；对硅片表面进行垂直注入；注入杂质为P型，浓度大于倾斜注入浓度具体视设计而定，在沟槽底部形成P型掺杂区，反向时，P型掺杂区使得外延中的耗尽区扩展，降低了该区域的电场强度，抑制了沟槽底部的峰值电场，因而可以提高TMBS耐压；并且反向时，由于耗尽区扩展导致沟槽底部的反向电容减小，降低TMBS反向电容，如图7所示。The silicon wafer is implanted vertically, the implantation concentration is higher than the oblique implantation, and the silicon wafer is annealed to form a P-type implantation region; the silicon wafer surface is vertically implanted; the implanted impurity is P-type, and the concentration is greater than the oblique implantation concentration. It depends on the design. Forming a P-type doped region, in the reverse direction, the P-type doped region expands the depletion region in the epitaxy, reduces the electric field intensity in this region, and suppresses the peak electric field at the bottom of the trench, thus improving the TMBS withstand voltage; and In the reverse direction, the reverse capacitance at the bottom of the trench decreases due to the expansion of the depletion region, which reduces the reverse capacitance of the TMBS, as shown in Figure 7.
牺牲氧化层及掩蔽层移除；牺牲氧化层移除及掩蔽层移除，如图8示。Sacrificial oxide layer and masking layer removal; sacrificial oxide layer removal and masking layer removal, as shown in FIG. 8 .
生长一层合适的氧化层；在硅片表面生长一层氧化层，作为多晶硅与硅片间的隔离，如图9所示。A suitable oxide layer is grown; an oxide layer is grown on the surface of the silicon wafer as an isolation between the polysilicon and the silicon wafer, as shown in FIG. 9 .
多晶硅淀积；淀积多晶硅，使得小沟槽被完全填充，如图10所示。Polysilicon deposition: Polysilicon is deposited so that the small trenches are completely filled, as shown in Figure 10.
多晶硅刻蚀；多晶硅刻蚀，使得硅片表面多晶硅刻蚀完，如图11所示。Polysilicon etching; polysilicon etching, so that the polysilicon on the surface of the silicon wafer is etched completely, as shown in Figure 11.
淀积一层氧化层介质，对器件边缘的表面和多晶硅表面形成保护，如图12所示。A layer of oxide layer dielectric is deposited to protect the surface of the edge of the device and the surface of the polysilicon, as shown in FIG. 12 .
介质层光刻；淀积光刻较并进行光刻，接着进行接触刻蚀，将外延硅表面和多晶硅表面的氧化层去除，使其可以与后续工艺的金属层接触；器件边缘的终端沟槽内的氧化层保留，形成本发明所需要的终端环结构，如图13所示。Dielectric layer photolithography; deposition photolithography and photolithography, followed by contact etching to remove the oxide layer on the epitaxial silicon surface and polysilicon surface, so that it can be in contact with the metal layer of the subsequent process; the terminal trench on the edge of the device The inner oxide layer remains, forming the terminal ring structure required by the present invention, as shown in FIG. 13 .
肖特基金属淀积及退火；肖特基金属淀积及退火，如图14所示。Schottky metal deposition and annealing; Schottky metal deposition and annealing, as shown in Figure 14.
前段金属淀积，淀积第二金属；前段金属淀积，淀积第二金属，如图15所示。The front-stage metal deposition is to deposit the second metal; the front-stage metal deposition is to deposit the second metal, as shown in FIG. 15 .
金属层光刻，在光刻胶的掩蔽作用下，刻蚀掉终端大沟槽的金属及肖特基金属，如图16所示。Metal layer photolithography, under the masking effect of photoresist, etch away the metal and Schottky metal of the terminal large trench, as shown in FIG. 16 .
TMBS的背面减薄及背面金属淀积，如图17所示。The back thinning and back metal deposition of TMBS are shown in Figure 17.
本发明提供了一种性能改进的TMBS结构和其制造方法。本发明的改进方法是在沟槽的底部和侧壁上分别进行不同掺杂类型的注入，改善TMBS的反向电场，以及降低正向的导通压降。The present invention provides a TMBS structure with improved properties and a method for its manufacture. The improved method of the present invention is to respectively perform implantation of different doping types on the bottom and side walls of the trench, improve the reverse electric field of TMBS, and reduce the forward conduction voltage drop.
反向偏置时，传统TMBS结构在沟槽底部存在大电场，本发明在沟槽底部注入P型掺杂区，增强沟槽底部的耗尽，增加沟槽底部的耗尽层宽度，提高TMBS耐压。同时，由于P型杂质注入的散射效应，沟槽的侧壁也会注入P型掺杂，导致侧壁区域的电阻率升高，使TMBS得正向导通压降升高。因此，才用倾斜注入N型杂质到沟槽的侧壁，降低沟槽侧壁的电阻率。本发明通过两次注入来提高器件的性能。一次倾斜注入(注入角度视具体设计而定)，在MOS结构侧壁形成N+注入区；一次为垂直注入，在MOS结构底端形成P注入区，且垂直注入浓度大于倾斜注入。注入的掩蔽层为沟槽刻蚀的掩蔽层，其放在牺牲氧化层移除时一起移除。本发明相对于常规TMBS：其提高了耐压、减小了正向压降、减小了反向电容、提高了开关速度。工艺成本只增加了两次注入工艺，没有增加光刻层次。本发明给出了一种沟槽肖特基二极管(TMBS)结构及其制造方法。相对于常规TMBS：其提高了耐压、减小了正向压降、提高了开关速度、减小了反向电容。When reverse biased, the traditional TMBS structure has a large electric field at the bottom of the trench. The invention implants a P-type doped region at the bottom of the trench to enhance the depletion at the bottom of the trench, increase the width of the depletion layer at the bottom of the trench, and improve the TMBS withstand voltage. At the same time, due to the scattering effect of P-type impurity implantation, the sidewall of the trench will also be implanted with P-type doping, resulting in an increase in the resistivity of the sidewall region and an increase in the forward conduction voltage drop of the TMBS. Therefore, the N-type impurity is implanted into the sidewall of the trench at an angle to reduce the resistivity of the sidewall of the trench. The invention improves the performance of the device through two injections. One oblique implantation (the implantation angle depends on the specific design) forms an N+ implantation region on the sidewall of the MOS structure; one vertical implantation forms a P implantation region at the bottom of the MOS structure, and the concentration of the vertical implantation is greater than that of the oblique implantation. The implanted masking layer is a masking layer for trench etching, which is removed together when the sacrificial oxide layer is removed. Compared with the conventional TMBS, the invention has the following advantages: it improves the withstand voltage, reduces the forward voltage drop, reduces the reverse capacitance and improves the switching speed. The process cost only increases the implantation process twice, and does not increase the photolithography level. The invention provides a trench schottky diode (TMBS) structure and a manufacturing method thereof. Compared with conventional TMBS: It improves the withstand voltage, reduces the forward voltage drop, improves the switching speed, and reduces the reverse capacitance.
本发明提供了两次注入来实现对TMBS器件的优化。一次为沟槽侧壁的倾斜注入，注入N型杂质，在沟槽侧壁形成N+注入区，由于N+注入区的存在，降低了外延层的电阻率，减小了器件的正向导通压降。一次是向底部的垂直注入，注入浓度和能量都大于前一次的倾斜注入；通过向沟槽底部注入P型杂质，来改善沟槽底部的电场分布；同时，也可以减小反向电容。The invention provides two injections to realize the optimization of the TMBS device. One is the oblique implantation of the side wall of the trench, implanting N-type impurities, and forming an N+ implantation region on the side wall of the trench. Due to the existence of the N+ implantation region, the resistivity of the epitaxial layer is reduced, and the forward conduction voltage drop of the device is reduced. . One is a vertical implantation to the bottom, and the implantation concentration and energy are greater than the previous oblique implantation; by injecting P-type impurities into the bottom of the trench, the electric field distribution at the bottom of the trench is improved; at the same time, the reverse capacitance can also be reduced.
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.
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| CN108269848A (en) * | 2016-12-31 | 2018-07-10 | 朱江 | A kind of groove Schottky semiconductor device |
| CN110190135A (en) * | 2019-05-29 | 2019-08-30 | 西安电子科技大学芜湖研究院 | A kind of floating junction Schottky diode and its preparation method |
| CN113471301A (en) * | 2020-03-31 | 2021-10-01 | 比亚迪半导体股份有限公司 | Groove Schottky diode and preparation method thereof |
| CN116169025A (en) * | 2023-02-10 | 2023-05-26 | 上海维安半导体有限公司 | Preparation method and device of ladder-gate trench Schottky barrier diode device |
| WO2025102667A1 (en) * | 2023-11-14 | 2025-05-22 | 华润微电子（重庆）有限公司 | Trench-type schottky barrier diode and manufacturing method therefor |
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