CN106129066A - A kind of array base palte, display floater and array base palte preparation method - Google Patents

Abstract

The present invention provides an array substrate, a display panel and a method for preparing the array substrate. By providing a first connection layer with conductivity between the substrate and the first signal line, since the first connection layer has conductivity, even when the first signal line When the position corresponding to the line area is etched, the first signal line is over-etched and disconnected, and the first connection layer and the first signal line can also be electrically connected to play the same role as the first signal line to ensure electrical connection. The transmission of the voltage is realized, so as to protect the first signal line, solve the problem of poor line caused by the over-cutting of the first signal line, and improve the display effect. In addition, since the first connection layer has a certain thickness, the etching process conditions can be relatively relaxed, and the thickness of the first signal line can be appropriately reduced, thereby reducing process requirements and making it easier to implement.

Description

A kind of array substrate, display panel and preparation method of array substrate

technical field

The invention relates to the field of display technology, in particular to an array substrate, a display panel and a method for preparing the array substrate.

Background technique

In the production process of TFT LCD (Thin Film Transistor-Liquid Crystal Display, thin film transistor liquid crystal display panel), usually 6 patterning processes are used. As shown in FIG. 1 , the peripheral area of an existing array substrate includes: a base 1, a first signal line 2, an insulating layer 3, a second signal line 4 and a protective layer 5, the second signal line 4 is formed on the base 1, The insulating layer 3 is formed on the substrate 1 and the second signal line 4 , the first signal line 2 is formed on the insulating layer 3 , and the protection layer 5 is formed on the insulating layer 3 and the first signal line 2 . In order to improve yield and production capacity, as shown in FIG. 1 , instead of forming a via hole on the gate insulating layer 3 through a patterning process alone, a second via is etched on the protective layer 5 corresponding to the position of the second signal line 4 at the same time. The via hole 6 and the first via hole 7 are formed by etching on the protection layer 5 and the insulating layer 3 corresponding to the position of the first signal line 2 . In order to ensure that the second via hole 6 can be etched to the second signal line 4, the first signal line 2 must be over-etched.

However, after the first signal line 2 is over-etched, its surface becomes rough and its corrosion resistance is poor. During subsequent processes such as cleaning, masking, etching, film removal, and box alignment, liquid is likely to remain, and the second A signal line 2 is corroded and broken, resulting in a defective line, and dark lines or bright lines appear in the display. Due to process fluctuations, the thickness of the first signal line 2 is uneven, and the corrosion usually occurs in the area where the thickness of the first signal line 2 is relatively thin. However, it is very difficult to improve the process, especially the thread defect is progressive, and it is difficult to detect it in time, thus increasing the quality risk.

Contents of the invention

The present invention aims at the above-mentioned deficiencies in the prior art, and provides an array substrate, a display panel and a method for preparing the array substrate, which are used to at least partly solve the problems of bad lines and poor display effects caused by over-scribing of signal lines.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

The present invention provides an array substrate, which includes a substrate, and further includes a first connection layer and a first signal line formed in the region of the first signal line on the substrate, and the first connection layer is located between the first signal line and the substrate. between, and has conductive properties.

Further, the array substrate further includes a second signal line formed in a second signal line region on the substrate, and an insulating layer formed on the substrate and the second signal line;

The first connection layer and the first signal line are formed on the insulating layer, and the first connection layer is located between the first signal line and the insulating layer.

Further, the array substrate further includes a protective layer formed on the insulating layer and the first signal line;

A position corresponding to the first signal line area in the protective layer is formed with a first via hole penetrating through the protective layer, and a position corresponding to the second signal line area in the protective layer and the insulating layer A second via hole is formed penetrating through the protective layer and the insulating layer.

Further, the array substrate further includes a second connection layer formed on the protective layer at a position corresponding to the first signal line area.

Preferably, the material of the first connection layer and/or the second connection layer is indium tin oxide.

Preferably, the shape of the first connection layer is the same as that of the first signal line.

The present invention also provides a display panel, which includes the aforementioned array substrate.

The present invention also provides a method for preparing an array substrate, the method comprising:

A pattern including a first connection layer and a first signal line is formed on the first signal line region on the substrate through a patterning process; wherein the first connection layer is located between the first signal line and the substrate and has electrical conductivity .

Further, before forming a pattern including the first connection layer and the first signal line in the first signal line region on the substrate through a patterning process, the method further includes:

forming a pattern including the second signal line on the second signal line region on the substrate through a patterning process;

form an insulating layer;

The formation of a pattern including the first connection layer and the first signal line on the first signal line region on the substrate through a patterning process specifically includes:

A pattern including a first connection layer and a first signal line is formed on the insulating layer at a position corresponding to the first signal line region through a patterning process, wherein the first connection layer is located on the first signal line between the insulating layer.

Further, after forming a pattern including the first connection layer and the first signal line on the position corresponding to the first signal line region on the insulating layer through a patterning process, the method further includes:

form a protective layer;

A first via hole penetrating through the protective layer is formed at a position corresponding to the first signal line region through a patterning process, and a via hole penetrating through the protective layer and the insulating layer is formed at a position corresponding to the second signal line region. second via.

Further, the patterning process forms a first via hole penetrating through the protection layer at a position corresponding to the first signal line area, and forms a through hole penetrating through the protection layer at a position corresponding to the second signal line area. After the second via of layer and insulating layer, also include:

A second connection layer is formed on the protection layer at a position corresponding to the first signal line region through a patterning process.

Preferably, the material of the first connection layer and/or the second connection layer is indium tin oxide.

Preferably, forming a pattern including the first connection layer and the first signal line on the insulating layer at a position corresponding to the first signal line region through a patterning process specifically includes:

A first conductive film and a second conductive film are sequentially deposited on the insulating layer at positions corresponding to the first signal line region, and a pattern including the first connection layer and the first signal line is formed through a patterning process.

Preferably, the formation of the pattern including the first connection layer and the first signal line through a patterning process specifically includes:

Coating photoresist on the second conductive film;

Exposing, developing, and etching the substrate after the above steps are performed using a mask, and forming a pattern including the first connection layer and the first signal line on the position corresponding to the first signal line area on the insulating layer.

The present invention can realize following beneficial effect:

In the present invention, a first connection layer with conductivity is provided between the substrate and the first signal line. Since the first connection layer has conductivity, even when the via hole is etched at the position corresponding to the first signal line area, the first signal line In the event of an overcut disconnection, the first connection layer and the first signal line can also be electrically connected, and play the same role as the first signal line to ensure electrical connection and realize voltage transmission, thereby protecting the first signal line It can solve the problem of poor line caused by the over-marking of the first signal line, and improve the display effect. In addition, since the first connection layer has a certain thickness, the etching process conditions can be relatively relaxed, and the thickness of the first signal line can be appropriately reduced, thereby reducing process requirements and making it easier to implement.

Description of drawings

Fig. 1 is the preparation flowchart of existing array substrate;

FIG. 2 is a schematic structural view of the peripheral area of the array substrate according to the embodiment of the present invention;

FIG. 3 is a flow chart of the preparation of the array substrate according to the embodiment of the present invention.

illustration:

1. Substrate 2. First signal line 3. Insulation layer 4. Second signal line

5. Protective layer 6. Second via hole 7. First via hole 8. First connection layer

9. The second connection layer

detailed description

The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The structure of the array substrate of the present invention will be described in detail below with reference to FIG. 2 .

As shown in FIG. 2, the present invention provides an array substrate, including a base 1, and a first connection layer 8 and a first signal line 2 formed in the first signal line region on the base 1. The first connection layer 8 is located on the first between the signal line 2 and the substrate 1, and has the property of conductivity.

In the present invention, a first connection layer with electrical conductivity is provided between the substrate and the first signal line, even if the first signal line is overcut and disconnected when the position corresponding to the first signal line area is etched, the first connection The layer and the first signal line can also be electrically connected to play the same role as the first signal line to ensure electrical connection and realize voltage transmission, so as to protect the first signal line and solve the problem of over-engraving of the first signal line. The problem of poor line is brought, and the display effect is improved. In addition, since the first connection layer has a certain thickness, the thickness of the first signal line can be appropriately reduced, and the etching process conditions can be relatively relaxed, that is, the etching time and power are appropriately reduced, and parameters such as gas pressure and proportion The scope is appropriately expanded, thereby reducing the process requirements and making it easier to implement.

Preferably, the material of the first connection layer 8 may be indium tin oxide (ITO), which is chemically inactive, has strong electrical conductivity, and has strong resistance to dry etching.

It should be noted that the array substrate may also include a second signal line 4 and an insulating layer 3, the second signal line 4 is formed on the second signal line region on the substrate, and the insulating layer 3 is formed on the substrate 1 and the second signal line area. 4 on. Correspondingly, the first connection layer 8 and the first signal line 2 are formed on the insulating layer 3, the first connection layer 8 is located between the first signal line 2 and the insulating layer 3, that is, the first connection layer 8 is located on the first signal line 2 (adjacent to the substrate 1), so as to protect the first signal line from overcutting.

Preferably, the first signal line 2 may be a data line (SD), the second signal line 4 may be a gate line, and the insulating layer 3 may be a gate insulating layer. Ensure that the SD layer is protected by an ITO layer when the via is etched, thereby solving the problem that the SD layer is corroded and broken at the via hole, resulting in defective lines.

Further, the array substrate further includes a protective layer 5 formed on the insulating layer 3 and the first signal line 2 . A first via hole 7 is formed in the protective layer 5 corresponding to the first signal line area, and the first via hole 7 penetrates the protective layer 5 for connecting with the first signal line 2 so as to lead to the first signal line 2. Signal. A second via hole 6 is formed in the protective layer 5 and the insulating layer 3 corresponding to the second signal line area, and the second via hole 6 penetrates the protective layer 5 and the insulating layer 3 for connecting with the second signal line 4, In order to introduce a signal to the second signal line 4 .

It should be noted that the first via hole 7 and the second via hole 6 are formed simultaneously through one patterning process, and the depth of the first via hole 7 and the second via hole 6 are the same. In this way, there is no need to form via holes on the insulating layer 3 through a patterning process alone, which simplifies the manufacturing process.

It should be noted that the width of the first connection layer 8 is greater than or equal to the width of the first signal line 2 at the first via hole 7, so that even if the first signal line 2 is overcut, the first connection layer 8 can be guaranteed It is effectively connected with the first signal line 2 to avoid the occurrence of line defects and improve the display effect.

Preferably, the shape of the first connection layer 8 is the same as that of the first signal line 2, so that, on the one hand, the first connection layer 8 and the first signal line 2 can be prepared using the same mask, thereby reducing production costs; On the other hand, the first connection layer 8 can effectively protect the first signal line 2 from over-cutting.

It should be noted that the shapes of the first connection layer 8 and the first signal line 2 are not limited, and may be in any shape such as square or circular, as long as they can protect the first signal line 2 .

Further, the array substrate may further include a second connection layer 9, which is formed on the protection layer 5 at a position corresponding to the first signal line region, so that it can be connected to the first signal line through the first via hole 7. Layer 8 is connected, so as to introduce signals to the first signal line 2 .

Preferably, the material of the second connection layer 9 may be indium tin oxide (ITO).

When the first signal line 2 does not undergo overetch corrosion, the resistance between the second connection layer 9 and the first signal line 2 is the smallest. When the first signal line 2 is overetched, the resistance between the second connection layer 9 and the first The resistance between the signal lines 2 increases, resulting in a decrease in transmission efficiency. The present invention can effectively reduce the gap between the second connection layer 9 and the first signal line 2 when the first signal line 2 is overetched by arranging the first connection layer 8 with conductivity under the first signal line 2. resistance to ensure transmission efficiency.

Another embodiment of the present invention further provides a display panel, which includes the aforementioned array substrate.

By providing a first connection layer with electrical conductivity between the substrate and the first signal line, even if the first signal line is overcut and disconnected when the position corresponding to the first signal line area is etched, the first connection The layer and the first signal line can also be electrically connected to play the same role as the first signal line to ensure electrical connection and realize voltage transmission, so as to protect the first signal line and solve the problem of over-engraving of the first signal line. The problem of poor line is brought, and the display effect is improved. In addition, since the first connection layer has a certain thickness, the etching process conditions can be relatively relaxed, and the thickness of the first signal line can be appropriately reduced, thereby reducing process requirements and making it easier to implement.

Another embodiment of the present invention also provides a method for preparing an array substrate, as shown in FIG. 3 , the method includes the following steps:

Step 11, a pattern including the first connection layer and the first signal line is formed on the first signal line area on the substrate through a patterning process.

Specifically, the first connection layer 8 is located between the first signal line 2 and the substrate 1 , and has conductivity, so as to protect the first signal line 2 .

Preferably, the material of the first connection layer 8 is indium tin oxide.

By providing the first connection layer with electrical conductivity between the substrate and the first signal line, even if the first signal line is over-etched and disconnected when the via hole is etched at the position corresponding to the first signal line area, the first connection layer and the first signal line The first signal line can also be electrically connected to play the same role as the first signal line, so as to ensure electrical connection and realize voltage transmission, thereby protecting the first signal line and solving the problem caused by over-marking of the first signal line. To solve the problem of bad lines, improve the display effect. In addition, since the first connection layer has a certain thickness, the thickness of the first signal line can be appropriately reduced, and the etching process conditions can be relatively relaxed, that is, the etching time and power are appropriately reduced, and parameters such as gas pressure and proportion The scope is appropriately expanded, thereby reducing the process requirements and making it easier to implement.

It should be noted that the second signal line 4 and the insulating layer 3 are also formed on the substrate 1, and the first connection layer 8 and the first signal line are formed on the insulating layer 3. Therefore, the following steps are also included before step 11:

Step 10, forming a pattern including the second signal line on the second signal line area on the substrate through a patterning process.

Specifically, a third conductive film is deposited on the substrate 1 at a position corresponding to the second signal line region, a photoresist is coated on the substrate 1, and the substrate 1 that has completed the above steps is exposed, developed, and exposed using a mask. Etching, forming a pattern including the second signal line 4 at the position corresponding to the second signal line area on the substrate 1 .

The second signal line can be a gate line, the third conductive film can be a metal film, and its material can be chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), neodymium (Nd) ), alloys of the above metals may also be used. The third conductive thin film may be deposited by using sputtering, thermal evaporation, or other film forming methods.

Step 10', forming an insulating layer.

Specifically, an insulating layer 3 is formed on the substrate 1 and the second signal line 4 . The insulating layer 3 can be formed by methods such as plasma enhanced chemical vapor deposition, and the material of the insulating layer 3 can be silicon oxide (such as SiOx) or silicon nitride (such as SiNx), or a combination of the two.

The formation of a pattern including the first connection layer and the first signal line on the first signal line region on the substrate through a patterning process (ie, step 11) specifically includes:

A pattern comprising the first connection layer 8 and the first signal line 2 is formed on the insulating layer 3 at a position corresponding to the first signal line region through a patterning process, wherein the first connection layer 8 is located between the first signal line 2 and the insulating layer between 3.

Further, after forming a pattern including the first connection layer and the first signal line at a position corresponding to the first signal line region on the insulating layer through a patterning process (that is, step 11), the method further includes The following steps:

Step 12, forming a protective layer.

Specifically, a protective layer 5 is formed on the insulating layer 3 and the first signal line 2 .

Step 13, forming a first via hole penetrating through the protective layer at a position corresponding to the first signal line area through a patterning process, and forming a through hole penetrating through the protective layer at a position corresponding to the second signal line area. The second via in the insulating layer.

Specifically, in order to improve product yield and production capacity and save processes, at the same time, the first via hole 7 penetrating through the protective layer 5 is formed by etching at the position corresponding to the first signal line area, and the via hole 7 is formed at the position corresponding to the second signal line area. A second via hole 6 penetrating through the protective layer 5 and the insulating layer 3 .

Further, after step 13, the method also includes:

Step 14 , forming a second connection layer on the protection layer at a position corresponding to the first signal line region through a patterning process.

Specifically, a fourth conductive film is deposited on the protective layer 5 at a position corresponding to the first signal line area, a photoresist is coated on the fourth conductive film, and the substrate 1 that has completed the above steps is exposed using a mask , developing, and etching, forming a pattern including the second connection layer 9 on the protective layer 5 at a position corresponding to the first signal line area.

Preferably, the material of the second connection layer 9 may be indium tin oxide, that is, the material of the fourth conductive film is indium tin oxide.

It should be noted that, in order to save the process flow and reduce the manufacturing cost, the shape of the first connection layer 8 can be the same as that of the first signal line 2, so that the first connection layer 8 and the first signal line 2 can be processed in one process. Finish.

Specifically, forming a pattern including a first connection layer and a first signal line at a position on the insulating layer corresponding to the first signal line region through a patterning process specifically includes:

A first conductive film and a second conductive film are sequentially deposited on the insulating layer 3 at positions corresponding to the first signal line region, and a pattern including the first connection layer 8 and the first signal line 2 is formed through a patterning process.

The first conductive film is used to form the first connection layer 8, and the material of the first conductive film is indium tin oxide. Preferably, the material of the second conductive film can be the same as that of the third conductive film, and the second conductive film and the third conductive film can be metal films, for example, chromium (Cr), molybdenum (Mo), aluminum ( One of Al), copper (Cu), tungsten (W), and neodymium (Nd), or an alloy of the above metals may be used. The second conductive thin film may be deposited by using sputtering, thermal evaporation, or other film forming methods.

Wherein, the formation of the pattern including the first connection layer 8 and the first signal line 2 through one patterning process specifically includes:

Coat photoresist on the second conductive film, use a mask to expose, develop and etch the substrate 1 after the above steps, and form a first The pattern of the connection layer 8 and the first signal line 2 .

It can be seen from this that in the process of forming the pattern including the first connection layer 8 and the first signal line 2, the present invention uses the same mask plate for exposure, development, and etching, thereby forming a pattern including the first connection layer 8. The pattern of the first signal line 2 and the first signal line 2 not only can make the first connection layer 8 and the first signal line 2 be aligned accurately, but also save the mask plate and further reduce the production cost.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (14)

1. An array substrate, comprising a base, characterized in that it further comprises a first connection layer and a first signal line formed in a first signal line area on the base, the first connection layer is located on the first signal line Between the wire and the substrate, and has conductive properties. 2. The array substrate according to claim 1, further comprising a second signal line formed in the second signal line region on the substrate and an insulating layer formed on the substrate and the second signal line; The first connection layer and the first signal line are formed on the insulating layer, and the first connection layer is located between the first signal line and the insulating layer. 3. The array substrate according to claim 2, further comprising a protective layer formed on the insulating layer and the first signal line; A position corresponding to the first signal line area in the protective layer is formed with a first via hole penetrating through the protective layer, and a position corresponding to the second signal line area in the protective layer and the insulating layer A second via hole is formed penetrating through the protective layer and the insulating layer. 4. The array substrate according to claim 2, further comprising a second connection layer formed on the protective layer at a position corresponding to the first signal line area. 5. The array substrate according to claim 4, wherein the material of the first connection layer and/or the second connection layer is indium tin oxide. 6. The array substrate according to any one of claims 1-5, wherein the shape of the first connection layer is the same as that of the first signal line. 7. A display panel, comprising the array substrate according to any one of claims 1-6. 8. A method for preparing an array substrate, characterized in that the method comprises: A pattern including a first connection layer and a first signal line is formed on the first signal line region on the substrate through a patterning process; wherein the first connection layer is located between the first signal line and the substrate and has electrical conductivity . 9. The method for preparing an array substrate according to claim 8, wherein, before forming a pattern including the first connection layer and the first signal line in the first signal line region on the substrate through a patterning process, the method Also includes: forming a pattern including the second signal line on the second signal line region on the substrate through a patterning process; form an insulating layer; The formation of a pattern including the first connection layer and the first signal line on the first signal line region on the substrate through a patterning process specifically includes: A pattern including a first connection layer and a first signal line is formed on the insulating layer at a position corresponding to the first signal line region through a patterning process, wherein the first connection layer is located on the first signal line between the insulating layer. 10. The method for manufacturing an array substrate according to claim 9, wherein the patterning process on the insulating layer at a position corresponding to the first signal line region includes a first connection layer and a first After the graph of the signal line, it also includes: form a protective layer; A first via hole penetrating through the protective layer is formed at a position corresponding to the first signal line region through a patterning process, and a via hole penetrating through the protective layer and the insulating layer is formed at a position corresponding to the second signal line region. second via. 11. The method for manufacturing an array substrate according to claim 10, wherein the patterning process forms a first via hole penetrating through the protective layer at a position corresponding to the first signal line area, and After forming the second via hole penetrating through the protective layer and the insulating layer at the position corresponding to the second signal line region, it also includes: A second connection layer is formed on the protection layer at a position corresponding to the first signal line region through a patterning process. 12. The method for manufacturing the array substrate according to claim 11, wherein the material of the first connection layer and/or the second connection layer is indium tin oxide. 13. The method for manufacturing an array substrate according to any one of claims 9-12, wherein the patterning process includes first Graphics of the connection layer and the first signal line, including: A first conductive film and a second conductive film are sequentially deposited on the insulating layer at positions corresponding to the first signal line region, and a pattern including the first connection layer and the first signal line is formed through a patterning process. 14. The method for preparing an array substrate according to claim 13, wherein said forming a pattern including the first connection layer and the first signal line through one patterning process specifically comprises: Coating photoresist on the second conductive film; Exposing, developing, and etching the substrate after the above steps are performed using a mask, and forming a pattern including the first connection layer and the first signal line on the position corresponding to the first signal line area on the insulating layer.