CN106057903A - Shielded gate trench type MOSFET and manufacturing method thereof - Google Patents
Shielded gate trench type MOSFET and manufacturing method thereof Download PDFInfo
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- CN106057903A CN106057903A CN201610621817.XA CN201610621817A CN106057903A CN 106057903 A CN106057903 A CN 106057903A CN 201610621817 A CN201610621817 A CN 201610621817A CN 106057903 A CN106057903 A CN 106057903A
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- polysilicon
- groove
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- oxide
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims abstract description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000009279 wet oxidation reaction Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000009826 distribution Methods 0.000 abstract description 5
- 210000000746 body region Anatomy 0.000 abstract 3
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
本发明公开了一种屏蔽栅沟槽型MOSFET，包括：硅衬底上部的沟槽，沟槽由氧化膜分为两部分，沟槽的上部为栅多晶硅，沟槽的下部为源多晶硅；沟槽之间为体区，体区的上方是源区，硅衬底的上方具有层间介质层，层间介质层上方是金属层，接触孔将金属层和体区连通；栅多晶硅和氧化膜之间还具有氮化硅层。本发明还公开了所述屏蔽栅沟槽型MOSFET的制造方法。本发明的器件结构栅极介质膜和多晶硅间介质膜同步生长，采用ONO结构；在源区光刻前增加一步表面氮化硅刻蚀工艺，能优化多晶硅层间介质膜的质量，改善了栅源耐压分布。
The invention discloses a shielded gate trench type MOSFET, comprising: a trench on the upper part of a silicon substrate, the trench is divided into two parts by an oxide film, the upper part of the trench is gate polysilicon, and the lower part of the trench is source polysilicon; Between the grooves is the body region, above the body region is the source region, above the silicon substrate is an interlayer dielectric layer, above the interlayer dielectric layer is a metal layer, and the contact hole connects the metal layer and the body region; the gate polysilicon and oxide film There is also a silicon nitride layer in between. The invention also discloses a manufacturing method of the shielding gate trench type MOSFET. The gate dielectric film and the inter-polysilicon dielectric film of the device structure of the present invention are grown synchronously, and the ONO structure is adopted; a step of surface silicon nitride etching process is added before the photolithography of the source area, which can optimize the quality of the inter-polysilicon dielectric film and improve the gate Source withstand voltage distribution.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of shield grid trench MOSFET.The invention still further relates to institute
State the manufacture method of shield grid trench MOSFET.
Background technology
When existing technique manufactures shield grid trench MOSFET, it is typically manufactured method as follows: deposition oxidation film on substrate；Fixed
Justice groove figure；Resist coating, oxide-film etches；Removing photoresist, etching forms groove；Deposit deposition oxidation film forms groove
The hard mask layer of sidewall；Depositing polysilicon；Etching polysilicon for the first time, removal devices surface polysilicon；Polysilicon is carved for the second time
Erosion, removes the polysilicon of the groove first half；Removal devices surface and the hard mask layer of the groove first half；By thermal oxide at device
In surface, trenched side-wall and groove, the surface of remaining polysilicon forms oxide-film as hard mask layer；Depositing polysilicon, by groove
Fill up and on the substrate between two grooves, formed body district by ion implanting and ion propulsion；By ion implanting and ion propulsion
Source region is formed above body district；Deposit makes interlayer dielectric layer；Deposit makes metal level.Existing manufacture method, inter polysilicon oxygen
Changing film and grid oxygen to grow, the oxide-film compactness of grown on polysilicon is poor simultaneously, and after being etched back to by polysilicon
Pattern impact, in uneven thickness, cause grid source and drain electricity higher, grid source is pressure distribution poor.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of employing ONO structure (thermal oxide+silicon nitride deposition+silicon nitride
Surface wet oxygen) shield grid trench MOSFET, and provide the manufacture method of a kind of described shield grid trench MOSFET.This
Bright device architecture and manufacture method thereof can optimize the quality of deielectric-coating between polysilicon layer, improve the pressure distribution in grid source.
For solving above-mentioned technical problem, the shield grid trench MOSFET that the present invention provides, including: the ditch on silicon substrate top
Groove, groove is divided into two parts by oxide-film, and the top of groove is gate polysilicon, and the bottom of groove is source polysilicon；Between groove
For body district, the top in body district is source region, and the top of silicon substrate has interlayer dielectric layer, is metal level, connects above interlayer dielectric layer
Metal level is connected by contact hole with body district；Also there is between gate polysilicon and oxide-film silicon nitride layer.
Wherein, described silicon nitride layer surface is through wet oxidation process.
The manufacture method planting shield grid trench MOSFET that the present invention provides, including:
1) oxide-film is made on silicon substrate for the first time；
2) definition groove figure, opens etching window；
3) etching forms groove；
4) second time makes oxide-film, makes trenched side-wall and bottom have oxide-film；
6) depositing polysilicon for the first time；
7) etching polysilicon for the first time, carries out device surface planarization；
8) etching polysilicon for the second time, removes the polysilicon of the groove first half；
9) removal devices surface and the oxide-film of the groove first half；
10) third time makes oxide-film, makes the surface of remaining polysilicon in device surface, trenched side-wall and groove form oxygen
Change film；
11) deposit silicon nitride；
12) depositing polysilicon for the second time, fills up groove, carries out polysilicon and be etched back to；
13) by forming body district in ion implanting and ion propulsion silicon substrate between two grooves；
14) by the silicon nitride on dry etching removal devices surface；
15) above body district, source region is formed by ion implanting and ion propulsion；
16) deposit makes interlayer dielectric layer；
17) etching makes contact hole；
18) titanium or titanium nitride are deposited in the contact hole, and deposition tungsten, it is etched back to carry out device surface planarization；
19) deposit makes metal level.
Wherein, step 11) also include silicon nitride surface wet oxidation process.
The device architecture gate dielectric film of the present invention and inter polysilicon deielectric-coating synchronous growth, increase by one before source region photoetching
Walk surfaces nitrided silicon etching process, use ONO structure (thermal oxide+silicon nitride deposition+silicon nitride surface wet oxygen), can improve existing
The problem that between polysilicon layer, deielectric-coating compactness difference thickness distribution is uneven, and then improve the pressure distribution in grid source.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of the present invention.
Fig. 2 is manufacture method schematic diagram one of the present invention.
Fig. 3 is manufacture method schematic diagram two of the present invention.
Fig. 4 is manufacture method schematic diagram three of the present invention.
Description of reference numerals
1 silicon substrate
2 source polysilicons
3 body districts
4 source regions
5 gate polysilicons
6 interlayer dielectric layers
7 contact holes
8 metal levels
9 silicon nitride layers
10 oxide layers
Detailed description of the invention
As it is shown in figure 1, the shield grid trench MOSFET that the present invention provides, including the groove on silicon substrate top, groove by
Oxide-film is divided into two parts, and the top of groove is gate polysilicon, and the bottom of groove is source polysilicon；It is body district between groove, body
The top in district is source region, and the top of silicon substrate has interlayer dielectric layer, is metal level above interlayer dielectric layer, and contact hole is by metal
Ceng Heti district connects；Also having silicon nitride layer between gate polysilicon and oxide-film, described silicon nitride layer surface is at wet oxidation
Reason.
The manufacture method planting shield grid trench MOSFET that the present invention provides, including:
1) as in figure 2 it is shown, make oxide-film on silicon substrate for the first time；
2) definition groove figure, opens etching window；
3) etching forms groove；
4) as it is shown on figure 3, second time makes oxide-film, trenched side-wall and bottom is made to have oxide-film；
6) depositing polysilicon for the first time；
7) etching polysilicon for the first time, carries out device surface planarization；
8) etching polysilicon for the second time, removes the polysilicon of the groove first half；
9) removal devices surface and the oxide-film of the groove first half；
10) as shown in Figure 4, third time makes oxide-film, makes remaining polysilicon in device surface, trenched side-wall and groove
Surface forms oxide-film；
11) deposit silicon nitride, to silicon nitride surface wet oxidation process.；
12) depositing polysilicon for the second time, fills up groove, carries out polysilicon and be etched back to；
13) by forming body district in ion implanting and ion propulsion silicon substrate between two grooves；
14) by the silicon nitride on dry etching removal devices surface；
15) above body district, source region is formed by ion implanting and ion propulsion；
16) deposit makes interlayer dielectric layer；
17) etching makes contact hole；
18) titanium or titanium nitride are deposited in the contact hole, and deposition tungsten, it is etched back to carry out device surface planarization；
19) deposit makes metal level.
Above by detailed description of the invention and embodiment, the present invention has been described in detail, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and changes
Entering, these also should be regarded as protection scope of the present invention.
Claims (4)
1. a shield grid trench MOSFET, including: the groove on silicon substrate top, groove is divided into two parts, ditch by oxide-film
The top of groove is gate polysilicon, and the bottom of groove is source polysilicon；Being body district between groove, the top in body district is source region, and silicon serves as a contrast
The top at the end has interlayer dielectric layer, is metal level above interlayer dielectric layer, and metal level is connected by contact hole with body district；Its feature
It is: also there is between gate polysilicon and oxide-film silicon nitride layer.
2. shield grid trench MOSFET as claimed in claim 1, it is characterised in that: described silicon nitride layer surface is through wet oxygen
Change processes.
3. the manufacture method of a shield grid trench MOSFET, it is characterised in that including:
1) oxide-film is made on silicon substrate for the first time；
2) etching forms groove；
3) second time makes oxide-film；
4) depositing polysilicon for the first time；
5) etching polysilicon for the first time, carries out device surface planarization；
6) etching polysilicon for the second time, removes the polysilicon of the groove first half；
7) removal devices surface and the oxide-film of the groove first half；
8) third time makes oxide-film；
11) deposit silicon nitride；
12) depositing polysilicon for the second time, fills up groove, carries out polysilicon and be etched back to；
13) by forming body district in ion implanting and ion propulsion silicon substrate between two grooves；
14) by the silicon nitride on dry etching removal devices surface；
15) above body district, source region is formed by ion implanting and ion propulsion；
16) deposit makes interlayer dielectric layer；
17) etching makes contact hole；
18) titanium or titanium nitride are deposited in the contact hole, and deposition tungsten, it is etched back to carry out device surface planarization；
19) deposit makes metal level.
4. the manufacture method of as claimed in claim 3 shield grid trench MOSFET, it is characterised in that: step 11) also include right
Silicon nitride surface wet oxidation process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610621817.XA CN106057903A (en) | 2016-08-01 | 2016-08-01 | Shielded gate trench type MOSFET and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610621817.XA CN106057903A (en) | 2016-08-01 | 2016-08-01 | Shielded gate trench type MOSFET and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106057903A true CN106057903A (en) | 2016-10-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610621817.XA Pending CN106057903A (en) | 2016-08-01 | 2016-08-01 | Shielded gate trench type MOSFET and manufacturing method thereof |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115064484A (en) * | 2022-06-07 | 2022-09-16 | 浙江同芯祺科技有限公司 | Micro-shrinking process for wafer side wall opening |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101558499A (en) * | 2005-06-24 | 2009-10-14 | 飞兆半导体公司 | Structure and method for forming laterally extending dielectric layer in a trench-gate FET |
| CN101615632A (en) * | 2008-06-26 | 2009-12-30 | 飞兆半导体公司 | Structure and method for forming shielded gate trench FET with interelectrode dielectric including nitride layer |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
-
2016
- 2016-08-01 CN CN201610621817.XA patent/CN106057903A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101558499A (en) * | 2005-06-24 | 2009-10-14 | 飞兆半导体公司 | Structure and method for forming laterally extending dielectric layer in a trench-gate FET |
| CN101615632A (en) * | 2008-06-26 | 2009-12-30 | 飞兆半导体公司 | Structure and method for forming shielded gate trench FET with interelectrode dielectric including nitride layer |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115064484A (en) * | 2022-06-07 | 2022-09-16 | 浙江同芯祺科技有限公司 | Micro-shrinking process for wafer side wall opening |
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Application publication date: 20161026 |