CN106057826A - Array substrate and manufacturing method thereof, and display apparatus - Google Patents

Abstract

Embodiments of the present invention provide an array substrate, a preparation method thereof, and a display device, which relate to the field of display technology, which can not only ensure the stability of the thin film transistor in the pixel unit, but also reduce the size of the thin film transistor in the gate drive circuit, so as to realize Narrow bezel design. The array substrate includes a pixel unit and a gate drive circuit; the pixel unit includes a first thin film transistor, the gate drive circuit includes a second thin film transistor, and the active layer of the first thin film transistor includes a stacked first metal oxide pattern and a second thin film transistor. Two metal oxide patterns; the active layer of the second thin film transistor is a third metal oxide pattern; wherein, the optical stability of the second metal oxide pattern is greater than that of the first metal oxide pattern, and the first metal oxide pattern The carrier mobility of the object pattern and the third metal oxide pattern is greater than that of the second metal oxide pattern. Used for array substrates including gate drive circuits and pixel units.

Description

A kind of array substrate and its preparation method, display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device.

Background technique

With the continuous development of display technology, people have higher and higher requirements for narrow borders of displays. In order to further reduce the width of the display frame, the current technology is to manufacture the gate drive circuit (Gate On Array, GOA for short) on the TFT (Thin Film Transistor, thin film transistor) array substrate, which can not only reduce the production process, but also reduce the cost. , and since a gate driver chip (Integrate Circuit, IC for short) is not required, the border can be made very narrow, and the integration degree of the TFT array substrate can be improved.

Oxide Thin Film Transistor (OTFT for short) among thin film transistors has become a hotspot in the development of thin film transistors due to its advantages such as high carrier mobility, low power consumption, and being applicable to low-frequency driving. The oxide thin film transistor means that the active layer in the thin film transistor is formed by metal oxide semiconductor.

In the prior art, since the thin film transistor in the pixel unit and the thin film transistor in the gate drive circuit are generally made of the same material, the thin film transistor in the pixel unit has good stability and the thin film transistor in the gate drive circuit has good stability. Transistors having a small size cannot be satisfied at the same time.

Contents of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can not only ensure the stability of the thin film transistors in the pixel unit, but also reduce the size of the thin film transistors in the gate driving circuit, so as to realize a narrow frame design.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, an array substrate is provided, including a pixel unit and a gate drive circuit; the pixel unit includes a first thin film transistor, the gate drive circuit includes a second thin film transistor, and the active The layer includes a first metal oxide pattern and a second metal oxide pattern that are stacked; the active layer of the second thin film transistor is a third metal oxide pattern; wherein, the optical stability of the second metal oxide pattern greater than the optical stability of the first metal oxide pattern, and the carrier mobility of the first metal oxide pattern and the third metal oxide pattern is greater than that of the second metal oxide pattern. child mobility.

Preferably, the material of the first metal oxide pattern and the third metal oxide pattern is selected from at least one of ZnO, ITZO, ITZTO, IZO, and ZTO; the material of the second metal oxide pattern is IGZO.

Preferably, the first metal oxide pattern and the third metal oxide pattern are made of the same material.

Preferably, the array substrate includes a base substrate, and the first metal oxide pattern is closer to the base substrate than the second metal oxide pattern.

Preferably, the thickness of the first metal oxide pattern, the second metal oxide pattern and the third metal oxide pattern is 10-50 nm.

Preferably, in a direction perpendicular to the array substrate, the first metal oxide pattern and the second metal oxide pattern completely overlap; or, the boundary of the second metal oxide pattern is between the first and second metal oxide patterns. within the boundaries of a metal oxide pattern.

In a second aspect, a display device is provided, including the above-mentioned array substrate.

Preferably, the display device is a liquid crystal display device or an OLED display device.

In a third aspect, a method for preparing an array substrate is provided. The array substrate includes a pixel unit and a gate driving circuit; the pixel unit includes a first thin film transistor, and the gate driving circuit includes a second thin film transistor. The preparation method of the array substrate includes: sequentially forming a first metal oxide thin film and a second metal oxide thin film; adopting a patterning process, patterning the first metal oxide thin film to form a first metal oxide pattern and a third metal oxide film. A metal oxide pattern, patterning the second metal oxide film to form a second metal oxide pattern on the first metal oxide pattern; wherein, the first metal oxide pattern and the second metal The oxide pattern is the active layer of the first thin film transistor, and the third metal oxide pattern is the active layer of the second thin film transistor.

Preferably, the patterning process is a double-slit diffraction patterning process or a half-tone mask patterning process.

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device. Since the active layer of the first thin film transistor in the pixel unit of the array substrate includes a double-layer structure (the first metal oxide pattern and the second metal oxide pattern , the active layer of the second thin film transistor in the gate drive circuit includes a single-layer structure (the third metal oxide pattern), and the optical stability of the second metal oxide pattern is greater than that of the first metal oxide pattern , that is, the optical stability of the second metal oxide pattern is better, thereby ensuring that the first thin film transistor of the pixel unit has good stability. On this basis, the first metal oxide pattern and the third metal oxide pattern The carrier mobility is greater than the carrier mobility of the second metal oxide pattern, that is, the carrier mobility of the third metal oxide pattern is higher, so the third metal oxide pattern is the second thin film transistor. When the active layer is used, the driving requirements of the gate driving circuit can be met, so the size of the second thin film transistor in the gate driving circuit can be reduced to realize a narrow frame design.

Compared with the prior art, the first thin film transistor in the pixel unit and the second thin film transistor in the gate drive circuit are made of the same material, the active layer of the first thin film transistor in the embodiment of the present invention adopts a double-layer structure, and the second The active layer of the second thin-film transistor adopts a single-layer structure, which can not only ensure the stability of the first thin-film transistor in the pixel unit, but also reduce the size of the second thin-film transistor in the gate drive circuit, so as to meet the narrow frame design requirements.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a first structural schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 2(a) is a first structural schematic diagram of an array substrate including a first thin film transistor and a second thin film transistor provided by an embodiment of the present invention;

FIG. 2(b) is a second structural schematic diagram of an array substrate including a first thin film transistor and a second thin film transistor provided by an embodiment of the present invention;

FIG. 2(c) is a structural schematic diagram 3 of an array substrate including a first thin film transistor and a second thin film transistor provided by an embodiment of the present invention;

FIG. 3 is a schematic flowchart of a method for preparing an array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic structural view of forming a first metal oxide film and a second metal oxide film provided by an embodiment of the present invention;

5 is a schematic structural diagram for forming a first metal oxide pattern, a second metal oxide pattern and a third metal oxide pattern according to an embodiment of the present invention;

FIG. 6 is a second structural schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 7 is a schematic structural view of forming a photoresist on the first metal oxide thin film and the second metal oxide thin film according to an embodiment of the present invention.

Reference signs:

01-display area; 02-non-display area; 03-pixel unit; 04-gate drive circuit; 10-first thin film transistor; 101-active layer of the first thin film transistor; 1011-first metal oxide pattern; 1012-second metal oxide pattern; 102-first gate; 103-first source; 104-first drain; 105-first gate insulating layer; 106-first pixel electrode; 107-first protection 20-the second thin film transistor; 201-the active layer of the second thin film transistor; 2011-the third metal oxide pattern; 202-the second gate; 203-the second source; 204-the second drain; 205-the second gate insulating layer; 206-the second pixel electrode; 207-the second protective layer; 30-the base substrate; 40-the first metal oxide film; 50-the second metal oxide film; 60-photolithography glue.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

None of the metal oxide semiconductors in the prior art can satisfy both good optical stability and high carrier mobility. Based on this, an embodiment of the present invention provides an array substrate, as shown in FIG. 1 and FIG. 2 , including a pixel unit 03 and a gate drive circuit 04; Two thin film transistors 20, the active layer 101 of the first thin film transistor 10 includes a first metal oxide pattern 1011 and a second metal oxide pattern 1012 stacked; the active layer 201 of the second thin film transistor 20 is a third metal oxide object pattern 2011; wherein, the optical stability of the second metal oxide pattern 2011 is greater than the optical stability of the first metal oxide pattern 1011, and the carrier migration of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 The rate is greater than the carrier mobility of the second metal oxide pattern 1012.

It should be noted that, first, as shown in FIG. 1 , the array substrate is divided into a display area 01 and a non-display area 02 surrounding the display area 01, the pixel unit 03 is arranged in the display area 01 of the array substrate, and the gate drive circuit 04 is arranged In the non-display area 02 of the array substrate. Wherein, the gate driving circuit 04 may be disposed on one side of the display area 01 , or may be disposed on both sides of the display area 01 , which is not limited here. In FIG. 1 of the embodiment of the present invention, the gate driving circuit 04 is arranged on both sides of the display area 01 as an example.

Second, optical stability refers to the stability of materials to photochemical reactions. Material molecules become new chemical species in a transiently excited state after absorbing light, and then undergo decomposition or coupling reactions to transform into new structures. The photostability of a material refers to the ability of the material to resist new chemical species that generate this transient excited state after exposure to light.

The higher the optical stability of the metal oxide in the thin film transistor, the smaller the shift degree of the transfer characteristic curve of the thin film transistor under different intensities of blue light illumination under the condition of NBIS (negative bias illumination stress). The smaller the deviation of the transfer characteristic curve of the thin film transistor is, the more stable the performance of the thin film transistor is. Exemplarily, the active layer of the third thin film transistor includes only the first metal oxide pattern 1011, the active layer of the fourth thin film transistor includes only the second metal oxide pattern 1012, and other parts of the third thin film transistor and the fourth thin film transistor The materials of the film layers are all the same, if the optical stability of the second metal oxide pattern 1012 is greater than that of the first metal oxide pattern 1011, that is, in the case of NBIS, the third thin film transistor and the fourth thin film transistor have different intensities Under blue light, the shift degree of the transfer characteristic curve of the third thin film transistor is greater than the shift degree of the transfer characteristic curve of the fourth thin film transistor, that is, the active layer of the thin film transistor includes the second metal oxide pattern 1012, and the shift degree of the transfer characteristic curve of the thin film transistor is The performance is relatively stable.

Third, as shown in FIG. 2(a), FIG. 2(b) and FIG. 2(c), the first thin film transistor 10 not only includes the active layer 101, but also includes a first gate 102, a first source 103 , the first drain 104 and the first gate insulating layer 105; wherein, the first source 103 and the first drain 104 are in contact with the active layer 101 of the first thin film transistor 10; similarly, the second thin film transistor 20 except In addition to the active layer 201, it also includes a second gate 202, a second source 203, a second drain 204 and a second gate insulating layer 205; wherein, the second source 203 and the second drain 204 are both connected to the first The active layer 201 of the two thin film transistors 20 is in contact.

Here, the first thin film transistor 10 in the pixel unit 03 and the second thin film transistor 20 in the gate driving circuit 04 can be formed at the same time, specifically, the first gate 102 and the second gate 202 can be formed at the same time, the first The gate insulating layer 105 and the second gate insulating layer 205 can be formed at the same time, and the first source 103 , the first drain 104 and the second source 203 and the second drain 204 can be formed at the same time.

On this basis, the first thin film transistor 10 and the second thin film transistor 20 may be bottom gate thin film transistors or top gate thin film transistors. In the drawings of the embodiments of the present invention, the first thin film transistor 10 and the second thin film transistor 20 are all bottom-gate thin film transistors as an example for illustration.

Wherein, as shown in FIG. 2( a ), FIG. 2( b ) and FIG. 2( c ), the first thin film transistor 10 and the second thin film transistor 20 may both be fabricated on the base substrate 30 .

Fourth, there is no limitation on which metal oxides to choose for the first metal oxide pattern 1011, the second metal oxide pattern 1012, and the third metal oxide pattern 2011, as long as the optical properties of the second metal oxide pattern 1012 are satisfied. The stability is greater than the optical stability of the first metal oxide pattern 1011, that is, the optical stability of the second metal oxide pattern 1012 is better, and the carrier migration of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 The carrier mobility of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 only needs to be higher than the carrier mobility of the second metal oxide pattern 1012 .

Fifth, the material of the first metal oxide pattern 1011 in the first thin film transistor 10 and the material of the third metal oxide pattern 2011 in the second thin film transistor 20 may be the same or different. In the drawings of the embodiments of the present invention, the material of the first metal oxide pattern 1011 and the material of the third metal oxide pattern 2011 are the same as an example for illustration.

There is no limitation on the positions of the first metal oxide pattern 1011 and the second metal oxide pattern 1012 in the active layer 101 of the first thin film transistor 10, which may be the first metal oxide pattern as shown in FIG. 2(a). 1011 is disposed on the top, or the second metal oxide pattern 1012 is disposed on the top as shown in FIG. 2( b ) and FIG. 2( c ).

Sixth, since the optical stability of the second metal oxide pattern 1012 is greater than the optical stability of the first metal oxide pattern 1011, that is, the optical stability of the second metal oxide pattern 1012 is better, the first thin film transistor 10 has The source layer 101 includes the second metal oxide pattern 1012, and thus the formed first thin film transistor 10 has good stability.

On this basis, the carrier mobility of the first metal oxide pattern 1011 is greater than the carrier mobility of the second metal oxide pattern 1012, that is, the carrier mobility of the first metal oxide pattern 1011 is higher, The active layer 101 of the first thin film transistor 10 includes the first metal oxide pattern 1011 , so that the formed first thin film transistor 10 has good switching characteristics.

Seventh, if the carrier mobility of the active layer 201 of the second thin film transistor 20 is low, the on-state current of the second thin film transistor 20 is small, so when making the second thin film transistor 20, it needs to be designed larger. The size of the active layer 201 meets the driving requirements, which leads to a larger size of the second thin film transistor 20 , and finally makes the size of the gate driving circuit 04 larger, which is not conducive to the realization of the narrow border technology.

Based on the above, the active layer 201 of the second thin film transistor 20 in the embodiment of the present invention is the third metal oxide pattern 2011, and the carrier mobility of the third metal oxide pattern 2011 is greater than that of the second metal oxide pattern 1012. Carrier mobility, that is, the carrier mobility of the third metal oxide pattern 2011 is relatively high, and the active layer 201 of the second thin film transistor 20 includes the third metal oxide pattern 2012, thus forming the second thin film transistor The on-state current of 20 is large and has good switching characteristics.

Here, since the gate drive circuit 04 is completely blocked by the black matrix, the active layer 201 of the second thin film transistor 20 in the gate drive circuit 04 will not be affected by light, that is, the second thin film transistor 20 can maintain a stable thin film transistor properties.

An embodiment of the present invention provides an array substrate. Since the active layer 101 of the first thin film transistor 10 in the pixel unit 03 includes a double-layer structure (the first metal oxide pattern 1011 and the second metal oxide pattern 1012), the gate The active layer 201 of the second thin film transistor 20 in the driving circuit 04 includes a single-layer structure (the third metal oxide pattern 2011), and the optical stability of the second metal oxide pattern 1012 is greater than that of the first metal oxide pattern 1011. The optical stability, that is, the optical stability of the second metal oxide pattern 1012 is relatively good, thus ensuring good stability of the first thin film transistor 10 of the pixel unit 03 . On this basis, the carrier mobility of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 is greater than the carrier mobility of the second metal oxide pattern 1012, that is, the carrier mobility of the third metal oxide pattern 2011. The carrier mobility is relatively high, so when the third metal oxide pattern 2011 is the active layer 201 of the second thin film transistor 20, it can meet the driving requirements of the gate drive circuit 04, so the gate drive circuit can be reduced in size. 04, the size of the second thin film transistor 20 is used to achieve a narrow border design.

Compared with the prior art, the first thin film transistor 10 in the pixel unit 03 and the second thin film transistor 20 in the gate driving circuit 04 are made of the same material, the active layer 101 in the first thin film transistor 10 in the embodiment of the present invention A double-layer structure is adopted, and the active layer 201 of the second thin film transistor 20 adopts a single-layer structure, which can not only ensure the stability of the first thin film transistor 10 in the pixel unit 03, but also reduce the size of the second thin film transistor in the gate drive circuit 01. The size of the transistor 20 can meet the design requirement of narrow frame.

Preferably, the materials of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 are selected from ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin zinc oxide), and Tin oxide), ZTO (zinc tin oxide); the material of the second metal oxide pattern 1012 is IGZO (indium gallium zinc oxide).

Among them, ZnO, ITZO, ITZTO, IZO, and ZTO all belong to metal oxides with high carrier mobility, and IGZO is a metal oxide with good photostability.

Here, it should be noted that ZnO, ITZO, ITZTO, IZO, and ZTO have high carrier mobility but poor optical stability; while IGZO has good optical stability but low carrier mobility.

Due to the high carrier mobility of ZnO, ITZO, ITZTO, IZO, and ZTO, the on-state current of the second thin film transistor 20 is relatively large, so that the size of the active layer 201 in the second thin film transistor 20 can be designed smaller , finally making the size of the second thin film transistor 20 smaller. Since the optical stability of IGZO is better, the active layer 101 of the first thin film transistor 10 formed by using IGZO has better light stability. On this basis, since the active layer 101 of the first thin film transistor 10 also includes the first metal oxide pattern 1011, the on-state current of the first thin film transistor 10 is relatively large, and thus the active layer 101 of the first thin film transistor 10 can be The size of the layer 101 is designed to be small, so that the size of the first thin film transistor 20 is small.

Preferably, the materials of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 are the same.

Wherein, both the first metal oxide pattern 1011 and the third metal oxide pattern 2011 are selected from materials with higher carrier mobility.

In the embodiment of the present invention, since the first metal oxide pattern 1011 and the third metal oxide pattern 2011 are made of the same material, the first metal oxide pattern 1011 and the third metal oxide pattern 2011 can be formed at the same time, thereby simplifying the first Manufacturing process of the thin film transistor 10 and the second thin film transistor 20 .

Preferably, as shown in FIG. 2( b ) and FIG. 2( c ), the array substrate includes a base substrate 30 , and the first metal oxide pattern 1011 is closer to the base substrate 30 than the second metal oxide pattern 1012 .

Here, the carrier mobility of the first metal oxide pattern 1011 is high, but the optical stability is not good, so the first metal oxide pattern 1011 is disposed below, and the second metal oxide pattern 1012 is disposed above, so that The second metal oxide pattern 1012 can protect the first metal oxide pattern 1011 and reduce the light received by the first metal oxide pattern 1011 so that the first thin film transistor 10 can maintain stable characteristics.

In addition, when the materials of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 are the same, the first gold oxide pattern 1011 is arranged closer to the base substrate 30 than the second metal oxide pattern 1012, so that The first metal oxide pattern 1011 , the second metal oxide pattern 1012 and the third metal oxide pattern 2011 can be formed by one patterning process, thereby simplifying the manufacturing process of the first thin film transistor 10 and the second thin film transistor 20 .

Preferably, the thickness of the first metal oxide pattern 1011 , the second metal oxide pattern 1012 and the third metal oxide pattern 2011 is 10-50 nm.

Wherein, the thicknesses of the first metal oxide pattern 1011 , the second metal oxide pattern 1012 and the third metal oxide pattern 2011 may be the same or different.

Because if the thickness of the active layer in the thin film transistor is too small, it may not be possible to ensure that the thin film transistor has good switching characteristics; if the thickness of the active layer is too large, it will increase the manufacturing cost of the thin film transistor, so the preferred embodiment of the present invention The thickness of the first metal oxide pattern 1011, the second metal oxide pattern 1012 and the third metal oxide pattern 2011 is 10-50 nm, so as to ensure that the first thin film transistor 10 and the second thin film transistor 20 have good switching characteristics, And the manufacturing cost of the first thin film transistor 10 and the second thin film transistor 20 can be reduced.

Preferably, in a direction perpendicular to the array substrate, as shown in FIG. 2(b), the first metal oxide pattern 1011 and the second metal oxide pattern 1012 completely overlap; or, as shown in FIG. 2(c), The boundary of the second metal oxide pattern 1012 is within the boundary of the first metal oxide pattern 1011 .

In the embodiment of the present invention, in the direction perpendicular to the array substrate, the first metal oxide pattern 1011 and the second metal oxide pattern 1012 completely overlap; or, the boundary of the second metal oxide pattern 1012 is at the When within the boundary of the pattern 1011, the first metal oxide pattern 1011 and the second metal oxide pattern 1012 of the first thin film transistor 10 can be formed simultaneously through one patterning process.

An embodiment of the present invention provides a display device, including the above-mentioned array substrate.

Wherein, the display device provided in this embodiment may be any device that displays images whether moving (for example, video) or fixed (for example, still images), and regardless of text or pictures. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP3 players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., mileage instrument displays, etc.), navigators, cockpit controls and/or displays, camera view displays (e.g., rear view camera displays in vehicles), electronic photographs, electronic billboards or signage, projectors, architectural structures, packaging and Aesthetic structures (eg, for a display of an image of a piece of jewelry), etc. It may also be a display component such as a display panel.

An embodiment of the present invention provides a display device. Since the display device includes the above-mentioned array substrate, and the active layer 101 of the first thin film transistor 10 in the pixel unit 03 of the array substrate includes a double-layer structure (the first metal oxide pattern 1011 and the second metal oxide pattern 1012), the active layer 201 of the second thin film transistor 20 in the gate driving circuit 04 includes a single-layer structure (the third metal oxide pattern 2011), and the second metal oxide pattern 1012 The optical stability is greater than the optical stability of the first metal oxide pattern 1011 , that is, the optical stability of the second metal oxide pattern 1012 is better, thus ensuring good stability of the first thin film transistor 10 of the pixel unit 03 . On this basis, the carrier mobility of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 is greater than the carrier mobility of the second metal oxide pattern 1012, that is, the carrier mobility of the third metal oxide pattern 2011. The carrier mobility is relatively high, so when the third metal oxide pattern 2011 is the active layer 201 of the second thin film transistor 20, it can meet the driving requirements of the gate drive circuit 04, so the gate drive circuit can be reduced in size. 04, the size of the second thin film transistor 20 is used to achieve a narrow border design.

Compared with the prior art, the first thin film transistor 10 in the pixel unit 03 and the second thin film transistor 20 in the gate driving circuit 04 are made of the same material, the active layer 101 in the first thin film transistor 10 in the embodiment of the present invention A double-layer structure is adopted, and the active layer 201 of the second thin film transistor 20 adopts a single-layer structure, which can not only ensure the stability of the first thin film transistor 10 in the pixel unit 03, but also reduce the size of the second thin film transistor in the gate drive circuit 01. The size of the transistor 20 can make the display device meet the narrow frame design requirements.

Preferably, the display device is a liquid crystal display device or an OLED (Organic Light Emitting Diode, organic electroluminescence diode) display device.

Wherein, when the display device is an OLED display device, in addition to the array substrate, the display device also includes a packaging substrate; when the display device is a liquid crystal display device, in addition to the array substrate, the display device also includes a cell substrate. At this time, The color film layer can be arranged on the array substrate, and can also be arranged on the cell-matching substrate.

The embodiment of the present invention also provides a preparation method of an array substrate, the array substrate includes a pixel unit 03 and a gate driving circuit 04 ; the pixel unit 03 includes a first thin film transistor 10 , and the gate driving circuit 04 includes a second thin film transistor 20 .

As shown in Figure 3, the preparation method of the array substrate includes:

S100 , as shown in FIG. 4 , sequentially form a first metal oxide film 40 and a second metal oxide film 50 .

Wherein, the specific materials of the first metal oxide film 40 and the second metal oxide film 50 are not limited, as long as the carrier mobility of the first metal oxide film 40 is greater than that of the second metal oxide film 50. Carrier mobility, the optical stability of the second metal oxide film 50 is greater than the optical stability of the first metal oxide film 40, that is, the carrier mobility of the first metal oxide film 40 is higher, and the second The optical stability of the metal oxide thin film 50 is relatively good.

Here, the first thin film transistor 10 and the second thin film transistor 20 may be bottom gate thin film transistors or top gate thin film transistors. In the case that the first thin film transistor 10 and the second thin film transistor 20 are bottom-gate thin film transistors, before step S100, the method for preparing the array substrate further includes forming a metal thin film on the base substrate 30, and forming a second thin film transistor through a patterning process. A gate 102 and a second gate 202 , and a gate insulating layer (shown as 205 or 105 in FIG. 4 ) is formed on the first gate 102 and the second gate 202 .

S101, as shown in FIG. 5, adopt a patterning process to pattern the first metal oxide film 40 to form a first metal oxide pattern 1011 and a third metal oxide pattern 1012, and pattern the second metal oxide film 50 to form a The second metal oxide pattern 1012 on the first metal oxide pattern 1011 .

Wherein, the first metal oxide pattern 1011 and the second metal oxide pattern 1012 are the active layer 101 of the first thin film transistor 10 , and the third metal oxide pattern 2011 is the active layer 201 of the second thin film transistor 20 .

It should be noted that, after forming the active layer 101 of the first thin film transistor 10 (including the first metal oxide pattern 1011 and the second metal oxide pattern 1012) and the active layer 201 of the second thin film transistor 20 (the third metal oxide pattern After the oxide pattern 2011), the preparation method of the array substrate further includes, as shown in FIG. layer 107 and the second protective layer 207, the first protective layer 107 and the second protective layer 207 can be formed in the same layer, and then the first pixel electrode 106 and the second pixel electrode 206 are formed, wherein the first pixel electrode 106 and the second pixel electrode One drain 104 is connected, and the second pixel electrode 206 is connected to the second drain 204 .

An embodiment of the present invention provides a method for manufacturing an array substrate. The active layer 101 of the first thin film transistor 10 in the pixel unit 03 includes a double-layer structure (a first metal oxide pattern 1011 and a second metal oxide pattern 1012), The active layer 201 of the second thin film transistor 20 in the gate drive circuit 04 includes a single-layer structure (the third metal oxide pattern 2011), and the optical stability of the second metal oxide pattern 1012 is greater than that of the first metal oxide pattern The optical stability of 1011 , that is, the optical stability of the second metal oxide pattern 1012 is better, so that the first thin film transistor 10 of the pixel unit 03 can be ensured to have good stability. On this basis, the carrier mobility of the first metal oxide pattern 1011 and the third metal oxide pattern 2011 is greater than the carrier mobility of the second metal oxide pattern 1012, that is, the carrier mobility of the third metal oxide pattern 2011. The carrier mobility is relatively high, so when the third metal oxide pattern 2011 is the active layer 201 of the second thin film transistor 20, it can meet the driving requirements of the gate drive circuit 04, so the gate drive circuit can be reduced in size. 04, the size of the second thin film transistor 20 is used to achieve a narrow border design.

Compared with the prior art, the first thin film transistor 10 in the pixel unit 03 and the second thin film transistor 20 in the gate driving circuit 04 are made of the same material, the active layer 101 in the first thin film transistor 10 in the embodiment of the present invention A double-layer structure is adopted, and the active layer 201 of the second thin film transistor 20 adopts a single-layer structure, which can not only ensure the stability of the first thin film transistor 10 in the pixel unit 03, but also reduce the size of the second thin film transistor in the gate drive circuit 01. The size of the transistor 20 can make the display device meet the narrow frame design requirements.

Preferably, as shown in FIG. 7 , the above-mentioned patterning process is a double-slit diffraction patterning process or a half-tone mask patterning process.

Wherein, the double-slit diffraction patterning process or the half-tone mask patterning process includes: as shown in FIG. The active layer 101 of 10 and the photoresist 60 outside the corresponding positions of the active layer 201 of the second thin film transistor 20, and then, as shown in FIG. The oxide pattern 1012 and the third metal oxide pattern 2011.

In the embodiment of the present invention, the active layer 101 (including the first metal oxide pattern 1011 and the second metal oxide pattern 1012) of the first thin film transistor 10 can be formed at one time by using the double-slit diffraction patterning process or the half-tone mask patterning process and the active layer 201 (third metal oxide pattern 2011 ) of the second thin film transistor 20 , which simplifies the manufacturing process of the first thin film transistor 10 and the second thin film transistor 20 .

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. an array base palte, including pixel cell and gate driver circuit；Described pixel cell includes the first film transistor, Described gate driver circuit includes the second thin film transistor (TFT), it is characterised in that

The active layer of described the first film transistor includes the first metal oxide pattern and the second burning that stacking arranges Article pattern；The active layer of described second thin film transistor (TFT) is the 3rd metal oxide pattern；

Wherein, the optical stability of described second metal oxide pattern is steady more than the optics of described first metal oxide pattern Qualitative, the carrier mobility of described first metal oxide pattern and described 3rd metal oxide pattern is more than described second The carrier mobility of metal oxide pattern.

Array base palte the most according to claim 1, it is characterised in that described first metal oxide pattern and the described 3rd At least one in ZnO, ITZO, ITZTO, IZO, ZTO of the material of metal oxide pattern；

The material of described second metal oxide pattern is IGZO.

Array base palte the most according to claim 1, it is characterised in that described first metal oxide pattern and the described 3rd The material of metal oxide pattern is identical.

4. according to the array base palte described in any one of claim 1-3, it is characterised in that described array base palte includes substrate base Plate, described first metal oxide pattern compared to described second metal oxide pattern near described underlay substrate.

Array base palte the most according to claim 1, it is characterised in that described first metal oxide pattern, described second The thickness of metal oxide pattern and described 3rd metal oxide pattern is 10-50nm.

Array base palte the most according to claim 4, it is characterised in that on the direction being perpendicular to described array base palte, institute State the first metal oxide pattern and described second metal oxide pattern is completely superposed；Or, described second metal-oxide The border of pattern is within the border of described first metal oxide pattern.

7. a display device, it is characterised in that include the array base palte described in any one of claim 1-6.

Display device the most according to claim 7, it is characterised in that described display device is liquid crystal indicator or OLED Display device.

9. the preparation method of an array base palte, it is characterised in that described array base palte includes pixel cell and raster data model electricity Road；Described pixel cell includes that the first film transistor, described gate driver circuit include the second thin film transistor (TFT)；

The preparation method of described array base palte includes:

Sequentially form the first metal-oxide film and the second metal-oxide film；

Use a patterning processes, described first metal-oxide film composition is formed the first metal oxide pattern and the 3rd Metal oxide pattern, is formed described second metal-oxide film composition and is positioned on described first metal oxide pattern Second metal oxide pattern；

Wherein, described first metal oxide pattern and described second metal oxide pattern are described the first film transistor Active layer, described 3rd metal oxide pattern is the active layer of described second thin film transistor (TFT).

Preparation method the most according to claim 9, it is characterised in that described patterning processes is two-slit diffraction patterning processes Or intermediate tone mask plate patterning processes.