CN106057124A - Signal generating circuit and method thereof - Google Patents

Abstract

The invention discloses a signal generating circuit and a method thereof. The circuit has first to sixth switches. The first terminal of the first switch is coupled to the output node, the second terminal receives the lighting clock signal, and the control terminal receives the first control signal. The first terminal of the second switch is coupled to the first node, the second terminal receives the lighting clock signal, and the control terminal receives the first control signal. The first terminal and the control terminal of the third switch receive the first voltage signal, and the second terminal is coupled to the first node. The first terminal of the fourth switch receives the first voltage signal, the second terminal is coupled to the output node, and the control terminal is coupled to the first node. The first terminal of the fifth switch receives the first voltage signal, and the second terminal is coupled to the second node. The first terminal of the sixth switch is coupled to the second node, the second terminal receives the second voltage signal, and the control terminal receives the second control signal. One end of the capacitor is coupled to the first node, and the other end is coupled to the second node.

Description

Signal generating circuit and method thereof

technical field

The present invention relates to a signal generation circuit and its method, in particular to a signal generation circuit for generating signals to drive pixel circuits.

Background technique

At present, display panel technology often uses a shift register circuit (shift register) to provide the scan signal required in the pixel circuit. Currently, the display panel often adopts a gate driver on array (GOA) technology to provide scanning signals required by pixel circuits. Compared with the traditional display panel using gate driver ICs made of silicon wafers, the display panel using the GOA circuit can be combined with the TFT array manufacturing process of the display panel, so the production of the display panel Costs can be further reduced.

The pixel circuits in the display panel are used to drive the light emitting diodes in the pixels, so that the light emitting diodes emit light according to the data voltage. At present, some pixel circuits drive pixels not only according to the scan signal, but also according to the EM signal, and the EM signal is generated by the signal generation circuit according to the control signal of the shift register circuit. Although the current signal generating circuit can provide the luminous signal for driving the pixel circuit, it often causes leakage current due to the insufficient driving voltage of some switches in the circuit, which further affects the luminous signal output by the signal generating circuit and cannot provide a sufficient long-term The high voltage level often makes the pixel circuit unable to completely drive the pixel in one frame time.

Contents of the invention

The present invention provides a signal generating circuit and its method, so as to solve the situation that some switches in the existing signal generating circuit have leakage current.

The signal generating circuit disclosed in the present invention has a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a capacitor. The first end of the first switch is electrically connected to the output node, the second end of the first switch receives the light-emitting clock signal, and the control end of the first switch receives the first control signal. The first end of the second switch is electrically connected to the first node, the second end of the second switch receives the light-emitting clock signal, and the control end of the second switch receives the first control signal. The first end and the control end of the third switch receive the first voltage signal, and the second end of the third switch is electrically connected to the first node. The first end of the fourth switch receives the first voltage signal, the second end of the fourth switch is electrically connected to the output node, and the control end of the fourth switch is electrically connected to the first node. The first end of the fifth switch receives the first voltage signal, and the second end of the fifth switch is electrically connected to the second node. The first terminal of the sixth switch is electrically connected to the second node, the second terminal of the sixth switch receives the second voltage signal, and the control terminal of the sixth switch receives the second control signal. One end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the second node.

The signal generating circuit disclosed in the present invention has a signal generating module, a coupling element, a first control switch and a second control switch. The signal generating module receives the light-emitting clock signal and the first voltage signal, and is used for adjusting the voltage level of the first node according to the first control signal, and generating an output signal according to the voltage level of the first node. One end of the coupling element is electrically coupled to the first node, and the other end is electrically coupled to the second node. The first control switch receives the first voltage signal to increase the voltage level of the second node. The second control switch receives the second voltage signal and is used for pulling down the voltage level of the second node according to the second control signal.

The signal generating method disclosed in the present invention is suitable for a signal generating circuit. The signal generating method provides a light-emitting clock signal to a first node and an output node according to a first control signal, and the output node is used for outputting a driving signal. According to the first control signal, a first voltage signal is provided to the first node. According to the voltage level of the first node, a first voltage signal is provided to the output node. According to the second control signal, the first voltage signal is provided to the second node. The voltage level of the first node is coupled with the voltage level of the second node.

According to the signal generation circuit and method disclosed in the present invention, by adjusting the voltage level of the second node, and then coupling the voltage level of the second node to the first node, the voltage level of the first node can be further improved In order to improve, the first node has a sufficiently high voltage level, so that the signal generating circuit can output a signal within a relatively long time interval according to the voltage level of the first node.

The above descriptions about the present disclosure and the following descriptions of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide further explanations of the patent protection scope of the present invention.

Description of drawings

FIG. 1 is a schematic diagram of a shift register and a signal generating circuit respectively providing scanning signals and light emitting signals according to an embodiment of the present invention.

FIG. 2A is a schematic circuit diagram of a shift register according to an embodiment of the invention.

FIG. 2B is a voltage timing diagram of the shift register according to the embodiment shown in FIG. 2A .

FIG. 3A is a schematic diagram of a signal generating circuit according to an embodiment of the present invention.

FIG. 3B is a voltage timing diagram of the signal generating circuit shown in the embodiment shown in FIG. 3A .

FIG. 4A is a schematic diagram of a signal generating circuit according to another embodiment of the present invention.

FIG. 4B is a voltage timing diagram of the signal generating circuit shown in the embodiment shown in FIG. 4A .

FIG. 5 is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention.

FIG. 6A is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention.

FIG. 6B is a voltage timing diagram of the signal generating circuit shown in the embodiment shown in FIG. 6A .

FIG. 7A is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention.

FIG. 7B is a voltage timing diagram of the signal generating circuit shown in the embodiment shown in FIG. 7A .

FIG. 8 is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention.

FIG. 9 is a flow chart of steps of a signal generating method according to an embodiment of the present invention.

Among them, reference signs:

10 Gate drive circuit

101 shift register

102, 20, 30, 40, 50, 60, 70 signal generating circuit

51, 61, 71 signal generation module

T1, M1, X1, U1 first switch

T2, M2, X2, U2 second switch

T3, M3, X3, U3 third switch

T4, M4, X4, U4 fourth switch

T5, M5, X5 fifth switch

T6, M6, X6 sixth switch

a1, b1, d1, e1 first node

a2, b2, d2, e2 second node

out1, out2, out3, out4, out5, out6 output nodes

V1, W1, Y1 first control switch

V2, W2, Y2 second control switch

W3, Y3 third control switch

C, Ca, Cb, Cd, Ce, Cf, Cg capacitance

Scan(n-1), Scan(n), Scan(n+1) scan signal

EM(n), EM(n+1) Luminous signal

ECK Light-emitting clock signal

SCK scan clock signal

Q(n) first control signal

Q(n+1) Second control signal

Va1, Vb1 signal on the first node

Va2, Vb2 signal on the second node

t1, t2, t3 time points

P1 First Operational Phase

P2 second stage of operation

Vth3, Vth4 threshold voltage

VGH first voltage signal

VGL second voltage signal

N1 drive switch

N2 first pull-up switch

N3 Main pull-up switch

N4 Master pull-down switch

N5 first pull-down switch

N6 second pull-down switch

nd1 node

nd2, nd3 output nodes

detailed description

The detailed features and advantages of the present invention are described in detail below in the implementation manner, and its content is enough to make any person skilled in the art understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of protection of the claims and With the accompanying drawings, any person skilled in the art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the concept of the present invention in detail, but do not limit the scope of the present invention in any way.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a shift register and a signal generating circuit respectively providing scanning signals and light emitting signals according to an embodiment of the present invention. As shown in the figure, in the gate driving circuit 10 of the display panel, there are multi-level shift registers 101 and multi-level signal generating circuits 102, and each level of shift registers 101 is used to provide scanning signals to the pixel circuits For example, the shift register 101 of the nth stage provides the scanning signal Scan(n) to the pixel circuit, and provides the control signal Q(n) to the signal generating circuit 102 of the nth stage, so that the signal generating circuit 102 can make the signal generating circuit 102 according to the control signal Q(n) ), providing the light emitting signal EM(n) to the pixel circuit. The shift register 101 of the nth stage also provides the gate drive signal G(n) to the shift register of the next stage, so that the shift register of the next stage generates according to the gate drive signal G(n) The scanning signal Scan(n+1), the control signal Q(n+1) and the gate driving signal G(n+1). The pixel circuit drives the light-emitting diodes in the pixels according to the scanning signal and the light-emitting signal provided by the shift register 101 and the signal generating circuit 102, and makes the light-emitting diodes emit light according to the data voltage.

In one embodiment, as shown in FIG. 2A , the nth stage shift register 101 has a driving switch N1, a first pull-up switch N2, a capacitor C, a main pull-up switch N3, a main pull-down switch N4, a first The pull-down switch N5 and the second pull-down switch N6. The driving switch N1 , the first pull-up switch N2 , the main pull-up switch N3 , the main pull-down switch N4 , the first pull-down switch N5 and the second pull-down switch N6 respectively have a first terminal, a second terminal and a control terminal. The first end and the control end of the drive switch N1 are electrically connected to the gate drive signal output node of the previous stage shift register to receive the gate drive signal G(n-1) output by the previous stage shift register ). The second end of the driving switch N1 is electrically connected to the node nd1 of the control signal Q(n). The first end of the first pull-up switch N2 receives the clock signal CK, the second end of the first pull-up switch N2 is electrically connected to the output node nd2 of the gate drive signal G(n), and the control of the first pull-up switch N2 The terminal is electrically connected to the node nd1. One end of the capacitor C is electrically connected to the node nd1, and the other end is electrically connected to the output node nd2. The first end of the main pull-up switch N3 receives the scan clock signal SCK, the second end of the main pull-up switch N3 is electrically connected to the output node nd3 of the scan signal Scan(n), and the control end of the main pull-up switch N3 is electrically connected to Node nd1.

The first end of the main pull-down switch N4 is electrically connected to the output node nd3, the second end of the main pull-down switch N4 receives the second voltage signal VGL, and the control end of the main pull-down switch N4 receives the pull-down control signal P(n+1). The first end of the first pull-down switch N5 is electrically connected to the output node nd2, the second end of the first pull-down switch N5 receives the second voltage signal VGL, and the control end of the first pull-down switch N5 receives the pull-down control signal P(n ). The first terminal of the second pull-down switch N6 is electrically connected to the node nd1, the second terminal of the second pull-down switch N6 receives the second voltage signal VGL, and the control terminal of the second pull-down switch N6 receives the pull-down control signal P(n).

The voltage timing diagram of the nth stage shift register 101 is shown in FIG. 2B , and FIG. 2B is a voltage timing diagram of the shift register according to the embodiment shown in FIG. 2A . At the time point t1, the voltage of the gate drive signal G(n-1) output by the shift register of the previous stage driving the switch N1 rises, and the voltage of the node nd1 rises, and then the voltage of the node nd1 is subjected to the first upper The first end of the pull-up switch N2 receives the coupling capacitance between the clock signal CK and swings, and the first end of the main pull-up switch N3 receives the scanning clock signal SCK and swings due to the coupling capacitance between the scanning clock signal SCK, for example, in time The period from point t2 to time point t3. During the period from time point t2 to time point t3, when the control signal Q(n) at the node nd1 is at a high voltage level, the first pull-up switch N2 and the main pull-up switch N3 are turned on, and the clock signal CK is provided to the output Node nd2, the voltage of the gate driving signal G(n) output from the output node nd2 swings with the clock signal CK. The scan clock signal SCK is provided to the output node nd3, and the voltage of the scan signal Scan(n) output from the output node nd3 swings with the scan clock signal SCK.

At time point t3, the voltage of the pull-down control signal P(n) rises, the first pull-down switch N5 and the second pull-down switch N6 are turned on, and the node nd1 and the output node nd2 are provided with the second voltage signal VGL. The main pull-up switch N3 is not turned on, the voltage of the scan signal Scan(n) output by the output node nd3 no longer swings with the scan clock signal SCK, until the time point t4, the voltage of the pull-down control signal P(n+1) rises , the main pull-down switch N4 is turned on, the output node nd3 is provided with the second voltage signal VGL, and the voltage of the scan signal Scan(n) output from the output node nd3 drops. Accordingly, the shift register 101 of the nth stage can generate the scanning signal Scan(n), the control signal Q(n) and the gate driving signal G(n), so that the nth stage signal generating circuit 102 can generate the signal according to the control signal Q (n) to operate, the n+1th stage shift register can be operated according to the gate drive signal G(n), and the pixel circuit is based on the scanning signal Scan(n) and the light-emitting signal generated by the signal generating circuit 102 , to drive the LEDs in the pixels. For the specific operation method, please refer to the description of the Chinese invention patent application publication number CN104332182A. The above-mentioned shift register is only an example of a feasible circuit structure. The signal generation circuit disclosed below can be used with other kinds of shift registers. device with the following signal generation circuit.

Other feasible shift registers such as the gate drive circuit disclosed in Taiwan Invention Patent Publication No. I511459, or changing the output signal ST(n+1) of the transistor T31 control terminal in the I511459 patent to the output signal ST(n+ 2) The realized shift register. The control signal Q(n) generated by other shift registers can meet the signals required by the following signal generators, and can be used as the shift registers matched with the signal generators in the following embodiments.

Next, the circuit configuration of the signal generation circuit will be described. Please refer to FIG. 3A and FIG. 3B together. FIG. 3A is a schematic diagram of a signal generation circuit according to an embodiment of the present invention, and FIG. 3B is a voltage timing diagram of the signal generation circuit according to the embodiment of FIG. 3A . As shown in the figure, the signal generating circuit 20 has a first switch T1 , a second switch T2 , a third switch T3 , a fourth switch T4 , a fifth switch T5 , a sixth switch T6 and a capacitor Ca. The first terminal of the first switch T1 is electrically connected to the output node out1, the second terminal of the first switch T1 receives the light emitting clock signal ECK, and the control terminal of the first switch T1 receives the first control signal Q(n). The first terminal of the second switch T2 is electrically connected to the first node a1, the second terminal of the second switch T2 receives the light emitting clock signal ECK, and the control terminal of the second switch T2 receives the first control signal Q(n). The first end and the control end of the third switch T3 receive the first voltage signal VGH, and the second end of the third switch T3 is electrically connected to the first node a1. The first end of the fourth switch T4 receives the first voltage signal VGH, the second end of the fourth switch T4 is electrically connected to the output node out1, and the control end of the fourth switch T4 is electrically connected to the first node a1. The first terminal and the control terminal of the fifth switch T5 receive the first voltage signal VGH, and the second terminal of the fifth switch T5 is electrically connected to the second node a2. The first end of the sixth switch T6 is electrically connected to the second node a2, the second end of the sixth switch T6 receives the second voltage signal VGL, and the control end of the sixth switch T6 receives the second control signal Q(n+1). One end of the capacitor Ca is electrically connected to the first node a1, and the other end is electrically connected to the second node a2.

In conjunction with the voltage timing diagram shown in FIG. 3B , in the first operation phase P1, when the voltage level of the first control signal Q(n) output by the shift register rises, the first switch T1 and the second The switch T2 is turned on, and the light-emitting clock signal ECK is provided to the output node out1 and the first node a1, and the light-emitting signal EM(n) output from the output node out1 and the voltage signal on the first node a1 drop. In the voltage sequence diagram of FIG. 3B , the signal on the first node a1 is represented by Va1 , and the signal on the second node a2 is represented by Va2 . The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 20 .

At the time point t1 in the first operation phase P1, the voltage level of the second control signal Q(n+1) output by the shift register of the next stage rises, the sixth switch T6 is turned on, and the second voltage signal VGL is provided to the second node a2. At the moment when the voltage level of the second node a2 drops, the capacitor Ca couples the voltage level of the second node a2 to the first node a1, so that the voltage level of the first node a1 also drops instantly, and then the voltage of the first node a1 The level is pulled back according to the voltage level of the light emitting clock signal ECK.

Next, at the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 20 executes the second operation phase P2. At this time, the first switch T1 and the second switch T2 are turned off, and the first node a1 is provided with the first voltage signal VGH through the third switch T3, so that the voltage level rises. The fourth switch T4 is turned on according to the rising voltage level of the first node a1 , and the first voltage signal VGH is provided to the output node out1 . At this time, the light emitting signal EM(n) is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch T3 and the threshold voltage Vth4 of the fourth switch T4, and the capacitor Ca is applied to the first node a1 voltage level.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the sixth switch T6 is turned off, and the first voltage signal VGH is provided to the sixth switch T5 through the fifth switch T5. The second node a2 increases the voltage level of the second node a2. The first node a1 is boosted to a higher voltage level by the voltage level of the second node a2 through the coupling of the capacitor Ca. At this time, the first node a1 with a higher voltage level can keep the fourth switch T4 turned on in a frame interval, so that the first voltage signal VGH is provided to the output node out1 . In one embodiment, the channel width-to-length ratio of the sixth switch T6 is greater than the channel width-to-length ratio of the fifth switch T5. Accordingly, when the voltage level of the second control signal Q(n+1) increases, the sixth switch T6 can pull down the voltage level of the second node a2 more effectively. In other words, through the control of the fifth switch T5, the sixth switch T6 and the capacitor Ca in cooperation with the second control signal Q(n+1), the voltage level of the first node a1 can be increased and the leakage current of the first node a1 can be reduced. The effect of the fourth switch T4 further enables the signal generating circuit 20 to completely drive the pixel circuit in one frame period.

Next, please refer to FIG. 4A and FIG. 4B together. FIG. 5 is a schematic diagram of a signal generation circuit according to another embodiment of the present invention, and FIG. 4B is a voltage of the signal generation circuit according to the embodiment of FIG. 4A timing diagram. As shown in the figure, the signal generating circuit 30 has a first switch M1 , a second switch M2 , a third switch M3 , a fourth switch M4 , a fifth switch M5 , a sixth switch M6 , a seventh switch M7 and a capacitor Cb. In this embodiment, the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6 and the capacitor Cb are substantially the same as the embodiment shown in FIG. 3A, No more details. Different from the embodiment in FIG. 3A , this embodiment further has a seventh switch M7 electrically connected to the second node b2 . The first terminal of the seventh switch M7 is electrically connected to the second node b2, the second terminal of the seventh switch M7 receives the second voltage signal VGL, and the control terminal of the seventh switch M7 receives the first control signal Q(n).

In actual operation, at the time point t1 in the first operation phase P1, the voltage level of the first control signal Q(n) output by the shift register rises, and the first switch M1, the second switch M2 and The seventh switch M7 is turned on, the light-emitting clock signal ECK is provided to the output node out2 and the first node b1, the light-emitting signal EM(n) output from the output node out2 and the voltage signal on the first node b1 drop, and the second voltage signal VGL is provided to the second node b2, and the voltage signal on the second node b2 drops. In FIG. 6, the signal on the first node b1 is represented by Vb1, and the signal on the second node b2 is represented by Vb2. The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 30 .

At the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 30 executes the second operation phase P2. At this time, the first switch M1 and the second switch M2 are turned off, and the first node b1 is provided with the first voltage signal VGH through the third switch M3, so that the voltage level rises. The fourth switch M4 is turned on according to the rising voltage level of the first node b1, and the first voltage signal VGH is provided to the output node out2. The light emitting signal EM(n) output from the output node out2 is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch M3 and the threshold voltage Vth4 of the fourth switch M4, and the capacitor Cb is applied to the first node b1 on the voltage level.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the sixth switch M6 is turned off, and the first voltage signal VGH is provided to the sixth switch M5 through the fifth switch M5. The second node b2 increases the voltage level of the second node b2. The first node b1 is boosted to a higher voltage level by the voltage level of the second node b2 through the coupling of the capacitor Cb. At this time, the first node b1 with a higher voltage level can keep the fourth switch M4 turned on in a frame interval, so that the first voltage signal VGH is provided to the output node out2.

In one embodiment, the channel width-to-length ratio of the sixth switch M6 and the seventh switch M7 is greater than that of the fifth switch M5 . Accordingly, when the voltage levels of the second control signal Q(n+1) and the first control signal Q(n) increase, the sixth switch M6 and the seventh switch M7 can pull down the voltage of the second node b2 more effectively level.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention. As shown in FIG. 5, the signal generating circuit 40 has a first switch X1, a second switch X2, and a third switch X3 , the fourth switch X4, the fifth switch X5, the sixth switch X6, the seventh switch X7 and the capacitor Cd. The circuit diagram of the embodiment in FIG. 5 is substantially the same as the embodiment shown in FIG. 4A . The difference from the embodiment in FIG. 4A is that the control end of the fifth switch X5 is electrically connected to the output node out3. The voltage timing diagram according to the embodiment shown in FIG. 5 is substantially the same as that shown in FIG. 4B , and will not be shown again. The operation of the embodiment shown in FIG. 5 is described below with the voltage timing diagram shown in FIG. 4B. At the time point t1 in the first operation phase P1, the voltage level of the first control signal Q(n) output by the shift register rises, and the first switch X1, the second switch X2 and the seventh switch X7 are turned on. , the light emitting clock signal ECK is provided to the output node out3 and the first node d1, the light emitting signal EM(n) output from the output node out3 and the voltage signal on the first node d1 drop, and the second voltage signal VGL is provided to the second Node d2, the voltage signal on the second node d2 drops. In FIG. 4B , the signal on the first node d1 is represented by Vb1 , and the signal on the second node d2 is represented by Vb2 . The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 40 .

At the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 40 executes the second operation phase P2. At this time, the first switch X1 and the second switch X2 are turned off, and the first node d1 is provided with the first voltage signal VGH through the third switch X3, so that the voltage level rises. The fourth switch X4 is turned on according to the rising voltage level of the first node d1, and the first voltage signal VGH is provided to the output node out3. The light emitting signal EM(n) output from the output node out3 is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch X3 and the threshold voltage Vth4 of the fourth switch X4, and the capacitor Cd is applied to the first node d1 on the voltage level.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the sixth switch X6 is turned off, and the fifth switch X5 outputs the light emitting signal EM(n ) is turned on, and the first voltage signal VGH is provided to the second node d2, so that the voltage level of the second node d2 rises. The first node d1 is boosted to a higher voltage level by the voltage level of the second node d2 through the coupling of the capacitor Cd. At this time, the first node d1 with a higher voltage level can keep the fourth switch X4 turned on in a frame interval, so that the first voltage signal VGH is provided to the output node out3 .

Please refer to another embodiment shown in FIG. 6A. FIG. 6A is a schematic diagram of a signal generating circuit according to another embodiment of the present invention, and FIG. 6B is a voltage sequence of the signal generating circuit shown in the embodiment of FIG. 6A picture. As shown in the figure, the signal generating circuit 50 has a signal generating module 51 , a coupling element Ce, a first control switch V1 and a second control switch V2 . The signal generation module 51 receives the light-emitting clock signal ECK and the first voltage signal VGH, adjusts the voltage level of the first node e1 according to the first control signal Q(n), and generates an output signal according to the voltage level of the first node e1 , such as the luminescent signal EM(n). In one embodiment, the signal generation module 51 is, for example, an existing signal generator in the past. In this embodiment, the signal generation module 51 is based on the first switch U1, the second switch U2, the third switch U3 and the fourth switch U4 The circuit structure of the signal generating module 51 is not limited to the example. The first switch U1, the second switch U2, the third switch U3, and the fourth switch U4 in the signal generation module 51 are the same as the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 of the previous embodiment. They are substantially the same and will not be repeated here.

One end of the coupling element Ce is electrically coupled to the first node e1, and the other end is electrically coupled to the second node e2. The first terminal and the control terminal of the first control switch V1 receive the first voltage signal VGH, and the second terminal of the first control switch V1 is electrically connected to the second node e2. The first terminal of the second control switch V2 is electrically connected to the second node e2, the second terminal of the second control switch V2 receives the second voltage signal VGL, and the control terminal of the second control switch V2 receives the second control signal Q(n+ 1). In order to effectively pull down the voltage level of the second node e2 when the voltage level of the first control signal Q(n) is increased, the second control switch V2 has a channel width-to-length ratio greater than that of the first control switch The channel width-to-length ratio of V1.

With reference to the voltage timing diagram shown in FIG. 6B, in the first operation phase P1, when the voltage level of the first control signal Q(n) output by the shift register rises, the first control signal Q(n) of the signal generation module 51 The switch U1 and the second switch U2 are turned on, the light-emitting clock signal ECK is provided to the output node out4 and the first node e1, and the light-emitting signal EM(n) output from the output node out4 and the voltage signal on the first node e1 drop. In the voltage sequence diagram of FIG. 6B , the signal on the first node e1 is denoted by Ve1 , and the signal on the second node e2 is denoted by Ve2 . The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 50 .

At the time point t1 in the first operation phase P1, the voltage level of the second control signal Q(n+1) output by the shift register of the next stage rises, the second control switch V2 is turned on, and the second voltage The signal VGL is supplied to the second node e2. When the voltage level of the second node e2 drops, the capacitor Ce couples the voltage level of the second node e2 to the first node e1, so that the voltage level of the first node e1 also drops instantly, and then the voltage of the first node e1 The level is pulled back according to the voltage level of the light emitting clock signal ECK.

Next, at the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 50 executes the second operation phase P2. At this moment, the first switch U1 and the second switch U2 are turned off, and the first node e1 is provided with the first voltage signal VGH through the third switch U3, so that the voltage level rises. The fourth switch U4 is turned on according to the rising voltage level of the first node e1, and the first voltage signal VGH is provided to the output node out4. At this time, the light emitting signal EM(n) output from the output node out4 is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch U3 and the threshold voltage Vth4 of the fourth switch U4, and the capacitor Ce is applied to the first A voltage level on node e1.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the second control switch V2 is turned off, and the first voltage signal VGH is provided through the first control switch V1 to the second node e2, so that the voltage level of the second node e2 rises. The first node e1 is boosted to a higher voltage level by the voltage level of the second node e2 through the coupling of the capacitor Ce. At this moment, the voltage level of the first node e1 can make the fourth switch U4 turn on in a frame interval, so that the output node out4 can completely output the light emitting signal EM(n). In one embodiment, the channel width-to-length ratio of the second control switch V2 is greater than the channel width-to-length ratio of the first control switch V1 . Accordingly, when the voltage level of the second control signal Q(n+1) increases, the second control switch V2 can pull down the voltage level of the second node e2 more effectively. In other words, through the control of the first control switch V1, the second control switch V2 and the capacitor Ce in cooperation with the second control signal Q(n+1), the voltage level of the first node e1 can be increased and the leakage of the first node e1 can be reduced. The effect of the current on the fourth switch U4 further enables the signal generating circuit 50 to completely drive the pixel circuit in one frame period.

Other situations to reduce the leakage current of some switches in the signal generator are shown in FIG. 7A. Please refer to FIG. 7A and FIG. 7B together. FIG. 7A is a schematic diagram of a signal generating circuit according to another embodiment of the present invention. FIG. 7B is a voltage timing diagram of the signal generating circuit shown in the embodiment shown in FIG. 7A . As shown in the figure, the signal generating circuit 60 has a signal generating module 61 , a coupling element Cf, a first control switch W1 , a second control switch W2 and a third control switch W3 . The signal generating module 61 receives the light-emitting clock signal ECK and the first voltage signal VGH to adjust the voltage level of the first node f1 according to the first control signal Q(n), and generate an output signal according to the voltage level of the first node f1 , such as the luminescent signal EM(n). In one embodiment, the signal generation module 61 is, for example, an existing signal generator in the past. In this embodiment, the signal generation module 61 is based on the first switch U1, the second switch U2, the third switch U3 and the fourth switch U4 The circuit structure of the signal generation module 61 is not limited to the example. The first switch U1, the second switch U2, the third switch U3, and the fourth switch U4 in the signal generation module 61 are the same as the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 of the previous embodiment. They are substantially the same and will not be repeated here.

One end of the coupling element Cf is electrically coupled to the first node f1, and the other end is electrically coupled to the second node f2. The first terminal and the control terminal of the first control switch W1 receive the first voltage signal VGH, and the second terminal of the first control switch W1 is electrically connected to the second node f2. The first terminal of the second control switch W2 is electrically connected to the second node f2, the second terminal of the second control switch W2 receives the second voltage signal VGL, and the control terminal of the second control switch W2 receives the second control signal Q(n+ 1). The first terminal of the third control switch W3 is electrically connected to the second node f2, the second terminal of the third control switch W3 receives the second voltage signal VGL, and the control terminal of the third control switch W3 receives the first control signal Q(n) . In order to effectively pull down the voltage level of the second node f2 when the voltage level of the first control signal Q(n) is increased, the second control switch W2 has a channel width-to-length ratio greater than that of the first control switch The channel width-to-length ratio of W1.

In actual operation, at the time point t1 in the first operation phase P1, the voltage level of the first control signal Q(n) output by the shift register rises, and the first switch U1, the second switch U2 and The third control switch W3 is turned on, and the light-emitting clock signal ECK is provided to the output node out5 and the first node f1, the light-emitting signal EM(n) output from the output node out5 and the voltage signal on the first node f1 drop, and the second voltage The signal VGL is provided to the second node f2, and the voltage signal on the second node f2 drops. In FIG. 7B, the signal on the first node f1 is represented by Vf1, and the signal on the second node f2 is represented by Vf2. The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 60 .

At the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 60 executes the second operation phase P2. At this time, the first switch U1 and the second switch U2 are turned off, and the first node f1 is provided with the first voltage signal VGH through the third switch U3, so that the voltage level rises. The fourth switch U4 is turned on according to the rising voltage level of the first node f1, and the first voltage signal VGH is provided to the output node out5. The light emitting signal EM(n) output from the output node out5 is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch U3 and the threshold voltage Vth4 of the fourth switch U4, and the capacitor Cf is applied to the first node f1 on the voltage level.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the second control switch W2 is turned off, and the first voltage signal VGH is provided through the first control switch W1 to the second node f2 to increase the voltage level of the second node f2. The first node f1 is boosted to a higher voltage level by the voltage level of the second node f2 through the coupling of the capacitor Cf. At this time, the first node f1 with a higher voltage level can keep the fourth switch U4 turned on in a frame interval, so that the first voltage signal VGH is provided to the output node out5 .

In one embodiment, the channel width-to-length ratio of the second control switch W2 and the third control switch W3 is greater than the channel width-to-length ratio of the first control switch W1 . Accordingly, when the voltage levels of the second control signal Q(n+1) and the first control signal Q(n) increase, the second control switch W2 and the third control switch W3 can more effectively pull down the second node f2 voltage level.

Please refer to FIG. 8 next. FIG. 8 is a schematic diagram of a signal generating circuit according to yet another embodiment of the present invention. As shown in FIG. 8 , the signal generating circuit 70 has a signal generating module 71, a coupling element Cg, a first control The switch Y1, the second control switch Y2 and the third control switch Y3, wherein the signal generation module 71, the coupling element Cg, the second control switch Y2 and the third control switch Y3 are the same as the signal generation module 61 and the coupling element Cf of the previous embodiment , the second control switch W2 and the third control switch W3 are substantially the same, and will not be repeated here.

Different from the previous embodiment, the control end of the first control switch Y1 is electrically connected to the output node out6. The voltage timing diagram of the embodiment in FIG. 8 is substantially the same as that in FIG. 7B , and will not be shown repeatedly. The operation of the embodiment of FIG. 8 is described below with the voltage timing diagram shown in FIG. 7B. At the time point t1 in the first operation phase P1, the voltage level of the first control signal Q(n) output by the shift register rises, and the first switch U1, the second switch U2 and the third control switch Y3 conduct On, the light emitting clock signal ECK is provided to the output node out6 and the first node g1, the light emitting signal EM(n) output from the output node out6 and the voltage signal on the first node g1 drop, and the second voltage signal VGL is provided to the first node g1 The second node g2, the voltage signal on the second node g2 drops. In FIG. 7B, the signal on the first node g1 is represented by Vf1, and the signal on the second node g2 is represented by Vf2. The rising period of the voltage of the first control signal Q(n) is the first operation phase P1 of the signal generating circuit 70 .

At the time point t2, the voltage level of the first control signal Q(n) drops, and the signal generating circuit 70 executes the second operation phase P2. At this time, the first switch U1 and the second switch U2 are turned off, and the first node g1 is provided with the first voltage signal VGH through the third switch U3, so that the voltage level rises. The fourth switch U4 is turned on according to the rising voltage level of the first node g1 , and the first voltage signal VGH is provided to the output node out6 . The light emitting signal EM(n) output from the output node out6 is raised to the voltage level of the first voltage signal VGH minus the threshold voltage Vth3 of the third switch U3 and the threshold voltage Vth4 of the fourth switch U4, and the capacitor Cg is applied to the first node g1 on the voltage level.

At the time point t3 in the second operation phase P2, the voltage level of the second control signal Q(n+1) drops, the second control switch Y2 is turned off, and the first control switch Y1 outputs the light emitting signal EM according to the output node out6 (n) is turned on, and the first voltage signal VGH is provided to the second node g2, so that the voltage level of the second node g2 rises. The first node g1 is boosted to a higher voltage level by the voltage level of the second node g2 through the coupling of the capacitor Cg. At this time, the voltage level of the first node g1 increases, so that the fourth switch U4 is completely turned on in a frame interval, and the output node out6 completely outputs the light emitting signal EM(n).

In order to illustrate the signal generating method applicable to the signal generating circuit more clearly, please refer to FIG. 3A and FIG. 9 together. FIG. 9 is a flow chart showing the steps of the signal generating method according to an embodiment of the present invention. As shown in the figure, in step S601, the signal generation circuit 20 provides the light-emitting clock signal ECK to the first node a1 and the output node out according to the first control signal Q(n), and the output node out is used to output the driving signal, as shown in Luminescence signal EM(n). In step S603, the signal generating circuit 20 provides the first voltage signal VGH to the first node a1 according to the first control signal Q(n). In step S605, the first voltage signal VGH is provided to the output node out according to the voltage level of the first node a1. In step S607, the first voltage signal VGH is provided to the second node a2 according to the second control signal Q(n+1). In step S609, the voltage level of the first node a1 is coupled with the voltage level of the second node a2.

In one embodiment, when the first control signal Q(n) is at a high voltage level, the signal generating circuit 20 provides the light emitting clock signal ECK to the first node a1 and the output node out. When the first control signal Q(n) is at a low voltage level, the first voltage signal VGH is provided to the first node a1. In another embodiment, the signal generation method further includes the step of providing the second voltage signal VGL to the second node a2 according to the second control signal Q(n+1), and wherein when the second control signal Q(n+1) When the voltage level is high, the second voltage signal VGL is provided to the second node a2, and when the second control signal Q(n+1) is at the low voltage level, the first voltage signal VGH is provided to the second node a2. The signal generating method described in this embodiment has actually been disclosed in the above-mentioned embodiments, and this embodiment will not be repeated here.

Based on the above, the embodiments of the present invention provide a signal generating circuit and method thereof. By coupling the voltage level of the second node to the first node, after the voltage level of the first control signal drops, the first The voltage level of the node can be further increased, thereby reducing the leakage current of the first node and affecting the output signal of the signal generating circuit. In other words, according to the voltage level of the first node, the signal generating circuit can output a light-emitting signal to the pixel circuit within one frame period, so as to solve the problem that some switches in the existing signal generating circuit will leak current and cause the pixel circuit to fail to operate in one frame. The problem of driving pixels completely in the frame cycle.

Although the present invention is disclosed above with the foregoing embodiments, they are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, all changes and modifications made belong to the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims.

Claims (15)

1. a signal generating circuit, it is characterised in that including:

One first switch, one first end of this first switch is electrically connected with an output node, and one second end of this first switch is used To receive a luminous clock signal, a control end of this first switch is in order to receive one first control signal；

One second switch, one first end of this second switch is electrically connected with a primary nodal point, and one second end of this second switch is used To receive this luminescence clock signal, a control end of this second switch is in order to receive this first control signal；

One the 3rd switch, one first end of the 3rd switch and a control end are in order to receive one first voltage signal, and the 3rd opens One second end closed is electrically connected with this primary nodal point；

One the 4th switch, the 4th switch one first end in order to receive this first voltage signal, the 4th switch one second End is electrically connected with this output node, and a control end of the 4th switch is electrically connected with this primary nodal point；

One the 5th switch, the 5th switch one first end in order to receive this first voltage signal, the 5th switch one second End is electrically connected with a secondary nodal point；

One the 6th switch, one first end of the 6th switch is electrically connected with this secondary nodal point, and one second end of the 6th switch is used To receive one second voltage signal, a control end of the 6th switch is in order to receive one second control signal；And

One electric capacity, one end is electrically connected with this primary nodal point, and the other end is electrically connected with this secondary nodal point.

2. signal generating circuit as claimed in claim 1, it is characterised in that a control end of the 5th switch is in order to receive this First voltage signal.

3. signal generating circuit as claimed in claim 1, it is characterised in that a control end of the 5th switch is electrically connected with should Output node.

4. signal generating circuit as claimed in claim 1, it is characterised in that the passage breadth length ratio of the 6th switch more than this The passage breadth length ratio of five switches.

5. signal generating circuit as claimed in claim 1, it is characterised in that also comprise one the 7th switch, the 7th switch One first end is electrically connected with this secondary nodal point, one second end of the 7th switch in order to receive this second voltage signal, the 7th One control end of switch is in order to receive this first control signal.

6. signal generating circuit as claimed in claim 5, it is characterised in that the passage breadth length ratio of the 7th switch more than this The passage breadth length ratio of five switches.

7. a signal generating circuit, it is characterised in that including:

One signal generator module, in order to receive luminous clock signal and one first voltage signal, in order to control according to one first Signal adjusts the voltage level of a primary nodal point, and produces an output signal according to the voltage level of this primary nodal point；

One coupling element, its this primary nodal point of one end electric property coupling, its other end electric property coupling one secondary nodal point；

One first controls switch, in order to receive this first voltage signal, in order to promote the voltage level of this secondary nodal point；And

One second controls switch, in order to receive one second voltage signal, in order to according to one second control signal this second section drop-down The voltage level of point.

8. signal generating circuit as claimed in claim 7, it is characterised in that this first grid controlling to switch is in order to receive this Output signal or in order to receive this first voltage signal.

9. signal generating circuit as claimed in claim 7, it is characterised in that also comprise one the 3rd control switch, the 3rd control System switch is in order to receive this second voltage signal, in order to the voltage level according to this first control signal this secondary nodal point drop-down.

10. signal generating circuit as claimed in claim 7, it is characterised in that the 3rd passage breadth length ratio controlling to switch is big Passage breadth length ratio in this first control switch.

11. 1 kinds of signal generating methods a, it is adaptable to signal generating circuit, this signal generating circuit is in order to provide a driving letter Number, this signal generating method includes:

According to one first control signal, it is provided that a luminous clock signal is to a primary nodal point and an output node, this output node In order to export this driving signal；

According to this first control signal, it is provided that one first voltage signal is to this primary nodal point；

Voltage level according to this primary nodal point, it is provided that this first voltage signal is to this output node；

According to one second control signal, it is provided that this first voltage signal is to a secondary nodal point；And

With the voltage level of this secondary nodal point, couple the voltage level of this primary nodal point.

12. signal generating methods as claimed in claim 11, it is characterised in that when this first control signal is high voltage level Time, it is provided that this luminescence clock signal to this primary nodal point and this output node, when this first control signal is low-voltage level, There is provided this first voltage signal to this primary nodal point.

13. signal generating methods as claimed in claim 11, it is characterised in that also include providing according to this second control signal One second voltage signal is to this secondary nodal point.

14. signal generating methods as claimed in claim 13, it is characterised in that when this second control signal is high voltage level Time, it is provided that this second voltage signal to this secondary nodal point, when this second control signal is low-voltage level, it is provided that this first electricity Pressure signal is to this secondary nodal point.

15. signal generating methods as claimed in claim 13, it is characterised in that according to this first control signal, it is provided that should Luminous clock signal is in the step of this primary nodal point and this output node, including according to this first control signal, it is provided that this is the years old Two voltage signals are to this secondary nodal point.