CN106024800B - A calibratable resistance device and integrated circuit - Google Patents
A calibratable resistance device and integrated circuit Download PDFInfo
- Publication number
- CN106024800B CN106024800B CN201610509752.XA CN201610509752A CN106024800B CN 106024800 B CN106024800 B CN 106024800B CN 201610509752 A CN201610509752 A CN 201610509752A CN 106024800 B CN106024800 B CN 106024800B
- Authority
- CN
- China
- Prior art keywords
- resistance
- port
- configuration
- resource block
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a calibratable resistor device and an integrated circuit, comprising: the system comprises a reference resistor, a calibration resistor array, a routing resource block, a first resistor port, a second resistor port and a configuration port; the first extreme of reference resistance is connected with the first extreme of calibration resistance array, and the second extreme of calibration resistance array is connected with first resistance port, and the second extreme of reference resistance is connected with the second resistance port, and the wiring input of calibration resistance array is connected with the wiring output of routing resource block, and the configuration input of routing resource block is connected with the configuration port. The invention solves the technical problem that the prior adjustable resistor realizes longer resistance value adjusting period, and effectively shortens the design period.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of adjustable resistance devices and integrated circuit.
Background technique
As IC design technology reaches its maturity, the shortening of product development cycle is in integrated circuit design process
Flow success rate is improved, the preset parameter adjustable circuit structure demand in circuit inside is increasing, passes through redundancy MOS device school
The breadth length ratio of quasi- circuit reserves the key parameters such as voltage, the electric current of resistance, capacitance structure calibration circuit.
Currently, mainly having in the resistance calibration program that IC interior uses: being reserved in circuit design process superfluous
Remaining electric resistance structure, is attached redundancy resistance by FIB and the method for rebuilding lead or key node electricity is modified in short circuit, realization
The function of resistance value.But this scheme needs flow again to verify after modifying key node resistance value, therefore realizes resistance value tune
Complete cycle is longer.
Summary of the invention
The embodiment of the present invention solves existing adjustable resistance by providing a kind of adjustable resistance device and integrated circuit
Period longer technical problem is adjusted in the presence of realization resistance value.
In a first aspect, adjustable resistance device provided in an embodiment of the present invention, comprising: reference resistance, calibrating resistance array,
Route resource block, first resistor port, second resistance port configure port；Described in the extreme connection of the first of the reference resistance
The first of calibrating resistance array is extreme, and the second of the calibrating resistance array extremely connects the pin of the first resistor port,
The second of the reference resistance extremely connects the pin of the second resistance port, the wiring input terminal of the calibrating resistance array
The cloth line output terminal of the route resource block is connected, the configuration input terminal of the route resource block connects drawing for the configuration port
Foot.
Preferably, the calibrating resistance array includes multiple unit resistance connections.
Preferably, the reference resistance is the compatible resistance type of CMOS technology.
Preferably, the unit resistance is the compatible resistance type of CMOS technology.
Preferably, the configuration port includes N number of configuration end, and N is positive integer.
Preferably, the route resource block includes: multi-path choice module and latch structure；The input terminal of the latch structure
It is correspondingly connected with the pin of the configuration port, the output end of the latch structure connects the input terminal of the multi-path choice module,
The output end of the multi-path choice module connects the cloth line output terminal.
Second aspect, the embodiment of the invention provides a kind of integrated circuits, including adjustable resistance described in first aspect
Device.
The one or more technical solutions provided in the embodiment of the present invention, have at least the following technical effects or advantages:
Since reference resistance is connect with calibrating resistance array, the wiring input terminal link road of calibrating resistance array is by resource block
Cloth line output terminal, route resource block configuration input terminal connection configuration port.So as to be assigned to road by configuring port
By resource block, the hard wired logic for calibrating resistance array corresponding with assignment is compiled out by route resource block, to change calibration
The connection relationship of unit resistance in electric resistance array, to increase and decrease the resistance value of calibrating resistance array, thus realize it is provided by the present invention can
Calibrating resistance device carries out resistance value calibration centered on the resistance value of reference resistance, without carrying out the resistance in existing scheme
Connection or resistive short do not need to verify the whole flow again of circuit, so being able to solve so as to avoid lead is rebuild yet
Existing adjustable resistance realizes that resistance value adjusts period longer technical problem, effectively shortens the resistance value adjustment period.
Further, adjustable resistance device provided in this embodiment includes N number of configuration end, and N number of configuration end corresponds to assignment two
System logical data then can assign 2 by configuring portnKind value gives route resource block, compiles out 2 by route resource blocknKind wiring
Logic realizes the 2 of calibrating resistance arraynA resistance value to calibrate reference resistance, therefore realizes a wide range of resistance to configure end on a small quantity
Value calibration to only need that a small amount of configuration end is arranged in actual design, therefore can save encapsulation PAD resource, reduce chip
Area occupied.
Further, the present invention be applied to extensive simulation, in Design of Digital Circuit when only need to change configuration by programming
The assignment of port is to realize that resistance value is calibrated, more conducively circuit exploitation design.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the circuit diagram of adjustable resistance device in the embodiment of the present invention；
Fig. 2 is the refinement circuit diagram of alignment of embodiment of the present invention electric resistance array；
Fig. 3 is the refinement circuit diagram that resource block is routed in the embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Refering to what is shown in Fig. 1, adjustable resistance device provided in an embodiment of the present invention includes: reference resistance 100, calibrating resistance
Array 101, route resource block 102, first resistor port 103, second resistance port 104 configure port 105.
The first of the extreme connection calibrating resistance array 101 of the first of reference resistance 100 is extreme, calibrating resistance array 101
The pin of second extreme connection first resistor port 103, the extreme connection second resistance port 104 of the second of reference resistance 100
Pin, calibrating resistance array 101 wiring input terminal link road by resource block 102 cloth line output terminal, route resource block 102
The pin of input terminal connection configuration port 105.To pass through above-mentioned adjustable resistance device: configuration port 105 is assigned to routing
Resource block 102, the value for being specifically assigned to configuration port 105 is different, and route resource block 102 controls calibrating resistance array 101 and is in
The existing different resistance value for calibration, thus to the resistance value of adjustable resistance device centered on the resistance value of reference resistance 100
It is calibrated.
In a specific example, refering to what is shown in Fig. 2, calibrating resistance array 101 include multiple unit resistances 1011 connect and
At the two poles of the earth of each unit resistance 1011 connect the cloth line output terminal of a route resource block 102, do not limit unit resistance herein
1011 number.As shown in Fig. 2 citing, multiple unit resistances 1011 are connected into calibrating resistance array 101, each unit resistance
1011 the two poles of the earth connect the cloth line output terminal of a route resource block 102, each connection of route resource block 102 configuration port 105
A configuration end.Specifically, each unit resistance 1011 is the compatible resistance type of CMOS technology, in the specific implementation process,
It can be the compatible resistance type of the CMOS technologies such as well resistance, polysilicon resistance, active area resistance.It therefore will not be because of calibrating resistance battle array
The addition of column 101 generates additional plate-making cost.
Specifically, configuration port 105 includes N number of configuration end, N is positive integer, configures the number and route resource block 102 at end
Number it is identical, all in accordance with actual demand be arranged number.High level " 1 " is assigned a value of to each configuration end in configuration port 105
Or low level " 0 ", so that configuring port 105 is assigned a value of binary logic data.Specifically, being assigned a value of to configuration port 105
When 1010 ... 10 (n total, identical as the configuration configuration number at end of port 105), there is no unit electric in calibrating resistance array 101
Resistance 1011 is linked into adjustable resistance device, then the resistance value of adjustable resistance device is equal to the resistance value of reference resistance 100.Configuration
10 to 0000 ... 00 every reduction 1 that 105 assignment of port is by 1010 ..., the resistance value of the adjustable resistance device reduce by a unit resistance
1011 resistance value.Configure 105 assignment of port by 1010 ... 10 to 1111 ... 11 it is every increase by 1, it is provided in an embodiment of the present invention can school
The resistance value of quasi- resistance device increases the resistance value of a unit resistance 1011.For example, 3 configuration ends can be set in configuration port 105,
The assignment for then configuring port 105 can be 000 to 111, and 8 kinds of different resistance values can be presented in corresponding adjustable resistance device,
Such as: 4 configuration ends can be set in configuration port 105, then the assignment for configuring port 105 can be 0000~1111, corresponding
16 kinds of different resistance values can be presented in adjustable resistance device, and so on, configuration port 105 can be set according to calibration range
Configuration end number.
Specifically, selecting the resistance value of the unit resistance 1011 in calibrating resistance array 101 according to demand.For example, it needs
To be carried out centered on the resistance value of reference resistance 100 0.1 Ω be calibration intervals calibrated, then calibrating resistance array 101 by
Multiple resistance values are that the unit resistance 1011 of 0.1 Ω is formed by connecting.For example, then may be used so that the resistance value of reference resistance 100 is 40 Ω as an example
The resistance value of calibrating resistance device can be 40 Ω, 40.1 Ω, 40.2 Ω, 40.3 Ω ..., 39.99 Ω, 39.98 Ω, 39.97
Ω….For another example, needing to carry out 1 Ω centered on the resistance value of reference resistance 100 is that interval is calibrated, then unit resistance
1011 resistance value is 1 Ω.By taking the resistance value of reference resistance 100 is 50 Ω as an example, then the resistance value of adjustable resistance device is 50 Ω, 51
Ω, 52 Ω, 53 Ω, 54 Ω ..., 49 Ω, 48 Ω, 47 Ω ....
Through the above scheme, the configuration end of configuration port 105 is N number of, then configures port 105 to route resource block 102
For N binary logic data, configures the binary logic data that port 105 exports and completed by the compiling of route resource block 102
Hard wired logic afterwards assigns calibrating resistance array 101, to control the unit resistance for accessing circuit in calibrating resistance array 101
1011, so that different resistance values is presented in calibrating resistance array 101, with resistance value needed for realizing user.By configuring port 105
Configure end be it is N number of, then can configure 2nKind binary logic data, the hard wired logic after the completion of compiling just have 2nKind, to reduce
The configuration end quantity of the configuration port 105 of adjustable resistance device, and then reduce and occupy encapsulation PAD resource and occupied chip
Area.
Specifically, refering to what is shown in Fig. 3, each route resource block 102 includes: multi-path choice module 1022 and latch structure
1021.The input terminal of latch structure 1021 is correspondingly connected with the pin at a configuration end of configuration port 105, latch structure 1021
The input terminal of output end connection multi-path choice module 1022, the output end connecting wiring output end of multi-path choice module 1022, from
And the wiring input terminal link road of calibrating resistance array 101 is realized by the cloth line output terminal of resource block 102.
Through the above scheme, binary logic data are arranged to latch structure 1021 in configuration port 105, match after being arranged successfully
It sets port 105 and nor affects on resistance without outer signal, but pass through the binary logic data that latch structure 1021 stores
Multi-path choice module 1022 is controlled, persistently controls whether single unit resistance 1011 accesses in the circuit of adjustable resistance device.
Specifically, reference resistance 100 is the compatible resistance type of CMOS technology, be specifically as follows well resistance, polysilicon resistance,
The CMOS technologies such as active area resistance are compatible with resistance type.Therefore will not be generated because of the addition of reference resistance 100 additional plate-making at
This.
The one or more embodiments provided by the embodiments of the present invention, at least realize following technical effect:
Since reference resistance is connect with calibrating resistance array, the wiring input terminal link road of calibrating resistance array is by resource block
Cloth line output terminal, route resource block configuration input terminal connection configuration port.So as to be assigned to road by configuring port
By resource block, the hard wired logic for calibrating resistance array corresponding with assignment is compiled out by route resource block, to change calibration
The connection relationship of unit resistance in electric resistance array, to increase and decrease the resistance value of calibrating resistance array, thus realize it is provided by the present invention can
Calibrating resistance device carries out resistance value calibration centered on the resistance value of reference resistance, without carrying out the resistance in existing scheme
Connection or resistive short do not need to verify the whole flow again of circuit, so being able to solve so as to avoid lead is rebuild yet
Existing adjustable resistance realizes that resistance value adjusts period longer technical problem, effectively shortens the design cycle.
Further, adjustable resistance device provided in this embodiment includes N number of configuration end, and N number of configuration end corresponds to assignment two
System logical data then can assign 2 by configuring portnKind value gives route resource block, compiles out 2 by route resource blocknKind wiring
Logic realizes the 2 of calibrating resistance arraynA resistance value to calibrate reference resistance, therefore realizes a wide range of resistance to configure end on a small quantity
Value calibration to only need that a small amount of configuration end is arranged in actual design, therefore can save encapsulation PAD resource, reduce chip
Area occupied.
Further, the present invention be applied to extensive simulation, in Design of Digital Circuit when only need to change configuration by programming
The assignment of port is to realize that resistance value is calibrated, more conducively circuit exploitation design.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610509752.XA CN106024800B (en) | 2016-06-30 | 2016-06-30 | A calibratable resistance device and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610509752.XA CN106024800B (en) | 2016-06-30 | 2016-06-30 | A calibratable resistance device and integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106024800A CN106024800A (en) | 2016-10-12 |
| CN106024800B true CN106024800B (en) | 2019-01-29 |
Family
ID=57106095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610509752.XA Active CN106024800B (en) | 2016-06-30 | 2016-06-30 | A calibratable resistance device and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106024800B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080018393A1 (en) * | 2006-07-07 | 2008-01-24 | Yamaha Corporation | Offset voltage correction circuit and class D amplifier |
| US20080219068A1 (en) * | 2007-03-08 | 2008-09-11 | Hynix Semiconductor Inc. | Zq calibration controller and method for zq calibration |
| CN102164010A (en) * | 2010-02-03 | 2011-08-24 | 特里奎恩特半导体公司 | Automatic calibration circuit |
| CN203872158U (en) * | 2014-04-28 | 2014-10-08 | 比亚迪股份有限公司 | Compensation circuit reducing resistance temperature characteristics |
-
2016
- 2016-06-30 CN CN201610509752.XA patent/CN106024800B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080018393A1 (en) * | 2006-07-07 | 2008-01-24 | Yamaha Corporation | Offset voltage correction circuit and class D amplifier |
| US20080219068A1 (en) * | 2007-03-08 | 2008-09-11 | Hynix Semiconductor Inc. | Zq calibration controller and method for zq calibration |
| CN102164010A (en) * | 2010-02-03 | 2011-08-24 | 特里奎恩特半导体公司 | Automatic calibration circuit |
| CN203872158U (en) * | 2014-04-28 | 2014-10-08 | 比亚迪股份有限公司 | Compensation circuit reducing resistance temperature characteristics |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106024800A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208589437U (en) | Semiconductor device | |
| US8164937B2 (en) | Digital potentiometer using third dimensional memory | |
| TWI472157B (en) | Die apparatus having configurable input/output and control method thereof | |
| KR20100029236A (en) | Dynamic impedance control for input/output buffers | |
| CN113657065B (en) | Clock circuit, memory and method for manufacturing semiconductor structure | |
| JP2008512065A (en) | Low voltage programmable eFUSE with difference sensing technology | |
| JP2005348413A (en) | Switching method for mask programmable logic device | |
| CN106024800B (en) | A calibratable resistance device and integrated circuit | |
| JP6856032B2 (en) | How Reconfigurable Circuits, Reconfigurable Circuit Systems, and Reconfigurable Circuits Operate | |
| CN106165095A (en) | Semiconductor module with two auxiliary emitter conductor paths | |
| CN103891146A (en) | Semiconductor circuits including electrical pins with multiple signal configurations or potential configurations | |
| CN103081034B (en) | Digital potentiometer with independent control over both resistive arms | |
| KR20110131368A (en) | Semiconductor devices | |
| CN113728291A (en) | Voltage driver with supply current stabilization | |
| US12159687B2 (en) | Clock circuit, memory and method for manufacturing semiconductor structure | |
| KR20210145999A (en) | Capacitor of semiconductor device and distributed model circuit thereof | |
| CN217085092U (en) | Resistance unit and adjustable resistance using the same | |
| US9542305B2 (en) | Impedance matching for high speed signaling in memory system | |
| JP2012508492A (en) | Circuit configuration for amplifying digital signal and transceiver circuit for bus system | |
| US11545480B2 (en) | Integrated circuit with single level routing | |
| CN113098450A (en) | Reconfigurable electromagnetic super-surface biasing method | |
| CN119210431A (en) | Chip, single-gate logic chip and manufacturing method | |
| US20090166683A1 (en) | Flexible layout for integrated mask-programmable logic devices and manufacturing process thereof | |
| CN101025637A (en) | Current mode trimming device | |
| CN111508959A (en) | Semiconductor device having equivalent series resistance element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201216 Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220506 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |