CN105977153B - Ultra-shallow junctions method for annealing - Google Patents
Ultra-shallow junctions method for annealing Download PDFInfo
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- CN105977153B CN105977153B CN201610327931.1A CN201610327931A CN105977153B CN 105977153 B CN105977153 B CN 105977153B CN 201610327931 A CN201610327931 A CN 201610327931A CN 105977153 B CN105977153 B CN 105977153B
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 238000000137 annealing Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 229910003481 amorphous carbon Inorganic materials 0.000 claims abstract description 51
- 239000011248 coating agent Substances 0.000 claims abstract description 31
- 238000000576 coating method Methods 0.000 claims abstract description 31
- 238000004151 rapid thermal annealing Methods 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 abstract description 7
- 239000002194 amorphous carbon material Substances 0.000 abstract description 4
- 239000006185 dispersion Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010436 fluorite Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of ultra-shallow junctions method for annealing, comprising: provides semiconductor substrate, the front of the semiconductor substrate has multiple device architectures, so that the front of the semiconductor substrate is uneven；An amorphous carbon layer and a coating are formed in the front of the semiconductor substrate, the multiple device architecture is completely covered in the amorphous carbon layer, and the coating covers the amorphous carbon layer；Front rapid thermal annealing or back side rapid thermal annealing are carried out to the semiconductor substrate.In the present invention, due to the higher heat absorption coefficients of amorphous carbon layer, and simultaneously as the radiator of semiconductor substrate, thus on a semiconductor substrate the more uniform dispersion of the thermal energy of heat source.So that the device architecture in semiconductor substrate is uniformly heated, annealing temperature is more uniform, to improve the performance of device architecture in semiconductor substrate.In addition, the coating formed on amorphous carbon layer can prevent other semiconductor substrates in amorphous carbon material pollution cavity and cavity.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, in particular to a kind of ultra-shallow junctions method for annealing.
Background technique
With the continuous development of semiconductor processing technology, rapid thermal annealing (Rapid Thermal Annealing, RTA)
Technique is gradually instead of traditional high temperature furnace annealing process.RTA is a kind of heat treatment process of short time high temperature.Usually chip is put
On quartzy frame in process cavity, and chip is heated with high-intensitive radiation of light source.Due to its have be rapidly heated with it is of short duration
The characteristics of duration, therefore can be obtained between the reparation of lattice defect, active ions and minimum ion diffusion three
Optimization, this but also its using more and more common.At the same time, the control of annealing temperature uniformity is also mentioned in RTA technique
Increasingly higher demands are gone out.
Ic manufacturing technology is all the production that multiple chips of repeated arrangement are completed at the same time in a chip.For
The product of multi-chip has different semiconductor structures, the heat budget of chip since different chips are based on respective application background
Just it is different.For example, the distribution density of active area and grid all very littles in radio circuit chip, and have in SRAM circuit chip
Source region or grid have biggish distribution density, on the other hand, can exist in same chip with different active areas or
The region of grid distribution density.This species diversity of the distribution density of the semiconductor structures such as active area or grid, carries out to chip
When rapid thermal anneal process, the difference of chip local temperature will lead to, to influence process uniformity.The temperature of RTA technique is not
Uniform phenomenon will have a direct impact on the electric property of semiconductor devices in integrated circuit, lead to the threshold value electricity of device in regional area
The parameters such as pressure, saturation current cannot reach target value.Therefore, the uniformity for improving RTA technique is all to study in the industry all the time
Hot technology.
Summary of the invention
The object of the present invention is to provide a kind of ultra-shallow junctions method for annealing, solve rapid thermal anneal process in the prior art
The non-uniform problem of annealing temperature.
In order to solve the above technical problems, the present invention provides a kind of ultra-shallow junctions method for annealing, comprising:
Semiconductor substrate is provided, the front of the semiconductor substrate has multiple device architectures, so that the semiconductor serves as a contrast
The front at bottom is uneven；
An amorphous carbon layer is formed in the front of the semiconductor substrate and institute is completely covered in a coating, the amorphous carbon layer
Multiple device architectures are stated, the coating covers the amorphous carbon layer；
Front rapid thermal annealing or back side rapid thermal annealing are carried out to the semiconductor substrate.
Optionally, the device architecture is MOS transistor, resistance or capacitor, and the device architecture is in the semiconductor
The front of substrate is unevenly distributed.
Optionally, the amorphous carbon layer is formed using chemical vapor deposition process, the amorphous carbon layer is formed using ethane,
And the temperature for carrying out chemical vapor deposition process is 200 DEG C~400 DEG C.
Optionally, the amorphous carbon layer with a thickness of 300nm~600nm.
Optionally, the coating is silicon oxide layer or polysilicon layer.
Optionally, the coating with a thickness of 50nm~100nm.
Optionally, further includes: remove the amorphous carbon layer and the coating.
Optionally, using plasma technique removes the amorphous carbon layer.
Optionally, the amorphous carbon layer is removed using oxygen and carbon tetrafluoride plasma process.
Optionally, the semiconductor substrate is cleaned using the mixed solution of sulfuric acid and hydrogen peroxide.
Optionally, carrying out temperature used by front rapid thermal annealing or negative rapid thermal anneal process is 300 DEG C~500
℃。
In ultra-shallow junctions annealing process of the invention, an amorphous carbon layer and a coating are formed in the front of semiconductor substrate,
Later, front rapid thermal annealing or back side rapid thermal annealing are carried out to semiconductor substrate.In the present invention, since amorphous carbon layer is higher
Heat absorption coefficients, and simultaneously as the radiator of semiconductor substrate, thus the thermal energy of heat source it is more uniform be dispersed in half
On conductor substrate.So that the device architecture in semiconductor substrate is uniformly heated, annealing temperature is more uniform, to improve half
The performance of device architecture on conductor substrate.In addition, the coating formed on amorphous carbon layer can prevent amorphous carbon material from polluting
Other semiconductor substrates in cavity and cavity.
Detailed description of the invention
Fig. 1 is the method flow diagram of the ultra-shallow junctions annealing in one embodiment of the invention；
Fig. 2 is the structural schematic diagram that amorphous carbon layer is formed in one embodiment of the invention；
Fig. 3 is the structural schematic diagram that coating is formed in one embodiment of the invention；
Fig. 4 is the schematic diagram of front thermal anneal process in one embodiment of the invention；
Fig. 5 is the schematic diagram of back side thermal anneal process in one embodiment of the invention.
Specific embodiment
Ultra-shallow junctions method for annealing of the invention is described in more detail below in conjunction with schematic diagram, which show this
The preferred embodiment of invention, it should be appreciated that those skilled in the art can modify invention described herein, and still realize this
The advantageous effects of invention.Therefore, following description should be understood as the widely known of those skilled in the art, and not make
For limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As described in the background art, inventor has found that it is different more due to being formed on the surface of semiconductor substrate
A device architecture, and device architecture is unevenly distributed, and the material of different components structure is not also identical, so that semiconductor
The thermal absorptivity of the different zones of substrate is different, leads to the non-uniform temperature in rapid thermal anneal process, so that semiconductor substrate
Different zones can not thermally equivalent, and then influence annealing after device performance.To solve the above-mentioned problems, inventor passes through
Research, proposes ultra-shallow junctions method for annealing of the invention, successively forms an amorphous carbon layer and one in the front of semiconductor substrate and covers
Cap rock can be the warm of heat source due to the higher heat absorption coefficients of amorphous carbon layer, and simultaneously as the radiator of semiconductor substrate
Dispersion that can be more uniform is on a semiconductor substrate.So that the device architecture in semiconductor substrate is uniformly heated, so that moving back
Temperature is uniform in fire process, to improve the performance of device architecture in semiconductor substrate.
Ultra-shallow junctions method for annealing of the invention is described in detail below in conjunction with FIG. 1 to FIG. 5.Fig. 1 is to surpass in the present invention
The method flow diagram of shallow junction annealing, specifically comprises the following steps:
Firstly, step S1 is executed, refering to what is shown in Fig. 2, providing semiconductor substrate 10, the positive mask of the semiconductor substrate 10
There are multiple device architectures 11, so that the front of the semiconductor substrate 10 is uneven.In the present embodiment, the device architecture
11 be MOS transistor, resistance or capacitor, certainly it will be appreciated by persons skilled in the art that the device architecture in the present invention simultaneously
The structures such as MOS transistor, resistance or capacitor are not limited to, such as can also be amplifier, D/A converter, simulation process electricity
Road and/or digital processing circuit, interface circuit etc., the method for forming these device architectures can use traditional CMOS technology.
Also, according to the design requirement of integrated circuit, the device architecture 11 is unevenly distributed in the positive of semiconductor substrate 10
It is even.It should be noted that the difference of the sparse density due to the device architecture 11 of the different zones in semiconductor substrate 10, is caused
10 different zones of semiconductor substrate are different to the reflectivity of thermal energy, cause the difference of the absorption heat between different zones, finally
So that 10 uneven heating of semiconductor substrate, influences device property.
Secondly, executing step S2, with continued reference to shown in Fig. 2, an amorphous carbon is formed in the front of the semiconductor substrate 10
Layer 20.In the present embodiment, the amorphous carbon layer 20 is formed using chemical vapor deposition process, institute is formed using ethane (C2H2)
The temperature stated amorphous carbon layer 20, and carry out chemical vapor deposition process is 200 DEG C~400 DEG C, for example, 250 DEG C, 300 DEG C, 350
℃.In the present embodiment, the amorphous carbon layer 20 with a thickness of 300nm~600nm, for example, 400nm, 500nm, 500nm, amorphous
Carbon-coating 20 is selected with a thickness of according to the uneven situation of semiconductor substrate surface, so that the amorphous carbon layer 20 is complete
Device architecture 11 described in all standing, and the front of the semiconductor substrate 10 is made to form flat structure by uneven, from
And in rapid thermal anneal process, the front of semiconductor substrate 10 is flat structure, and is identical amorphous carbon material, is made
The thermal absorptivity obtained everywhere in the front of semiconductor substrate is all the same.
Then, refering to what is shown in Fig. 3, forming a coating 30 on 20 surface of amorphous carbon layer, coating 30 covers described
Amorphous carbon layer, in the present embodiment, the coating 30 is silicon oxide layer, can form silica using chemical vapor deposition process
Layer, also, silicon oxide layer can't generate pollution to the cavity of amorphous carbon layer 20 and subsequent annealing process.Certainly, of the invention
In, the coating 30 is not limited to as silicon oxide layer, for example, it is also possible to for polysilicon layer etc..The thickness of the coating 30
For 50nm~100nm, for example, can be 60nm, 80nm.It is understood that coating 30 is used for amorphous for coating 30
Other semiconductor substrates in carbon-coating 20 in the cavity and cavity of amorphous carbon material pollution annealing.
Again, refering to what is shown in Fig. 4, executing step S3, front rapid thermal anneal process is carried out to the semiconductor substrate 10
40.In the present invention, carrying out temperature used by front rapid thermal anneal process 40 is 300 DEG C~500 DEG C, for example, 350 DEG C,
400℃,450℃.It is understood that absorbed layer of the amorphous carbon layer 20 as heat, absorbs the heat of fluorescent tube radiation in cavity,
Conducting shell as heat simultaneously, the heat of absorption is transmitted in the device architecture 11 of semiconductor substrate 10, due to amorphous carbon
Layer 20 can reduce the difference of the reflectivity of 10 different zones of semiconductor substrate, and amorphous carbon layer 20 can be reduced by device architecture 11
Temperature difference caused by the difference of surface topography and reflectivity.The even heat that each region of one side semiconductor substrate absorbs, separately
One side amorphous carbon layer heat can be evenly dispersed, guarantees that device architecture 11 is heated evenly.
Refering to what is shown in Fig. 5, it is fast to carry out the back side to the semiconductor substrate 10 in another embodiment in the present invention
Speed heat annealing process 50.Overleaf during quick thermal annealing process, used temperature is 300 DEG C~500 DEG C, for example, 350
℃,400℃,450℃.In carrying out back side thermal anneal process, absorbed layer of the semiconductor substrate as heat, since semiconductor serves as a contrast
The back side at bottom 10 is not due to having device architecture 11, the surfacing at the back side, the heat that 10 back side each section of semiconductor substrate absorbs
Amount uniformly, and the even heat of absorption is transmitted in device architecture 11, due to the presence of amorphous carbon layer 20,20 energy of amorphous carbon layer
The dispersion so that even heat is reached, so that the even heat that device architecture 11 absorbs, guarantees the uniformity of thermal anneal process.
In addition, ultra-shallow junctions method for annealing of the invention further include: remove the amorphous carbon layer 20 and the coating 30.This
In embodiment, the coating can be removed using wet corrosion technique, for example, when coating 30 is silica, using hydrogen
Fluorspar acid solution etching oxidation silicon is to remove coating.Then, the amorphous carbon layer 20 is removed using cineration technics, specifically
, using plasma technique removes the amorphous carbon layer 20.Using oxygen (O2) and carbon tetrafluoride (CF4) plasma
Technique removes the amorphous carbon layer 21.And the semiconductor substrate is cleaned using the mixed solution of sulfuric acid and hydrogen peroxide simultaneously
10, to guarantee that amorphous carbon layer 20 completely removes.
In conclusion ultra-shallow junctions method for annealing of the invention, forms an amorphous carbon layer and one in the front of semiconductor substrate
Coating carries out front rapid thermal annealing or back side rapid thermal annealing to semiconductor substrate later.In the present invention, due to amorphous
The higher heat absorption coefficients of carbon-coating, and simultaneously as the radiator of semiconductor substrate, so that the thermal energy heat source is more uniform
Dispersion is on a semiconductor substrate.So that the device architecture in semiconductor substrate is uniformly heated, annealing temperature is more uniform, from
And improve the performance of device architecture in semiconductor substrate.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (9)
1. a kind of ultra-shallow junctions method for annealing characterized by comprising
Semiconductor substrate is provided, the front of the semiconductor substrate has multiple device architectures, so that the semiconductor substrate
Front is uneven；
An amorphous carbon layer is formed in the front of the semiconductor substrate and a coating, the amorphous carbon layer are completely covered described more
A device architecture, the coating cover the amorphous carbon layer, wherein the amorphous carbon layer with a thickness of 300nm~600nm,
The coating with a thickness of 50nm~100nm；
Front rapid thermal annealing or back side rapid thermal annealing are carried out to the semiconductor substrate.
2. ultra-shallow junctions method for annealing as described in claim 1, which is characterized in that the device architecture is MOS transistor, resistance
Or capacitor, and the device architecture is unevenly distributed in the front of the semiconductor substrate.
3. ultra-shallow junctions method for annealing as described in claim 1, which is characterized in that formed using chemical vapor deposition process described
Amorphous carbon layer, the temperature for being formed the amorphous carbon layer using ethane, and being carried out chemical vapor deposition process are 200 DEG C~400 DEG C.
4. ultra-shallow junctions method for annealing as described in claim 1, which is characterized in that the coating is silicon oxide layer or polysilicon
Layer.
5. ultra-shallow junctions method for annealing as described in claim 1, which is characterized in that fast carrying out front to the semiconductor substrate
After speed heat annealing or back side rapid thermal annealing, the ultra-shallow junctions method for annealing further include: remove the amorphous carbon layer and described
Coating.
6. ultra-shallow junctions method for annealing as claimed in claim 5, which is characterized in that fast carrying out front to the semiconductor substrate
After speed heat annealing or back side rapid thermal annealing, using plasma technique removes the amorphous carbon layer.
7. ultra-shallow junctions method for annealing as claimed in claim 6, which is characterized in that fast carrying out front to the semiconductor substrate
After speed heat annealing or back side rapid thermal annealing, the amorphous carbon layer is removed using oxygen and carbon tetrafluoride plasma process.
8. ultra-shallow junctions method for annealing as claimed in claim 7, which is characterized in that using oxygen and carbon tetrafluoride plasma
After technique removes the amorphous carbon layer, the semiconductor substrate is cleaned using the mixed solution of sulfuric acid and hydrogen peroxide, to protect
The amorphous carbon layer is demonstrate,proved to completely remove.
9. ultra-shallow junctions method for annealing as described in claim 1, which is characterized in that carry out front rapid thermal annealing or negative quick
Temperature used by thermal anneal process is 300 DEG C~500 DEG C.
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| CN107564801A (en) * | 2017-08-31 | 2018-01-09 | 长江存储科技有限责任公司 | A kind of method for annealing |
| CN110364434A (en) * | 2019-07-19 | 2019-10-22 | 德淮半导体有限公司 | The manufacturing method of method for annealing and semiconductor devices |
| CN114975115A (en) * | 2022-06-21 | 2022-08-30 | 上海华力集成电路制造有限公司 | Annealing methods for ultra-shallow junctions |
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| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
| CN103390585A (en) * | 2012-05-11 | 2013-11-13 | 台湾积体电路制造股份有限公司 | Strained-channel semiconductor device fabrication |
| CN103632959A (en) * | 2013-11-15 | 2014-03-12 | 中航（重庆）微电子有限公司 | Grooved Schottky device structure and manufacturing method thereof |
| CN104616993A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| US8471360B2 (en) * | 2010-04-14 | 2013-06-25 | Sandisk 3D Llc | Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same |
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| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
| CN103390585A (en) * | 2012-05-11 | 2013-11-13 | 台湾积体电路制造股份有限公司 | Strained-channel semiconductor device fabrication |
| CN104616993A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103632959A (en) * | 2013-11-15 | 2014-03-12 | 中航（重庆）微电子有限公司 | Grooved Schottky device structure and manufacturing method thereof |
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