CN105958817A - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- CN105958817A CN105958817A CN201610409335.8A CN201610409335A CN105958817A CN 105958817 A CN105958817 A CN 105958817A CN 201610409335 A CN201610409335 A CN 201610409335A CN 105958817 A CN105958817 A CN 105958817A
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- charge pump
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- outfan
- gate
- clock signal
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- 238000001514 detection method Methods 0.000 claims abstract description 26
- 230000005611 electricity Effects 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 17
- 230000010349 pulsation Effects 0.000 description 10
- 240000002853 Nelumbo nucifera Species 0.000 description 6
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 6
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from DC input or output
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The embodiment of the invention discloses a charge pump circuit, which comprises a charge pump unit, a voltage detection unit and at least two charge pump control units, wherein the charge pump unit is used for working or stopping under the control of a clock signal and an enable signal in each cycle to output voltage; the voltage detection unit is used for outputting the enable signal of the next cycle to each charge pump control unit according to a comparison value of output end voltage of each charge pump control unit and a target voltage value; and the at least two charge pump control units correspond to at least two charge pump circuit bodies one by one and are used for generating a high level enable signal when the enable signal of the next cycle is in a high level and input clock signals of the current cycle and the next cycle are in the same level, or else, generating low level enable signals to the enable ends of the corresponding charge pump circuit bodies, so that the charge pump circuit bodies are controlled to work or stop; control on the quantity of the charge pump circuit bodies which are simultaneously started to work is achieved; and the target of reducing output voltage fluctuation and input power supply noise is achieved.
Description
Technical field
The present embodiments relate to circuit engineering, particularly relate to a kind of charge pump circuit.
Background technology
Nonvolatile flash memory medium (nor Flash/nand Flash) is the most common a kind of storage chip, have concurrently with
Machine memorizer (Random Access Memory, RAM) and read only memory (Read-Only Memory,
ROM) advantage, data power down will not lose, and is a kind of can to carry out, in system, the memorizer that electricity is erasable, with
Time its high integration and low cost make it the market mainstream.
Flash chip is made up of internal thousands of memory element, each storage element storage one digit number
According to, the storage completing data by applying corresponding voltage in the wordline of memory element operates, described electricity
Pressure is typically to be produced by charge pump circuit, and the voltage of charge pump circuit output would generally be with certain voltage wave
Dynamic, described voltage pulsation can affect the storage of data, and, along with the contracting of Flash chip technology feature size
Little, the capacitive load of output voltage is also with becoming big, in order to meet requirement readout time of Flash chip, needs
Want many charge pump circuit parallel operations, and then the voltage pulsation causing charge pump circuit to export more greatly and is difficult to
Control, be simultaneously entered power supply noise and also can increase, affect the storage performance of Flash chip.
A kind of charge pump construction schematic diagram of the prior art may refer to shown in Fig. 1, and this electric charge pump includes n
The charge pump circuit of individual parallel connection and the charge pump circuit one to one signal processing circuit in parallel with described n,
Output voltage VO UT carries out dividing potential drop through resistance R3 and R4, compares with reference voltage VREF, when
When output voltage is more than reference voltage, the enable signal PMPEN of output high level, otherwise output low level
Enable signal PMPEN.Enable signal PMPEN to be used for controlling whether the charge pump circuit in next cycle works,
Thus regulate and control output voltage.For each charge pump circuit, whether current period works, and depends on current
The enable signal PMPEN in cycle, when the enable signal PMPEN of current period is high level, in input
Clock signal clk IN<n>driving under charge pump circuit start working；In order to avoid all charge pump circuits
Work simultaneously or do not work, each input clock signal CLKIN<n>there is certain phase contrast, such as Fig. 2
It show four phase place input clock signal schematic diagrams, each input clock signal CLKIN<n>front and back differ greatly
About 1/8 clock cycle.
If controlling a lot of charge pump circuits with above-mentioned four phase clocks, although input clock signal
CLKIN<n>between delay can to a certain degree reduce the fluctuation of output voltage, but can not reach complete
The purpose reduced.Such as, after the most several charge pump circuit of current period quits work, enable signal PMPEN
For low level, the input clock signal CLKIN<n of the most several described charge pump circuits>it is low level, drive
Clock signal clk D<n>be parked in low level, then when next cycle charge pump circuit functions, arrive at t0
During t1, the input clock signal CLKIN<n of the most several described charge pump circuits>it is high level, if now
The enable signal PMPEN of the most several described charge pump circuit becomes high level, the most several the most described stopping works
The drive clock signal CLKD<n of the charge pump circuit made>become high level, the most several described stopping works simultaneously
The charge pump circuit made will start simultaneously at work, thus produce bigger voltage pulsation, as it is shown on figure 3, be
One and multiple charge pump circuits work the voltage pulsation difference schematic diagram produced, wherein, the first curve simultaneously
310 voltage pulsations exported when representing a charge pump circuit functions, the second curve 320 represents multiple electric charge
The voltage pulsation of output when pump circuit works simultaneously.It is similar to, if current period majority charge pump circuit stops
Only after work, it is low for enabling signal PMPEN, the input clock signal of the most several described charge pump circuits
CLKIN<n>it is high level, drive clock signal CLKD<n>it is parked in high level, then at next cycle electricity
During the work of lotus pump circuit, during t2 to t3, the input clock signal of the most several described charge pump circuits
CLKIN<n>it is low level, if the enable signal PMPEN of the most several the most described charge pump circuit becomes high
Level, the drive clock signal CLKD<n of the most several the most described out-of-work charge pump circuits>become simultaneously
Low level, the most several described out-of-work charge pump circuits will start simultaneously at work, and same generation is bigger
Voltage pulsation.Usual each phase place input clock signal CLKIN<n>between delay by CMOS door or resistance
Constitute, may change with the change such as supply voltage, technique, temperature so that t0 to t1 or t2 to t3 it
Between time become big, thus the probability producing bigger voltage pulsation increases.
In sum, need the fluctuation range designing a kind of circuit to reduce charge pump circuit output voltage, carry
The accuracy of high output voltage.
Summary of the invention
The present invention provides a kind of charge pump circuit, makes an uproar with the fluctuation range and input power reducing output voltage
Sound.
The embodiment of the present invention provides a kind of charge pump circuit, and described circuit includes:
Charge pump unit, described charge pump unit includes at least two charge pump circuit, described charge pump circuit
It is connected in parallel with each other, works under the control of clock signal and enable signal for each cycle or stop, with
Output voltage；
Voltage detection unit, the outfan phase of the input of described voltage detection unit and described charge pump unit
Even, for exporting next week according to the output end voltage of described charge pump unit and the fiducial value of target voltage values
The enable signal of phase is to electric charge pump control unit；
At least two electric charge pump control unit, with at least two charge pump circuit one_to_one corresponding, each electric charge pump
The first input end of control unit outfan with described voltage detection unit respectively is connected, and is used for obtaining next
The enable signal in cycle, the second input is for receiving the drive clock signal of current period, the 3rd input
Being connected with input clock source respectively, for obtaining the input clock signal in next cycle, described electric charge pump controls
Unit is believed for the input clock that enable signal is high level, current period and next cycle in next cycle
When number being same level, produce high level and enable signal, otherwise produce low level and enable signal, described electric charge
The outfan of pump control unit is connected with the Enable Pin of charge pump circuit, is used for exporting enable signal to described electricity
Lotus pump circuit, wherein, has Phase delay between the input clock signal of each charge pump circuit.
Exemplarily, described voltage detection unit includes division module and enables signal output module, wherein,
Described division module is for carrying out dividing potential drop to the output end voltage of described charge pump unit；Described enable signal is defeated
Go out module and enable for the fiducial value output of the output end voltage according to described charge pump unit with target voltage values
Signal.
Preferably, described division module includes the first resistance and the second resistance, described enable signal output module
Including the first comparator, wherein:
First end of described first resistance is connected with the outfan of described charge pump unit, the second end and described the
First end of two resistance is connected, the second end ground connection of described second resistance；Described first comparator anti-phase defeated
Entering end to be connected with the second end of described first resistance, normal phase input end is connected with reference voltage, and outfan exports
Enable signal.
Further, described circuit also includes:
At least two signal processing unit, with described at least two charge pump circuit and at least two electric charge pump control
The outfan of unit one_to_one corresponding processed, the first input end of each signal processing unit and electric charge pump control unit
Being connected, for obtaining the enable signal in next cycle, the second input is connected with input clock source, is used for obtaining
Taking off the input clock signal in a cycle, described signal processing unit is under the control of described enable signal
Produce drive clock signal and the opposite phased driving clock signal driving next cycle charge pump circuit functions, to drive
Dynamic charge pump circuit functions.
Preferably, described signal processing unit includes: the 4th phase inverter, the second nor gate, the 3rd nor gate,
Four nor gate and the 3rd and door,
Wherein, the input of described 4th phase inverter and the 3rd with the second input of door respectively with electric charge pump control
The outfan of unit processed is connected, and the outfan of the 4th phase inverter and the second input of the second nor gate are connected；
The first input end of the second nor gate and the 3rd is connected with input clock signal respectively with the second input of door,
The outfan of the second nor gate and the first input end of the 3rd nor gate are connected；Second input of the 3rd nor gate
End is connected with the outfan of four nor gate, and the first input end of outfan and four nor gate is connected；4th
Second input of nor gate and the 3rd is connected with the outfan of door.
Preferably, described electric charge pump control unit includes: the first phase inverter, the second phase inverter, first and door,
Second with door, the first nor gate, the first NAND gate, the second NAND gate and the 3rd phase inverter,
Wherein, the input of described first phase inverter and first with the second input of door respectively with input clock
Signal is connected, and the outfan of the first phase inverter and second is connected with the first input end of door；Described second anti-phase
The input of device and first is connected with the drive clock signal of current period respectively with the first input end of door, the
The outfan of two phase inverters and second is connected with the second input of door；First with the outfan of door and first or
The first input end of not gate is connected；Second is connected with the outfan of door and the second input of the first nor gate；
The outfan of the first nor gate and the second input of the second NAND gate are connected；First input of the second NAND gate
End is connected with the outfan of the first NAND gate, and the second input of outfan and the first NAND gate is connected；First
The first input end of NAND gate is connected with the outfan of voltage detection unit, outfan and the 3rd phase inverter defeated
Enter end to be connected.
Further, described circuit also includes input clock source, described input clock source respectively with electric charge pump control
Unit processed, signal processing unit are connected, for producing the input clock signal of setpoint frequency.
The embodiment of the present invention provide a kind of charge pump circuit, by the drive clock signal of current period and under
The input clock signal in one cycle and enable signal, determine the enable signal in next cycle, it is to avoid go out jointly
The situation that existing multiple charge pump circuits work simultaneously, it is achieved that when multiple charge pump circuit parallel operation, control
System starts the quantity of the charge pump circuit started working simultaneously, thus reached the fluctuation of reduction output voltage and
The purpose of input power noise.
Accompanying drawing explanation
Fig. 1 is a kind of charge pump construction schematic diagram of the prior art；
Fig. 2 is four phase place input clock signal schematic diagrams；
When Fig. 3 is a charge pump circuit functions and multiple charge pump circuit works simultaneously, output voltage fluctuates
Contrast schematic diagram；
Fig. 4 is the structural representation of a kind of charge pump circuit that the embodiment of the present invention one provides；
Fig. 5 is the structural representation of the voltage detection unit that the embodiment of the present invention two provides
Fig. 6 is the circuit diagram of a kind of voltage detection unit that the embodiment of the present invention two provides；
Fig. 7 is the circuit diagram of a kind of electric charge pump control unit that the embodiment of the present invention three provides；
Fig. 8 is each signal waveform schematic diagram that the embodiment of the present invention three provides；
Fig. 9 is the charge pump circuit of the present invention that provides of the embodiment of the present invention three and existing charge pump circuit exists
Input power noise under same loading condition and current simulations comparison of wave shape schematic diagram；
Figure 10 is the structural representation of a kind of charge pump circuit that the embodiment of the present invention four provides；
Figure 11 is the circuit diagram of a kind of signal processing unit that the embodiment of the present invention four provides.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this
Specific embodiment described by place is used only for explaining the present invention, rather than limitation of the invention.The most also need
It is noted that for the ease of describing, accompanying drawing illustrate only part related to the present invention and not all knot
Structure.
Embodiment one
A kind of charge pump circuit structural representation that Fig. 4 provides for the embodiment of the present invention one, the present embodiment is suitable for
Situation in multiple charge pump circuit parallel operations.Referring specifically to as shown in Figure 4, the present embodiment provide one
Plant charge pump circuit to specifically include: charge pump unit 410, voltage detection unit 420 and at least two electric charge
Pump control unit 430.
Charge pump unit 410, including at least two charge pump circuit 411, charge pump circuit 411 is parallel with one another
Connect, for each cycle at clock signal clk IN<n>and enable signal PMPEN-NEW control under
Work or stopping, with output voltage；
The input of voltage detection unit 420 is connected with the outfan of charge pump unit 410, for according to electricity
The output end voltage VOUT of lotus pump unit 410 and the fiducial value of target voltage values export the enable in next cycle
Signal PMPEN is to electric charge pump control unit 430；
At least two electric charge pump control unit 430, and at least two charge pump circuit 411 one_to_one corresponding, often
The first input end of individual electric charge pump control unit 430 outfan with voltage detection unit 420 respectively is connected,
For obtaining the enable signal PMPEN in next cycle, what i.e. current period exported is used for controlling next cycle electricity
The enable signal of lotus pump circuit, the second input is for receiving the drive clock signal CLKD<n of current period>,
3rd input is connected with input clock source respectively, for obtaining the input clock signal in next cycle
CLKIN<n>, electric charge pump control unit 430 is high level for the enable signal PMPEN in next cycle,
The drive clock signal CLKD<n of current period>and the input clock signal CLKIN<n in next cycle>be
During same level, produce high level and enable signal PMPEN-NEW, otherwise produce low level and enable signal
PMPEN-NEW, this enable signal PMPEN-NEW are to actually enter charge pump circuit next cycle to carry out
The enable signal controlled.The outfan of electric charge pump control unit 430 and the Enable Pin phase of charge pump circuit 411
Even, it is used for exporting enable signal PMPEN-NEW to charge pump circuit 411, wherein, each charge pump circuit
Input clock signal CLKIN<n>between have Phase delay.
Whether the first input end signal PMPEN of each electric charge pump control unit 430 is that high level depends on
Whether the output end voltage VOUT of charge pump unit 410 reaches target voltage values, if it is, first is defeated
Entering end signal PMPEN is high level, and otherwise first input end signal PMPEN is low level；Second input
End signal CLKD<n>depend on this electric charge pump control unit 430 correspondence for high level or low level
The duty of charge pump circuit 411 current period, if the charge pump circuit of correspondence 411 current period
Duty is off work, then the second input end signal CLKD<n>is low level, is otherwise high level；
And the input clock signal CLKIN<n of the 3rd input>it is the pulse signal of setting cycle.When the first input
When the enable signal PMPEN of end signal, i.e. next cycle is low level, corresponding electric charge pump control unit
430 output low levels enable signal PMPEN-NEW to corresponding charge pump circuit 411, then next cycle
This charge pump circuit 411 does not works；Enable signal PMPEN when first input end signal, i.e. next cycle
During for high level, and the second input (the drive clock signal CLKD<n of current period>) and the 3rd input
When end (the input clock signal CLKIN<n in next cycle>) is same level, corresponding electric charge pump controls
Unit 430 exports high level and enables signal PMPEN-NEW to corresponding charge pump circuit 411, then next
Cycle, this charge pump circuit 411 was started working.
Thus, it is supposed that the most several charge pump circuit of current period 411 quits work, corresponding enable signal
PMPEN is low level, the input clock signal CLKIN<n of the most several described charge pump circuits 411>it is low
Level, then current period drive clock signal CLKD<n>it is parked in low level, then at next cycle electric charge pump
When circuit 411 works, during t0 to t1, the input clock signal of the most several described charge pump circuits 411
CLKIN<n>it is high level, if the enable signal PMPEN of the most described the most several charge pump circuit 411 becomes
For high level, but due to the drive clock signal CLKD<n of the most several described charge pump circuit 411 current periods>
It is parked in low level, with the input clock signal CLKIN<n in next cycle>it not same level, thus electric
Lotus pump control unit 430 produces low level and enables signal to the most several described charge pump circuits 411, so institute
State the most several out-of-work charge pump circuit 411 and will no longer start simultaneously at work, due to each charge pump circuit
The input clock signal CLKIN<n of 411>between have certain Phase delay, so along with each input clock is believed
Number CLKIN<n>become low level successively, corresponding each out-of-work charge pump circuit 411 will open successively
Move and start working, thus reduce voltage pulsation.
Same principle, it is assumed that current period majority charge pump circuit 411 quits work, corresponding enable letter
Number PMPEN is low, the input clock signal CLKIN<n of the most several described charge pump circuits 411>it is high
Level, then drive clock signal CLKD<n>it is parked in high level, then at next cycle charge pump circuit 411
During work, during t2 to t3, the input clock signal CLKIN<n of the most several described charge pump circuits 411>
For low level, if the enable signal PMPEN of the most described the most several charge pump circuit 411 becomes high level,
But the drive clock signal CLKD<n due to the most several described charge pump circuit 411 current periods>it is parked in
High level, with the input clock signal CLKIN<n in next cycle>it not same level, so described majority
Individual out-of-work charge pump circuit 411 will no longer start simultaneously at work, thus reduce voltage pulsation.
A kind of charge pump circuit that the present embodiment provides, by between voltage detection unit and charge pump circuit
Increase electric charge pump control unit, and the first input end of described electric charge pump control unit is examined with described voltage respectively
The outfan surveying unit is connected, and for obtaining the enable signal in next cycle, the second input is worked as receiving
The drive clock signal in front cycle, the 3rd input is connected with input clock source respectively, is used for obtaining next week
The input clock signal of phase, described electric charge pump control unit is high level for the enable signal in next cycle,
When the drive clock signal of current period and the input clock signal in next cycle are same level, produce high electricity
The flat signal that enables, otherwise produces low level and enables the signal Enable Pin to charge pump circuit, and then control electric charge
The work of pump circuit and stopping, it is achieved that when multiple charge pump circuit parallel operation, control to start to open simultaneously
The quantity of the charge pump circuit of beginning work, thus reached the fluctuation of reduction output voltage and input power noise
Purpose.
Embodiment two
Fig. 5 is the structural representation of the voltage detection unit that the embodiment of the present invention two provides, at above-described embodiment
On the basis of, voltage detection unit 420 is optimized by the present embodiment, shown in Figure 5, and voltage is examined
Survey unit 420 to include:
Division module 421 and enable signal output module 422, wherein, division module 421 is for electric charge
The output end voltage of pump unit 410 carries out dividing potential drop；Enable signal output module 422 for according to electric charge pump list
The output end voltage of unit 410 enables signal PMPEN with the fiducial value output of target voltage values.
Preferably, as a kind of implementation of voltage detection unit 420, shown in Figure 6, dividing potential drop mould
Block 421 includes: the first resistance R1 and the second resistance R2, enables signal output module 422 and includes the first ratio
Relatively device COMP1, wherein:
First end of the first resistance R1 is connected with the outfan VOUT of charge pump unit 410, the second end with
First end of the second resistance R2 is connected, the second end ground connection of the second resistance R2；First comparator COMP1
Inverting input and the first resistance R1 the second end be connected, normal phase input end and reference voltage VREF phase
Even, outfan output enables signal PMPEN；
Wherein, the resistance of the first resistance R1 and the second resistance R2 is according to the output target of charge pump unit 410
Voltage is chosen.
The technical scheme of the present embodiment, is optimized for voltage detection unit division module and enables signal output mould
Block, wherein, division module, for the output end voltage of charge pump unit is carried out dividing potential drop, enables signal output
Module is for exporting next cycle according to the output end voltage of charge pump unit and the fiducial value of target voltage values
Enable signal, so that electric charge pump control unit can produce according to described enable signal controls next cycle
The enable signal of charge pump circuit functions.
Embodiment three
Fig. 7 is the circuit diagram of a kind of electric charge pump control unit that the embodiment of the present invention three provides, in above-mentioned enforcement
On the basis of example, electric charge pump control unit 430 is optimized by the present embodiment, each charge pump circuit
411 all corresponding electric charge pump control units 430.Referring specifically to shown in Fig. 7,
Electric charge pump control unit 430 specifically includes: the first phase inverter T1, the second phase inverter T2, first with
Door Y1, second and door Y2, the first nor gate HF1, the first NAND gate YF1, the second NAND gate YF2 and
3rd phase inverter T3.
Wherein, the input of the first phase inverter T1 and first with second input of door Y1 respectively with input time
Clock signal CLKIN is connected, the outfan of the first phase inverter T1 and second and the first input end phase of door Y2
Even；The input of described second phase inverter T2 and first with the first input end of door Y1 respectively with current period
Drive clock signal CLKD be connected, the outfan of the second phase inverter T2 and second is defeated with the second of door Y2
Enter end to be connected；First is connected with the outfan of door Y1 and the first input end of the first nor gate HF1；Second
It is connected with the outfan of door Y2 and second input of the first nor gate HF1；First nor gate HF1's is defeated
Go out end to be connected with the second input of the second NAND gate YF2；The first input end of the second NAND gate YF2 and
The outfan of one NAND gate YF1 is connected, and the second input of outfan and the first NAND gate YF1 is connected；The
The first input end of one NAND gate YF1 is connected with the outfan PMPEN of voltage detection unit 420, output
End is connected with the input of the 3rd phase inverter T3.
In order to illustrate the operation principle of electric charge pump control unit 430 that the embodiment of the present invention provides, set each
The input clock signal CLKIN of charge pump circuit 411 correspondence differs 1/8 clock cycle successively, specifically may be used
With four phase place input clock signal schematic diagrams shown in Figure 2.Circuit diagram shown in Figure 7, if
The first input end PMPEN of the first NAND gate YF1 is low level, then the outfan of the 3rd phase inverter T3
PMPEN-NEW is also low level；If the first input end PMPEN of the first NAND gate YF1 is high electricity
Flat, then at first input end and the second phase inverter T2 of input clock signal CLKIN and first and door Y1
Input CLKD time same level occurs, the outfan PMPEN-NEW of the 3rd phase inverter T3 is
High level.The enable signal PMPEN-NEW in next cycle of each charge pump circuit 411 by oneself
The input clock signal CLKIN in next cycle and the shadow of the drive clock signal CLKD state of current period
Ring and different.The electric charge pump in next cycle of electric charge pump control unit 430 output enables signal
PMPEN-NEW waveform diagram is shown in Figure 8, it is seen that making of next cycle of charge pump circuit 411
High level, making of next cycle of first charge pump circuit 411 can be become successively by signal PMPEN-NEW
Can signal PMPEN-NEW<1>to the enable signal in next cycle of the n-th charge pump circuit 411
PMPEN-NEW<n>become the moment input clock signal by each charge pump circuit 411 correspondence of high level
Delay between CLKIN determines, therefore, it is to avoid the problem that multiple charge pump circuits 411 work simultaneously,
Reduce input power noise and the output voltage fluctuation of charge pump unit 410.
Specifically may refer to the charge pump circuit of the present invention shown in Fig. 9 and existing charge pump circuit equally
Input power noise Simulation comparison of wave shape schematic diagram under loading condition, wherein the 3rd curve 3 represents the present invention
The input power noise of charge pump unit 410, the 4th curve 4 represents charge pump unit 410 in prior art
Input power noise, the 5th curve 5 represents the source current of the input of the charge pump unit 410 of the present invention,
6th curve 6 represents the input power electric current of charge pump unit 410 in prior art, it can be seen that by this
The technical scheme of invention, it will be apparent that reduce the input power noise of charge pump unit 410.
Above-mentioned electric charge pump control unit 430 achieves when current period enable signal PMPEN is low level,
The outfan PMPEN-NEW of electric charge pump control unit 430 is low level, corresponding charge pump circuit 411
Next cycle does not works；When the enable signal PMPEN of current period is high level, and next cycle
When the drive clock signal CLKD of input clock signal CLKIN and current period is same level, electric charge
The outfan PMPEN-NEW of pump control unit 430 is high level, corresponding charge pump circuit 411 next
Cycle starts work.
The circuit diagram of a kind of electric charge pump control unit that the present embodiment provides, it is achieved that when current period enables letter
When number being low level, the outfan of electric charge pump control unit is low level, corresponding next week of charge pump circuit
Phase does not works；When the enable signal of current period is high level, and the input clock signal in next cycle with
When the drive clock signal of current period is same level, the outfan of electric charge pump control unit is high level,
Corresponding next cycle of charge pump circuit starts work.
Embodiment four
Figure 10 is the structural representation of a kind of charge pump circuit that the embodiment of the present invention four provides, in above-mentioned enforcement
On the basis of example, the present embodiment has carried out further optimization, at electric charge pump control unit 430 and electric charge pump electricity
Add signal processing unit 440 between road 411, specifically may refer to shown in Figure 10, described electric charge pump electricity
Road includes:
Charge pump unit 410, voltage detection unit 420, at least two electric charge pump control unit 430 and at least
Two signal processing units 440.
Charge pump unit 410, including at least two charge pump circuit 411, charge pump circuit 411 is parallel with one another
Connect, for each cycle at clock signal clk IN<n>and enable signal PMPEN-NEW control under
Work or stopping, with output voltage；
The input of voltage detection unit 420 is connected with the outfan of charge pump unit 410, for according to electricity
The output end voltage VOUT of lotus pump unit 410 and the fiducial value of target voltage values export the enable in next cycle
Signal PMPEN is to electric charge pump control unit 430；
At least two electric charge pump control unit 430, and at least two charge pump circuit 411 one_to_one corresponding, often
The first input end of individual electric charge pump control unit 430 outfan with voltage detection unit 420 respectively is connected,
For obtaining the enable signal PMPEN in next cycle, when the second input is for receiving the driving of current period
Clock signal CLKD<n>, the 3rd input is connected with input clock source respectively, for obtaining the defeated of next cycle
Entering clock signal CLKIN<n>, electric charge pump control unit 430 is for the enable signal in next cycle
PMPEN is high level, the drive clock signal CLKD<n of current period>and the input clock in next cycle
Signal CLKIN<n>when being same level, produce high level and enable signal, otherwise produce low level and enable letter
Number, the outfan of electric charge pump control unit 430 is connected with the Enable Pin of charge pump circuit 411, is used for exporting
Signal PMPEN-NEW is to charge pump circuit 411 for enable, wherein, and the input clock letter of each charge pump circuit
Number CLKIN<n>between have Phase delay.
At least two signal processing unit 440 and at least two charge pump circuit 411 and at least two electric charge pump
Control unit 430 one_to_one corresponding, the first input end of each signal processing unit 440 and electric charge pump control single
The outfan of unit 430 is connected, for obtaining the enable signal PMPEN-NEW in next cycle, and the second input
End is connected with input clock source, for obtaining the input clock signal CLKIN in next cycle, signal processing list
Unit 440 drives next cycle charge pump circuit work for producing under the control enabling signal PMPEN-NEW
Make the drive clock signal CLKD and opposite phased driving clock signal CLKDB of 411, to drive electric charge pump electricity
Road 411 works.
Preferably, as a kind of implementation of signal processing unit 440, shown in Figure 11, at signal
Reason unit 440 include: the 4th phase inverter T4, the second nor gate HF2, the 3rd nor gate HF3, the 4th or
Not gate HF4 and the 3rd and door Y3,
Wherein, the input of the 4th phase inverter T4 and the 3rd with the first input end of door Y3 respectively with electric charge pump
The outfan PMPEN_NEW of control unit 430 be connected, the outfan of the 4th phase inverter T4 and second or
Second input of not gate HF2 is connected；The first input end of the second nor gate HF2 and the 3rd is with door Y3's
Second input is connected with input clock signal CLKIN respectively, the outfan of the second nor gate HF2 and
The first input end of three nor gate HF3 is connected；Second input of the 3rd nor gate HF3 and four nor gate
The outfan of HF4 is connected, and the first input end of outfan and four nor gate HF4 is connected；Four nor gate
Second input of HF4 and the 3rd is connected with the outfan of door Y3.
Input and the first input end signal PMPEN-NEW of the 3rd and door Y3 as the 4th phase inverter T4
During for high level, the drive clock signal CLKD driving the work of next cycle charge pump circuit 411 of generation
Change Tong Bu with input clock signal CLKIN；Input and the 3rd and door Y3 as the 4th phase inverter T4
First input end signal PMPEN-NEW when being low level, do not produce next cycle charge pump circuit of driving
The drive clock signal CLKD, input clock signal CLKIN of 411 work are cut off.
On the basis of the various embodiments described above, described charge pump circuit also includes input clock source, described defeated
Enter clock source to be connected with electric charge pump control unit 430, signal processing unit 440 respectively, be used for producing setting
The input clock signal CLKIN of frequency.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.Those skilled in the art
It will be appreciated that the invention is not restricted to specific embodiment described here, can enter for a person skilled in the art
Row various obvious changes, readjust and substitute without departing from protection scope of the present invention.Therefore, though
So by above example, the present invention is described in further detail, but the present invention be not limited only to
Upper embodiment, without departing from the inventive concept, it is also possible to include other Equivalent embodiments more,
And the scope of the present invention is determined by scope of the appended claims.
Claims (7)
1. a charge pump circuit, it is characterised in that including:
Charge pump unit, described charge pump unit includes at least two charge pump circuit, described charge pump circuit
It is connected in parallel with each other, works under the control of clock signal and enable signal for each cycle or stop, with
Output voltage；
Voltage detection unit, the outfan phase of the input of described voltage detection unit and described charge pump unit
Even, for exporting next week according to the output end voltage of described charge pump unit and the fiducial value of target voltage values
The enable signal of phase is to electric charge pump control unit；
At least two electric charge pump control unit, with at least two charge pump circuit one_to_one corresponding, each electric charge pump
The first input end of control unit outfan with described voltage detection unit respectively is connected, and is used for obtaining next
The enable signal in cycle, the second input is for receiving the drive clock signal of current period, the 3rd input
Being connected with input clock source respectively, for obtaining the input clock signal in next cycle, described electric charge pump controls
Unit is high level for the enable signal in next cycle, the drive clock signal of current period and next week
When the input clock signal of phase is same level, produces high level and enable signal, otherwise produce low level and enable
Signal, the outfan of described electric charge pump control unit is connected with the Enable Pin of charge pump circuit, makes for output
Described charge pump circuit can be given by signal, wherein, between the input clock signal of each charge pump circuit, have phase place to prolong
Late.
Circuit the most according to claim 1, it is characterised in that described voltage detection unit includes dividing potential drop
Module and enable signal output module, wherein, described division module is for the output to described charge pump unit
Terminal voltage carries out dividing potential drop；Described enable signal output module is for the outfan electricity according to described charge pump unit
Pressure enables signal with the fiducial value output of target voltage values.
Circuit the most according to claim 2, it is characterised in that described division module includes the first resistance
With the second resistance, described enable signal output module includes the first comparator, wherein:
First end of described first resistance is connected with the outfan of described charge pump unit, the second end and described the
First end of two resistance is connected, the second end ground connection of described second resistance；Described first comparator anti-phase defeated
Entering end to be connected with the second end of described first resistance, normal phase input end is connected with reference voltage, and outfan exports
Enable signal.
4. according to the circuit described in claim 1 or 3, it is characterised in that described electric charge pump control unit bag
Include: the first phase inverter, the second phase inverter, first with door, second with door, the first nor gate, first with non-
Door, the second NAND gate and the 3rd phase inverter,
Wherein, the input of described first phase inverter and first with the second input of door respectively with input clock
Signal is connected, and the outfan of the first phase inverter and second is connected with the first input end of door；Described second anti-phase
The input of device and first is connected with the drive clock signal of current period respectively with the first input end of door, the
The outfan of two phase inverters and second is connected with the second input of door；First with the outfan of door and first or
The first input end of not gate is connected；Second is connected with the outfan of door and the second input of the first nor gate；
The outfan of the first nor gate and the second input of the second NAND gate are connected；First input of the second NAND gate
End is connected with the outfan of the first NAND gate, and the second input of outfan and the first NAND gate is connected；First
The first input end of NAND gate is connected with the outfan of voltage detection unit, outfan and the 3rd phase inverter defeated
Enter end to be connected.
Circuit the most according to claim 1, it is characterised in that also include:
At least two signal processing unit, with described at least two charge pump circuit and at least two electric charge pump control
The outfan of unit one_to_one corresponding processed, the first input end of each signal processing unit and electric charge pump control unit
Being connected, for obtaining the enable signal in next cycle, the second input is connected with input clock source, is used for obtaining
Taking off the input clock signal in a cycle, described signal processing unit is under the control of described enable signal
Produce drive clock signal and the opposite phased driving clock signal driving next cycle charge pump circuit functions, to drive
Dynamic charge pump circuit functions.
Circuit the most according to claim 5, it is characterised in that described signal processing unit includes: the
Four phase inverters, the second nor gate, the 3rd nor gate, four nor gate and the 3rd and door,
Wherein, the input of described 4th phase inverter and the 3rd with the second input of door respectively with electric charge pump control
The outfan of unit processed is connected, and the outfan of the 4th phase inverter and the second input of the second nor gate are connected；
The first input end of the second nor gate and the 3rd is connected with input clock signal respectively with the second input of door,
The outfan of the second nor gate and the first input end of the 3rd nor gate are connected；Second input of the 3rd nor gate
End is connected with the outfan of four nor gate, and the first input end of outfan and four nor gate is connected；4th
Second input of nor gate and the 3rd is connected with the outfan of door.
Circuit the most according to claim 5, it is characterised in that also include input clock source, described defeated
Enter clock source to be connected with electric charge pump control unit, signal processing unit respectively, for producing the defeated of setpoint frequency
Enter clock signal.
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| CN201610409335.8A CN105958817B (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
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|---|---|---|---|
| CN201610409335.8A CN105958817B (en) | 2016-06-12 | 2016-06-12 | A kind of charge pump |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109756106A (en) * | 2018-12-27 | 2019-05-14 | 西安紫光国芯半导体有限公司 | A kind of method and circuit reducing charge pump system noise |
| CN111313694A (en) * | 2018-12-12 | 2020-06-19 | 北京兆易创新科技股份有限公司 | Charge pump control unit, charge pump circuit and nonvolatile memory |
| CN111404372A (en) * | 2020-05-08 | 2020-07-10 | Oppo广东移动通信有限公司 | Charge pump circuit, chip and terminal |
| CN111817553A (en) * | 2020-07-01 | 2020-10-23 | 浙江驰拓科技有限公司 | On-chip charge pump circuit |
| CN112165250A (en) * | 2020-10-12 | 2021-01-01 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
| CN113346739A (en) * | 2021-05-28 | 2021-09-03 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
| CN113824316A (en) * | 2021-10-26 | 2021-12-21 | 上海交通大学 | A synthesizable charge pump circuit based on digital inverter |
| CN114167936A (en) * | 2021-12-03 | 2022-03-11 | 中国科学院半导体研究所 | CMOS Charge Pump Pumping Device with Wide Operating Voltage Range |
| CN114421760A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第二十四研究所 | Power generation circuit in time-interleaved charge pump |
| CN114520009A (en) * | 2022-01-27 | 2022-05-20 | 珠海博雅科技股份有限公司 | Charge pump system and nonvolatile memory comprising same |
| CN114915164A (en) * | 2022-04-07 | 2022-08-16 | 北京中电华大电子设计有限责任公司 | Circuit and method for smoothly controlling starting power consumption of charge pump |
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| CN119030323A (en) * | 2024-10-29 | 2024-11-26 | 上海朔集半导体科技有限公司 | Charge pump circuit, chip and terminal equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634268A (en) * | 2016-01-15 | 2016-06-01 | 西安紫光国芯半导体有限公司 | Charge pump power supply with low ripple voltage |
| CN206060529U (en) * | 2016-06-12 | 2017-03-29 | 北京兆易创新科技股份有限公司 | A kind of charge pump |
-
2016
- 2016-06-12 CN CN201610409335.8A patent/CN105958817B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634268A (en) * | 2016-01-15 | 2016-06-01 | 西安紫光国芯半导体有限公司 | Charge pump power supply with low ripple voltage |
| CN206060529U (en) * | 2016-06-12 | 2017-03-29 | 北京兆易创新科技股份有限公司 | A kind of charge pump |
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| CN111313694A (en) * | 2018-12-12 | 2020-06-19 | 北京兆易创新科技股份有限公司 | Charge pump control unit, charge pump circuit and nonvolatile memory |
| CN109756106A (en) * | 2018-12-27 | 2019-05-14 | 西安紫光国芯半导体有限公司 | A kind of method and circuit reducing charge pump system noise |
| CN111404372A (en) * | 2020-05-08 | 2020-07-10 | Oppo广东移动通信有限公司 | Charge pump circuit, chip and terminal |
| CN111404372B (en) * | 2020-05-08 | 2023-08-22 | Oppo广东移动通信有限公司 | Charge pump circuit, chip and terminal |
| CN111817553A (en) * | 2020-07-01 | 2020-10-23 | 浙江驰拓科技有限公司 | On-chip charge pump circuit |
| CN111817553B (en) * | 2020-07-01 | 2021-12-24 | 浙江驰拓科技有限公司 | On-chip charge pump circuit |
| CN112165250B (en) * | 2020-10-12 | 2022-04-05 | 唯捷创芯(天津)电子技术股份有限公司 | A charge pump circuit, chip and communication terminal |
| CN112165250A (en) * | 2020-10-12 | 2021-01-01 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
| WO2022078059A1 (en) * | 2020-10-12 | 2022-04-21 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip, and communication terminal |
| CN113346739A (en) * | 2021-05-28 | 2021-09-03 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
| CN113346739B (en) * | 2021-05-28 | 2022-09-09 | 长江存储科技有限责任公司 | Charge pump circuit system, three-dimensional memory and three-dimensional memory system |
| CN113824316A (en) * | 2021-10-26 | 2021-12-21 | 上海交通大学 | A synthesizable charge pump circuit based on digital inverter |
| CN113824316B (en) * | 2021-10-26 | 2023-11-03 | 上海交通大学 | Comprehensive charge pump circuit based on digital inverter |
| CN114167936A (en) * | 2021-12-03 | 2022-03-11 | 中国科学院半导体研究所 | CMOS Charge Pump Pumping Device with Wide Operating Voltage Range |
| CN114421760A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第二十四研究所 | Power generation circuit in time-interleaved charge pump |
| CN114421760B (en) * | 2022-01-14 | 2025-10-17 | 中国电子科技集团公司第二十四研究所 | Time-interleaved charge pump internal power supply generation circuit |
| CN114520009A (en) * | 2022-01-27 | 2022-05-20 | 珠海博雅科技股份有限公司 | Charge pump system and nonvolatile memory comprising same |
| CN114915164A (en) * | 2022-04-07 | 2022-08-16 | 北京中电华大电子设计有限责任公司 | Circuit and method for smoothly controlling starting power consumption of charge pump |
| CN114915164B (en) * | 2022-04-07 | 2024-09-03 | 北京中电华大电子设计有限责任公司 | Circuit and method for smoothly controlling starting power consumption of charge pump |
| CN115940631A (en) * | 2023-01-10 | 2023-04-07 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
| CN115940631B (en) * | 2023-01-10 | 2023-11-17 | 中茵微电子(南京)有限公司 | Low ripple charge pump circuit |
| CN119030323A (en) * | 2024-10-29 | 2024-11-26 | 上海朔集半导体科技有限公司 | Charge pump circuit, chip and terminal equipment |
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