CN105811986A - High-speed conversion successive approximation ADC circuit - Google Patents
High-speed conversion successive approximation ADC circuit Download PDFInfo
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- CN105811986A CN105811986A CN201610116745.3A CN201610116745A CN105811986A CN 105811986 A CN105811986 A CN 105811986A CN 201610116745 A CN201610116745 A CN 201610116745A CN 105811986 A CN105811986 A CN 105811986A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention discloses a high-speed conversion successive approximation ADC circuit, comprising a first capacitance converting array, a second capacitance converting array, a first comparator, a second comparator, a SAR control logic, a differential signal inputting terminal, a first bootstrap switch and a second bootstrap switch. According to the invention, the high 5 bits of a ten-bit DAC capacitance array can be determined by the quantification of a 5-bit small capacitance array, which can increase the conversion speed in successive approximation ADC while ensuring low energy consumption in the process.
Description
Technical field
The present invention relates to technical field of integrated circuits, be specifically related to the Approach by inchmeal adc circuit of a kind of high-speed transitions.
Background technology
Data converter is the bridge connecting simulated world and digital world, and it is widely used in electronic system, such as wireless receiver, mobile phone, health medical treatment electronic device, digital image processing system etc..These application of great majority are required for the data converter of high-speed low-power-consumption, although pipeline ADC can reach significantly high speed, but generally power consumption is bigger；Traditional successive approximation register type (SAR) analog-digital converter (ADC) power consumption is relatively low, but along with the raising of resolution, conversion speed is restricted.
Along with the development of CMOS technology, successive approximation analog to digital C is owing to adopting digital circuit in a large number, and power consumption can reach very low, thus being once again subjected to favor.The reason that traditional successive approximation analog to digital C speed is restricted mainly has the digital to analog converter (DAC) of three: capacitive character DAC to set up the time, the time delay of comparator decision time and Digital Logical Circuits.
Multichannel successive approximation analog to digital C technology can reach significantly high sample rate, and power consumption is relatively low, but to may result in digital circuit complex in the elimination of interchannel mismatch, it is impossible to improves the comparator decision time, reaches relatively high conversion rate.
Summary of the invention
The present invention, based on Terminal Capacitance multiplexing, adopts small capacitances slightly to quantify to determine the successive approximation analog to digital C of high-order electric capacity weights, and while reaching high-speed sampling, the power consumption of circuit is relatively low.
The invention provides the Approach by inchmeal adc circuit of a kind of high-speed transitions, including: the first electric capacity conversion array, the second electric capacity conversion array, the first comparator, the second comparator, SAR control logic, differential signal input, the first bootstrapped switch and the second bootstrapped switch, wherein:
Described differential signal input is linked on the first bootstrapped switch and bootstrapped switch parallel, and controls the switch of logic control the first bootstrapped switch and the second bootstrapped switch based on SAR, completes input differential signal sampling；
Described first electric capacity conversion array and described second electric capacity conversion array include multiple electric capacity, the top crown of the plurality of electric capacity links together, bottom crown selects switch to may be connected to multiple input each via a multi-channel analog, and described first electric capacity conversion array and the second electric capacity conversion array have different bit resolution；
The upper step of described first electric capacity conversion array and the first bootstrapped switch connect, and are linked into the first comparator；
The upper step of described second electric capacity conversion array and the second bootstrapped switch connect, and are linked into the second comparator；
Both end voltage size on the electric capacity conversion array each accessed is compared by described first comparator and the second comparator, and comparative result output to SAR controls logic, and controlled SAR controls logic and completes the conversion of different bit resolution；
SAR controls logic for controlling multidiameter option switch in described first electric capacity conversion array and described second electric capacity conversion array and the switch of bootstrapped switch that described differential signal input is connected to, complete input signal sampling, and the output result according to described first comparator and the second comparator, gradually complete the analogue signal conversion to digital signal, output digital code, and control the conversion of different bit resolution.
Described first electric capacity conversion array is the electric capacity conversion array of 5 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing；Second electric capacity conversion array is the electric capacity conversion array of 10 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing.
Capacitance ratio in described first electric capacity conversion array is 4:2:1:1；Capacitance ratio in described second electric capacity conversion array is 128:64:32:16:8:4:2:1:1.
Described first comparator is low power consumption comparator.
Described second comparator is low noise comparator.
The plurality of input includes ADC reference voltage, common-mode voltage and reference ground.
Described common-mode voltage is the half of reference voltage.
The invention process by the successive approximation analog to digital C-structure of single-pass is improved, as: improve DAC structure, improve DAC set up speed；Redesign quick comparator, improve the comparator decision time；Optimize Digital Logical Circuits, reduce logical delay etc., it is possible to so that successive approximation analog to digital C is intermediate resolution (10), reach relatively high conversion rate (more than hundred megahertzs).And by the small capacitances array of 5 quantify to come in absolute 10 DAC capacitor arrays high 5, it is possible to ensure on the basis that low-power consumption is relatively low, improve the conversion speed of successive approximation analog to digital C.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the successive approximation analog to digital C circuit theory diagrams of the high-speed transitions in the embodiment of the present invention；
Fig. 2 is the successive approximation analog to digital C circuit structure diagram of the high-speed transitions in the embodiment of the present invention；
Fig. 3 is the working timing figure of 10 successive approximation analog to digital C in the embodiment of the present invention；
Fig. 4 is the thick quantization stage figure of the SAR logic register group in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, all other embodiments that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Accordingly, Fig. 1 illustrates the successive approximation analog to digital C circuit theory diagrams of the high-speed transitions in the embodiment of the present invention, this circuit includes: the first electric capacity conversion array, the second electric capacity conversion array, the first comparator, the second comparator, SAR control logic, differential signal input, the first bootstrapped switch and the second bootstrapped switch, wherein: this differential signal input is linked on the first bootstrapped switch and bootstrapped switch parallel, and based on the switch of SAR control logic control the first bootstrapped switch and the second bootstrapped switch, complete input differential signal sampling；This first electric capacity conversion array and described second electric capacity conversion array include multiple electric capacity, the top crown of the plurality of electric capacity links together, bottom crown selects switch to may be connected to multiple input each via a multi-channel analog, and this first electric capacity conversion array and the second electric capacity conversion array have different bit resolution；The upper step of this first electric capacity conversion array and the first bootstrapped switch connect, and are linked into the first comparator；The upper step of this second electric capacity conversion array and the second bootstrapped switch connect, and are linked into the second comparator；Both end voltage size on the electric capacity conversion array each accessed is compared by this first comparator and the second comparator, and comparative result output to SAR controls logic, and controlled SAR controls logic and completes the conversion of different bit resolution；This SAR controls logic for controlling multidiameter option switch in the first electric capacity conversion array and the second electric capacity conversion array and the switch of bootstrapped switch that differential signal input is connected to, complete input signal sampling, and the output result according to the first comparator and the second comparator, gradually complete the analogue signal conversion to digital signal, output digital code, and control the conversion of different bit resolution.
In specific implementation process, the first electric capacity conversion array is the electric capacity conversion array of 5 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing；Second electric capacity conversion array is the electric capacity conversion array of 10 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing.Capacitance ratio in this first electric capacity conversion array is 4:2:1:1；Capacitance ratio in second electric capacity conversion array is 128:64:32:16:8:4:2:1:1.
In specific implementation process, the first comparator adopts low power consumption comparator, and the second comparator adopts low noise comparator.
In specific implementation process, multiple inputs include ADC reference voltage, common-mode voltage and reference ground, and this common-mode voltage is the half of reference voltage.
Concrete, Fig. 2 illustrates the successive approximation analog to digital C circuit structure diagram of the high-speed transitions in the embodiment of the present invention, the Approach by inchmeal adc circuit that the embodiment of the present invention provides, utilize the thought that two steps quantify, with the small capacitances array quantized value based on Terminal Capacitance multiplexing, determining high 5 weights in 10 capacitor arrays, thus significantly reducing setting up the time of bulky capacitor, improving the switching rate of SARADC.Fig. 2 is the successive approximation analog to digital C of 10, and the SAR that this circuit includes the electric capacity conversion array module DAC1 of 5 analog conversion functions and 10 capacitor array module DAC2, comparator module CMP1 and CMP2, bootstrapping sampling switch SW1 and SW2, state variables change controls logic SARControllingLogic.
In Fig. 2, DAC1 module adopts the merging electric capacity DAC structure based on capacitative end multiplexing, and highest order capacitance is 25-3C=4C, for these 5 thick quantization DAC structure, in capacitor array, C3, C2, C1, C0 ratio is 4:2:1:1.Time initial, all electric capacity bottom crowns are connected on common-mode voltage Vcm.Sample phase, bootstrapping sampling switch Guan Bi, capacitor array top crown completes sampling, SARControllingLogic controls CMP1 work, and CMP2 does not work, differential input signal Vip and Vin is directly compared by comparator CMP1, exports MSB1_1 value, simultaneously using this value highest order value as module DAC2.If Vip > Vin, then MSB1_1 value is 1, and SARControllingLogic makes bottom crown corresponding for comparator anode electric capacity C3 receive ground from Vcm simultaneously, and the electric capacity that comparator negative terminal is corresponding receives VREF from Vcm.If comparator output is still 1, then C2 electric capacity is now directly repeated aforesaid operations by Vip-Vin > VREF/2, and otherwise, Vip-Vin >-VREF/2, now comparator anode electric capacity C2 receives VREF from Vcm, and the negative terminal electric capacity of correspondence receives ground from Vcm.It is repeated in aforesaid operations, until the previous position of Terminal Capacitance.For the conversion of Terminal Capacitance, only need to exporting result according to comparator, from Vcm, electric capacity is received ground, another side is then maintained at Vcm.
Often judge one, SARControllingLogic controls the multidiameter option switch that in 5 thick quantization quantization thin with 10 ADC, capacitor array is corresponding simultaneously, small capacitances decision value is passed to the high-order bulky capacitor value that thin quantizer is corresponding, corresponding bulky capacitor is carried out charge/discharge, thus what substantially reduce bulky capacitor in DAC2 module sets up the time simultaneously.When 5 thick quantizations complete, high 5 of 10 thin quantizers also obtain accordingly, and front four bulky capacitor have also been obtained corresponding conversion.Now, SARControllingLogic controls CMP1 and does not work, CMP2 is made to start working, capacitor array is from C4 electric capacity, it is sequentially carried out low level judgement by the merging capacitive way based on Terminal Capacitance multiplexing, finally give 10 output results, thus completing once complete analog and digital signal conversion.
In specific implementation process, low power consumption comparator can reduce the power consumption of circuit, and low noise comparator can improve the conversion accuracy of ADC.
Accordingly, Fig. 3 is the working timing figure of 10 successive approximation analog to digital C.Front 5 conversions of the present invention adopt small capacitances to substitute bulky capacitor, thus significantly improving electric capacity DAC to set up the time.MSB is directly compared through comparator CMP1 by input differential signal and obtains, and according to highest order code, SAR logic controls highest order electric capacity C3 and C8 simultaneously, and then C3 and C8 starts simultaneously at foundation, and after C3 sets up, C8, due to relatively big, also sets up continuing.Now comparator carries out second time judgement, and according to second output code, SAR logic controls C2 and C7 conversion simultaneously, and after C2 completes conversion, C7, due to relatively big, is also continuing foundation.Repeat said process, until C0 and C5 starts simultaneously at foundation, it is necessary to assure C1 and C5 completes conversion within a clock cycle.Can be seen that in the transformation process of whole small capacitances, bulky capacitor can continue to set up, until in 5 thick quantizing processs, last electric capacity C0 converts.Therefore C8 can time of changing into 4T, C7 can time of changing into 3T, C6 can time of changing into 2T, C5 can time of changing be T.After 5 thick has quantified, it is 10 SAR logics that SAR controls logical transition, and during this period, electric capacity C4 completes to change, and circuit starts to change remaining low level code according to normal 10 SARADC.Each assuming traditional binary system SARADC changes the time into Tcon, then each conversion time is at least big than highest order electric capacity C8 sets up the time, i.e. Tcon > 4T, so each conversion time of the present invention improves more than 4 times.The DAC array that the present invention adopts is based on the merging capacitance structure of Terminal Capacitance multiplexing, improves power efficiency, and the digital circuit power consumption increased is smaller, therefore the overall power of circuit is also relatively small.
Accordingly, Fig. 4 is SAR logic register group in successive approximation analog to digital C, including two Parasites Fauna, and the SAR logic register group REG2 of one 5 SAR logic register group REG1 and 10.The process that from 5 bit resolutions, SAR logic is become 10 bit resolutions is described in further detail by accompanying drawing 4.Time initial, the equal zero setting of REG1 and REG2, in conjunction with 3,5 thick quantization stages of ADC of accompanying drawing, enable control signal and control the SAR logic that REG1 is as 5, quantify to obtain 5 output codes successively by small capacitances DAC array, being designated as B4～B0, comparator often exports one digit number character code, and corresponding digital code controls the analog switch of corresponding capacitor array, thus complete the conversion (also completing the conversion of C8～C5) of electric capacity C3～C0 simultaneously, and write the result in corresponding high 5 of REG2.After 5 ADC have quantified, in 10 SAR logics, high 5 also obtain accordingly, are B4～B0.Hereafter, through SAR logistic transformation, namely slightly quantify end mark signal control REG1 and quit work, REG1 zeros data simultaneously, and REG2 proceeds by as 10 SAR logics and compares judgement.Owing to high 5 bit data obtain, now it is designated as D9～D5, only need to complete the conversion of low 5 bit data, be designated as D4～D0, thus being rapidly completed 10 bit data conversions.
To sum up, the embodiment of the present invention by the successive approximation analog to digital C-structure of single-pass is improved, as: improve DAC structure, improve DAC set up speed；Redesign quick comparator, improve the comparator decision time；Optimize Digital Logical Circuits, reduce logical delay etc., it is possible to so that successive approximation analog to digital C is intermediate resolution (10), reach relatively high conversion rate (more than hundred megahertzs).And by the small capacitances array of 5 quantify to come in absolute 10 DAC capacitor arrays high 5, it is possible to ensure on the basis that low-power consumption is relatively low, improve the conversion speed of successive approximation analog to digital C.
The Approach by inchmeal adc circuit of the high-speed transitions above embodiment of the present invention provided is described in detail, principles of the invention and embodiment are set forth by specific case used herein, and the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, all will change in specific embodiments and applications, in sum, this specification content should not be construed as limitation of the present invention.
Claims (7)
1. the Approach by inchmeal adc circuit of a high-speed transitions, it is characterized in that, including: the first electric capacity conversion array, the second electric capacity conversion array, the first comparator, the second comparator, SAR control logic, differential signal input, the first bootstrapped switch and the second bootstrapped switch, wherein:
Described differential signal input is linked on the first bootstrapped switch and bootstrapped switch parallel, and controls the switch of logic control the first bootstrapped switch and the second bootstrapped switch based on SAR, completes input differential signal sampling；
Described first electric capacity conversion array and described second electric capacity conversion array include multiple electric capacity, the top crown of the plurality of electric capacity links together, bottom crown selects switch to may be connected to multiple input each via a multi-channel analog, and described first electric capacity conversion array and the second electric capacity conversion array have different bit resolution；
The upper step of described first electric capacity conversion array and the first bootstrapped switch connect, and are linked into the first comparator；
The upper step of described second electric capacity conversion array and the second bootstrapped switch connect, and are linked into the second comparator；
Both end voltage size on the electric capacity conversion array each accessed is compared by described first comparator and the second comparator, and comparative result output to SAR controls logic, and controlled SAR controls logic and completes the conversion of different bit resolution；
SAR controls logic for controlling multidiameter option switch in described first electric capacity conversion array and described second electric capacity conversion array and the switch of bootstrapped switch that described differential signal input is connected to, complete input signal sampling, and the output result according to described first comparator and the second comparator, gradually complete the analogue signal conversion to digital signal, output digital code, and control the conversion of different bit resolution.
2. the Approach by inchmeal adc circuit of high-speed transitions as claimed in claim 1, it is characterised in that described first electric capacity conversion array is the electric capacity conversion array of 5 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing；Second electric capacity conversion array is the electric capacity conversion array of 10 bit resolutions, based on the merging DAC capacitor array of Terminal Capacitance multiplexing.
3. the Approach by inchmeal adc circuit of high-speed transitions as claimed in claim 2, it is characterised in that the capacitance ratio in described first electric capacity conversion array is 4:2:1:1；Capacitance ratio in described second electric capacity conversion array is 128:64:32:16:8:4:2:1:1.
4. the Approach by inchmeal adc circuit of high-speed transitions as claimed in claim 2, it is characterised in that described first comparator is low power consumption comparator.
5. the Approach by inchmeal adc circuit of high-speed transitions as claimed in claim 2, it is characterised in that described second comparator is low noise comparator.
6. the Approach by inchmeal adc circuit of the high-speed transitions as described in any one of claim 1 to 5, it is characterised in that the plurality of input includes ADC reference voltage, common-mode voltage and reference ground.
7. the Approach by inchmeal adc circuit of high-speed transitions as claimed in claim 6, it is characterised in that described common-mode voltage is the half of reference voltage.
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Cited By (12)
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| CN109802679A (en) * | 2018-12-05 | 2019-05-24 | 西安电子科技大学 | A kind of super low-power consumption gradually-appoximant analog-digital converter based on supply voltage |
| CN109905128A (en) * | 2019-03-15 | 2019-06-18 | 上海胤祺集成电路有限公司 | A kind of adaptive high speed SAR-ADC conversion time full utilization circuit and method |
| CN110429937A (en) * | 2019-07-16 | 2019-11-08 | 东南大学 | It is a kind of for improving the realization circuit and method of SAR-ISDM mixed structure ADC sample rate |
| CN110880937A (en) * | 2019-12-24 | 2020-03-13 | 中山大学 | N bit analog-to-digital converter based on gradual approximation architecture |
| CN111404549A (en) * | 2020-04-07 | 2020-07-10 | 芯海科技（深圳）股份有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
| CN111435837A (en) * | 2019-01-11 | 2020-07-21 | 瑞昱半导体股份有限公司 | Analog to digital conversion device |
| CN111756380A (en) * | 2020-06-23 | 2020-10-09 | 复旦大学 | A two-step successive approximation analog-to-digital converter with a shared bridge capacitor array |
| CN111865319A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | An ultra-low power successive approximation analog-to-digital converter based on a four-input comparator |
| CN112367084A (en) * | 2020-11-23 | 2021-02-12 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing |
| CN116208154A (en) * | 2023-05-06 | 2023-06-02 | 南京航空航天大学 | Bit weight detection and calibration method for pipeline successive approximation type ADC |
| CN119070824A (en) * | 2024-11-07 | 2024-12-03 | 湖南大学 | Successive approximation ADC, chip and analog-to-digital conversion method based on common mode voltage |
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| CN109802679A (en) * | 2018-12-05 | 2019-05-24 | 西安电子科技大学 | A kind of super low-power consumption gradually-appoximant analog-digital converter based on supply voltage |
| CN109802679B (en) * | 2018-12-05 | 2021-01-05 | 西安电子科技大学 | An ultra-low power successive approximation analog-to-digital converter based on supply voltage |
| CN111435837B (en) * | 2019-01-11 | 2023-01-31 | 瑞昱半导体股份有限公司 | Analog to Digital Converter |
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| CN109905128A (en) * | 2019-03-15 | 2019-06-18 | 上海胤祺集成电路有限公司 | A kind of adaptive high speed SAR-ADC conversion time full utilization circuit and method |
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| CN110429937B (en) * | 2019-07-16 | 2023-02-21 | 东南大学 | Realization circuit and method for improving SAR-ISDM mixed structure ADC sampling rate |
| CN110880937A (en) * | 2019-12-24 | 2020-03-13 | 中山大学 | N bit analog-to-digital converter based on gradual approximation architecture |
| CN110880937B (en) * | 2019-12-24 | 2024-04-12 | 中山大学 | n-bit analog-to-digital converter based on asymptotic approximation architecture |
| CN111404549A (en) * | 2020-04-07 | 2020-07-10 | 芯海科技（深圳）股份有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
| CN111756380A (en) * | 2020-06-23 | 2020-10-09 | 复旦大学 | A two-step successive approximation analog-to-digital converter with a shared bridge capacitor array |
| CN111865319A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | An ultra-low power successive approximation analog-to-digital converter based on a four-input comparator |
| CN112367084A (en) * | 2020-11-23 | 2021-02-12 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing |
| CN112367084B (en) * | 2020-11-23 | 2023-04-18 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing |
| CN116208154A (en) * | 2023-05-06 | 2023-06-02 | 南京航空航天大学 | Bit weight detection and calibration method for pipeline successive approximation type ADC |
| CN116208154B (en) * | 2023-05-06 | 2023-07-07 | 南京航空航天大学 | A Bit Weight Detection and Calibration Method of Pipeline Successive Approximation ADC |
| CN119070824A (en) * | 2024-11-07 | 2024-12-03 | 湖南大学 | Successive approximation ADC, chip and analog-to-digital conversion method based on common mode voltage |
| CN119543944A (en) * | 2025-01-23 | 2025-02-28 | 灿芯半导体(上海)股份有限公司 | A high-speed synchronous SAR ADC switching circuit |
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