CN105717966A - Reference voltage generating circuit and method, and integrated circuit - Google Patents

Abstract

The invention discloses a reference voltage generating circuit. The reference voltage generating circuit receives a constant input voltage, and comprises an operational amplifier output circuit and a voltage adjustment circuit, wherein the voltage adjustment circuit adjusts the input voltage of a first input end of the operational amplifier output circuit; the operational amplifier output circuit outputs a constant voltage according to the adjusted input voltage of the first input end and the input voltage of a second input end of the operational amplifier output circuit. The invention further discloses an integrated circuit and a reference voltage generating method.

Description

Reference voltage generating circuit, method and integrated circuit

Technical Field

The present invention relates to reference voltage technology, and in particular, to a reference voltage generating circuit, a method and an integrated circuit.

Background

The reference voltage generating circuit, which may also be referred to as a reference voltage generating circuit, generally refers to a highly stable voltage source used as a reference voltage in a circuit. With the increasing scale of integrated circuits, especially the development of System On Chip (SOC) technology, the reference voltage generating circuit has become an indispensable basic circuit module in large-scale, very large-scale integrated circuits and almost all digital analog systems.

Reference voltages are often used as references for system measurements and calibration in both precision measurement instruments and widely used digital communication systems. Therefore, the reference voltage generating circuit plays an important role in the analog integrated circuit, and directly influences the performance and precision of the electronic system.

An ideal reference voltage generating circuit should be independent of power supply and temperature, and provide a stable voltage in the circuit, and the term "reference" is used to indicate that the value of the reference voltage source should have higher precision and stability than the value of a general power supply.

Disclosure of Invention

The embodiment of the invention provides a reference voltage generating circuit, a reference voltage generating method and an integrated circuit.

An embodiment of the present invention provides a reference voltage generation circuit configured to receive a constant input voltage, including: an operational amplifier output circuit and a voltage adjusting circuit; wherein,

the voltage adjusting circuit is configured to adjust an input voltage of a first input terminal of the operational amplifier output circuit;

the operational amplifier output circuit is configured to output a constant voltage according to the adjusted input voltage of the first input terminal and the adjusted input voltage of the second input terminal of the operational amplifier output circuit.

An embodiment of the present invention further provides an integrated circuit, including a reference voltage generation circuit configured to receive a constant input voltage, the reference voltage generation circuit including: an operational amplifier output circuit and a voltage adjusting circuit; wherein,

the voltage adjusting circuit is configured to adjust an input voltage of a first input terminal of the operational amplifier output circuit;

the operational amplifier output circuit is configured to output a constant voltage according to the adjusted input voltage of the first input terminal and the adjusted input voltage of the second input terminal of the operational amplifier output circuit.

The embodiment of the invention also provides a reference voltage generating method, wherein the reference voltage generating circuit receives constant input voltage; the method further comprises the following steps:

the voltage adjusting circuit of the reference voltage generating circuit adjusts the input voltage of the first input end of the operational amplifier output circuit of the reference voltage generating circuit;

and the operational amplifier output circuit outputs constant voltage according to the adjusted input voltage of the first input end and the adjusted input voltage of the second input end.

The embodiment of the invention also provides a reference voltage generation method, which comprises the following steps:

the reference voltage generating circuit receives a constant input voltage;

the reference voltage generating circuit outputs a constant voltage; wherein,

the value of the output voltage is entirely determined by the input voltage.

According to the reference voltage generating circuit, the reference voltage generating method and the integrated circuit provided by the embodiment of the invention, the reference voltage generating circuit receives constant input voltage, the voltage adjusting circuit adjusts the input voltage of the first input end of the operational amplifier output circuit, and the operational amplifier output circuit outputs constant voltage according to the adjusted input voltage of the first input end and the adjusted input voltage of the second input end of the operational amplifier output circuit; therefore, the stability and the precision of the reference voltage generated by the reference voltage generating circuit can be improved, and the influence of process deviation or temperature on the reference voltage can be eliminated.

Drawings

FIG. 1 is a schematic diagram of a reference voltage generating circuit;

FIG. 2 is a schematic diagram of a first reference voltage generating circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a second reference voltage generating circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a reference voltage generating circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a reference voltage generating circuit according to a second embodiment of the present invention;

FIG. 6 is a schematic diagram of a three-reference voltage generating circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a four reference voltage generating circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a five-reference voltage generating circuit according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a six-reference voltage generating circuit according to an embodiment of the present invention;

fig. 10A is a schematic structural diagram of a first dc level converting circuit according to an embodiment of the present invention;

fig. 10B is a schematic diagram of a second dc level shift circuit according to the embodiment of the invention;

FIG. 11A is a graph showing the variation of the compensation voltage with the number of sampling times using the reference voltage generating circuit shown in FIG. 1;

fig. 11B is a diagram of the variation of the compensation voltage with the sampling times of the reference voltage generating circuit according to the first embodiment of the present invention.

Detailed Description

Fig. 1 is a schematic diagram of a reference voltage generating circuit, which generates a reference voltage not having a constant voltage value but having a very variable voltage value, under the influence of circuit technology and temperature. The reason why the generated reference voltage is not constant is analyzed as follows:

in the reference voltage generating circuit shown in FIG. 1, V of the first P-channel metal oxide semiconductor field effect transistor (PMOS) MP1 and the second PMOSMP2_gsSimilarly, V of the first transistor Q1 and the second transistor Q2_beSimilarly, the ratio of the resistance values of the first resistor R1 and the second resistor R2 is 1: N; wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer. For convenience of description, the voltage at the input terminal to which the gate of the second PMOSMP2 is connected is referred to as V_inThe voltage at the junction formed by the first transistor Q1 and the first resistor R1 is referred to as V₂The voltage at the non-inverting input of the operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the operational amplifier A0 is referred to as V_INAn operational amplifierThe voltage output by A0 is called V_ref。

In the reference voltage generating circuit shown in fig. 1, the following relationship exists:

V₂＝V_gs-V_be＝ΔV(1)

V_IP＝V_IN(2)

V_IP＝V_in+(V_gs-V_be)(3)

V_ref-V_IN＝N(V_IN-V₂)(4)

combining and replacing the formulas (1) to (4) to obtain:

V_ref＝(N+1)V_in+ΔV＝(N+1)V_in+(V_gs-V_be)(5)

when V is_inWhen 0, then there are:

V_ref＝V_gs-V_be(6)

from equation (6), the voltage V output by the operational amplifier A0_refIs and V_gsAnd V_beClosely related, in particular: when V is_inWhen equal to 0, V_ref＝V_gs-V_beVoltage V output from operational amplifier a0_refIs totally composed of V_gsAnd V_beAnd (4) determining. In the ideal case, V_refShould be a constant value, however, due to circuit technology and temperature, V_gsAnd V_beIs subject to change, and V_gsAnd V_beIs not uniform, thus resulting in V_refNot a constant value but a varying value, which will substantially reduce the reference voltage V_refStability and accuracy of the method. Wherein, V_gsAnd V_beThe inconsistent variation trend of (a) means that: v_gsAnd V_beThe variation at the same time is different, for example, assume thatAt a first moment V_gsCalculating V as a reference_gsAt other times, by V at the first time_beCalculating V as a reference_beThe amount of change at other times, and assume V_gsThe variation at the second time is Δ 1, V_beIf the variation at the second time is Δ 2, then Δ 1 is not equal to Δ 2, so according to equation (6), V at the first time is resulted_refV from the second moment_refDifferent; here, Δ 1 may be a positive number, a negative number, or zero; accordingly, Δ 2 may be a positive number, a negative number, or zero.

Based on this, in the following various embodiments of the invention: when the input voltage of the reference voltage generating circuit is constant, the voltage output by the operational amplifier output circuit is kept constant, and the value of the output voltage is completely determined by the input voltage.

The invention is described in further detail below with reference to the figures and the embodiments.

It should be noted that the first and second terms used herein only indicate elements at different positions, and do not limit parameters or functions of the elements.

The reference voltage generating circuit provided by the embodiment of the invention receives constant input voltage; as shown in fig. 2, the reference voltage generating circuit includes: a voltage regulator circuit 21 and an operational amplifier output circuit 22; wherein,

the voltage adjustment circuit 21 keeps the voltage output from the operational amplifier output circuit 22 constant.

Here, in practical applications, the keeping of the voltage output by the operational amplifier output circuit 22 constant means that: in practical use, the voltage output by the operational amplifier output circuit 22 varies within an allowable variation range in circuit design. Wherein, the allowable variation range refers to: the range of variation of the voltage output by the operational amplifier output circuit 22 meets the use requirements.

Specifically, the voltage adjusting circuit 21 adjusts the input voltage of the first input terminal of the operational amplifier output circuit 22, and the operational amplifier output circuit 22 outputs a constant voltage based on the adjusted input voltage of the first input terminal and the input voltage of the second input terminal of the operational amplifier output circuit 22.

In one embodiment, as shown in fig. 3, the reference voltage generating circuit further includes: a first direct current level shift (DCshift) circuit 31 and a second direct current level shift circuit 32; wherein,

in the process of outputting the voltage by the operational amplifier output circuit 22, the first dc level conversion circuit 31 performs a first displacement on the voltage inputted thereto and outputs the voltage to the first input terminal of the operational amplifier output circuit 22, and the second dc level conversion circuit 32 performs a second displacement on the voltage inputted thereto and outputs the voltage to the second input terminal of the operational amplifier output circuit 22, so that the transistor of the first operational amplifier output stage in the operational amplifier output circuit 22 operates in a non-linear region to ensure the fidelity of the output signal; when the operational amplifier output circuit 22 outputs a voltage and the first input terminal of the operational amplifier output circuit 22 corresponds to the non-inverting input terminal of the first operational amplifier in the operational amplifier output circuit 22, the voltage adjusting circuit 21 adjusts the input voltage of the first dc level converting circuit 31, so as to adjust the input voltage of the first input terminal of the operational amplifier output circuit 22, and the operational amplifier output circuit 22 outputs a constant voltage according to the adjusted input voltage of the first input terminal and the adjusted input voltage of the second input terminal. Here, in practical applications, the first displacement may be equal to the second displacement, and the first displacement may not be equal to the second displacement.

By adjusting the input voltage of the first dc level shift circuit 31, specifically, the voltage adjustment circuit 21 divides the input voltage of the first input terminal of the operational amplifier output circuit 22 and feeds the divided voltage back to the first dc level shift circuit 31, the influence of the process deviation and temperature of the devices in the first dc level shift circuit 31 and the second dc level shift circuit 32 on the output voltage of the operational amplifier output circuit 22 is eliminated, so that the voltage output by the operational amplifier output circuit 22 is kept constant.

Here, the main factor for eliminating the influence of the process deviation and the temperature of the components in the first dc level conversion circuit 31 on the input voltage of the first input end is that when the field effect transistor and the transistor in the first dc level conversion circuit 31 are influenced by the process deviation and the temperature, the input voltage of the first input end of the operational amplifier output circuit 22 is not influenced by the change of the bias voltages of the field effect transistor and the transistor in the first dc level conversion circuit 31, and further the reference voltage is not influenced.

In an embodiment, when the operational amplifier output circuit 22 outputs a voltage and the first input terminal of the operational amplifier output circuit 22 corresponds to the inverting input terminal of the first operational amplifier in the operational amplifier output circuit 22, the voltage adjusting circuit 21 divides the input voltage of the first input terminal of the operational amplifier output circuit 22, so as to eliminate the influence of the process variation and the temperature of the devices in the first dc level converting circuit 31 and the second dc level converting circuit 32 on the output voltage of the operational amplifier output circuit 22, thereby keeping the voltage output by the operational amplifier output circuit 22 constant.

Example one

In the present embodiment, as shown in fig. 4, the first dc level converting circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: the third resistor R3 and the fourth resistor R4, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: n: 1; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

In the reference voltage generating circuit shown in FIG. 4, V of the first PMOSMP1 and the second PMOSMP2_gsThe same, the first triodeV of Q1 and Q2 of second triode_beSimilarly, in practical applications, both the first transistor Q1 and the second transistor Q2 may be NPN transistors. Wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer.

The operating principle of the reference voltage generating circuit shown in fig. 4 is:

for convenience of description, in the following description, the input voltage of the reference voltage generating circuit is referred to as V_RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oThe input voltage of the second DC level shifter 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe voltage at the junction formed by the first PMOSMP1, the third resistor R3 and the fourth resistor R4 is referred to as V₁The voltage at the junction formed by the first transistor Q1, the third resistor R3, and the first resistor R1 is referred to as V₂The voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+V_gs-V_be(7)

V_1in＝V₁(8)

V_1o＝V₂(9)

V₂＝(N+1)V₁(10)

ΔV＝V_gs-V_be(11)

by combining and replacing equations (7) to (11), the following results can be obtained:

$V_2=(1+\frac{1}{N})\mathrm{\ΔV}---\left(12\right)$

the reference voltage generation circuit shown in fig. 4 also has the following relationship:

V_ref＝(N+1)V_IN-NV₂(13)

V_IP＝V_IN(14)

V_IP＝V_2o(15)

V_2o＝V_2in+V_gs-V_be(16)

V_2in＝V_RGin(17)

combining and replacing the equations (11) to (17) to obtain:

$V_{\mathrm{ref}}=(N+1)V_{\mathrm{RGin}}+(N+1)\mathrm{\ΔV}-N(1+\frac{1}{N})\mathrm{\ΔV}$

V_ref＝(N+1)V_RGin(18)

as can be seen from equation (18), the voltage V output from the first operational amplifier a0_refI.e. the magnitude of the voltage output by the operational amplifier output circuit 22, and the input voltage V of the reference voltage generating circuit_RGinAnd the size of N; at the time of circuit determination, the magnitude of the voltage outputted from the operational amplifier output circuit 22 is only equal to the input voltage V of the reference voltage generating circuit_RGinIs independent of the gate-source voltages of the first and second PMOSMP1, 2 and the voltages between the base and emitter of the first and second transistors Q1, Q2, in other words, by adjusting the input voltage of the first dc level shifter 31, the influence of the device parameters of the first and second dc level shifters 31, 32, i.e. the transistor parameters, on the output voltage of the operational amplifier output circuit 22 is eliminated, namely: the influence of the circuit process technology and temperature on the output voltage of the operational amplifier output circuit 22 is eliminated, and when the circuit is determined, the output voltage of the operational amplifier output circuit 22 is only related to the input voltage of the reference voltage generating circuit, so that the output voltage of the operational amplifier output circuit 22 is kept constant; and, when the input voltage V of the reference voltage generating circuit_RGinWhen zero, the output voltage V of the operational amplifier output circuit 22_refAlso zero.

Example two

In the present embodiment, as shown in fig. 5, the first dc level converting circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: the third resistor R3, the fourth resistor R4 and the first reference current source I1, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: n: 1; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

In the reference voltage generating circuit shown in FIG. 5, V of the first PMOSMP1 and the second PMOSMP2_gsSimilarly, V of the first transistor Q1 and the second transistor Q2_beSimilarly, in practical applications, both the first transistor Q1 and the second transistor Q2 may be NPN transistors. Wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer.

The operating principle of the reference voltage generating circuit shown in fig. 5 is:

for convenience of description, in the following description, the input voltage of the reference voltage generating circuit is referred to as V_RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oThe input voltage of the second DC level shifter 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe voltage at the junction formed by the first PMOSMP1, the third resistor R3 and the fourth resistor R4 is referred to as V₁The voltage at the junction formed by the first transistor Q1, the third resistor R3, and the first resistor R1 is referred to as V₂The current of the first reference current source is called I₁The fourth resistor R4 has a resistance R, and the voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+V_gs-V_be(7)

V_1in＝V₁(8)

V_1o＝V₂(9)

ΔV＝V_gs-V_be(11)

V₂＝(N+1)V₁+NI₁R(19)

by combining and replacing the equations (7) to (9), the equation (11) and the equation (19), the following results can be obtained:

$V_2=(1+\frac{1}{N})\mathrm{\ΔV}-I_{1}R---\left(20\right)$

the reference voltage generation circuit shown in fig. 5 also has the following relationship:

V_ref＝(N+1)V_IN-NV₂(13)

V_IP＝V_IN(14)

V_IP＝V_2o(15)

V_2o＝V_2in+V_gs-V_be(16)

V_2in＝V_RGin(17)

by combining and replacing the formula (11), the formula (13) to the formula (17) and the formula (20), the following results can be obtained:

$V_{\mathrm{ref}}=(N+1)V_{\mathrm{RGin}}+(N+1)\mathrm{\ΔV}-N(1+\frac{1}{N})\mathrm{\ΔV}+{\mathrm{NI}}_{1}R$

V_ref＝(N+1)V_RGin+NI₁R(21)

as can be seen from equation (21), the voltage V output from the first operational amplifier a0_refI.e. the magnitude of the voltage output by the operational amplifier output circuit 22, and the input voltage V of the reference voltage generating circuit_RGinCurrent I of the first reference current source₁The resistance values R and N of the fourth resistor R4 are related; the output voltage of the operational amplifier output circuit 22 is only equal to the input voltage V at the time of circuit determination_RGinMagnitude of (1), current I of the first reference current source₁And the resistance R of the fourth resistor R4 is related to the gate-source voltage of the first pmos mp1 and the second pmos mp2, and the voltage between the base and the emitter of the first transistor Q1 and the second transistor Q2, in other words, by adjusting the input voltage of the first dc level shifter 31, the influence of the device parameters of the first dc level shifter 31 and the second dc level shifter 32, i.e. the transistor parameters, on the output voltage of the operational amplifier output circuit 22 is eliminated, that is: the influence of the circuit process technology and temperature on the output voltage of the operational amplifier output circuit 22 is eliminated, and when the circuit is determined, the output voltage of the operational amplifier output circuit 22 is only related to the input voltage of the reference voltage generating circuit, the current of the first reference current source I1 and the resistance value of the fourth resistor R4, so that the output voltage of the operational amplifier output circuit 22 is kept constant; and, when the input voltage V of the reference voltage generating circuit_RGinWhen zero, the output voltage V of the operational amplifier output circuit 22_refIs NI₁R, so that the catalyst can be used according to the requirementsThe current of the first reference current source I1 connected between the input end of the first direct-current level conversion circuit 31 and the ground is adjusted, so that the required output voltage is accurately obtained, the user requirement is met, and the user experience is improved.

EXAMPLE III

In the present embodiment, as shown in fig. 6, the first dc level converting circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: a third resistor R3, a fourth resistor R4, and a second reference current source I2, wherein the ratio of the resistances of the third resistor R3 to the fourth resistor R4 is: n: 1; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

In the reference voltage generating circuit shown in FIG. 6, V of the first PMOSMP1 and the second PMOSMP2_gsSimilarly, V of the first transistor Q1 and the second transistor Q2_beSimilarly, in practical applications, both the first transistor Q1 and the second transistor Q2 may be NPN transistors. Wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer.

The operating principle of the reference voltage generating circuit shown in fig. 6 is:

for convenience of description, in the following description, the input voltage of the reference voltage generating circuit is referred to as V_RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oThe input voltage of the second DC level shifter 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe voltage at the junction formed by the first PMOSMP1, the third resistor R3 and the fourth resistor R4 is referred to as V₁The voltage at the junction formed by the first transistor Q1, the third resistor R3, and the first resistor R1 is referred to as V₂The current of the second reference current source is called I₂The fourth resistor R4 has a resistance R, and the voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+V_gs-V_be(7)

V_1in＝V₁(8)

V_1o＝V₂(9)

ΔV＝V_gs-V_be(11)

V₂＝(N+1)V₁-NI₂R(22)

combining and replacing the formulas (7) to (9), the formula (11) and the formula (22) to obtain:

$V_2=(1+\frac{1}{N})\mathrm{\ΔV}+I_{2}R---\left(23\right)$

the reference voltage generation circuit shown in fig. 6 also has the following relationship:

V_ref＝(N+1)V_IN-NV₂(13)

V_IP＝V_IN(14)

V_IP＝V_2o(15)

V_2o＝V_2in+V_gs-V_be(16)

V_2in＝V_RGin(17)

by combining and replacing the formula (11), the formula (13) to the formula (17) and the formula (23), the following results can be obtained:

$V_{\mathrm{ref}}=(N+1)V_{\mathrm{RGin}}+(N+1)\mathrm{\ΔV}-N(1+\frac{1}{N})\mathrm{\ΔV}-{\mathrm{NI}}_{2}R$

V_ref＝(N+1)V_RGin-NI₂R(24)

as can be seen from equation (24), the voltage V output from the first operational amplifier a0_refI.e. the magnitude of the voltage output by the operational amplifier output circuit 22, and the input voltage V of the reference voltage generating circuit_RGinCurrent I of the second reference current source₂The resistance values R and N of the fourth resistor R4 are related; the output voltage of the operational amplifier output circuit 22 is only equal to the input voltage V at the time of circuit determination_RGinMagnitude of (1), current I of the second reference current source₂And a fourth resistor R4The resistance R is related to the gate-source voltages of the first PMOSMP1 and the second PMOSMP2, and the voltages between the base and the emitter of the first transistor Q1 and the second transistor Q2, in other words, by adjusting the input voltage of the first dc level converting circuit 31, the influence of the device parameters of the first dc level converting circuit 31 and the second dc level converting circuit 32, i.e. the transistor parameters, on the output voltage of the operational amplifier output circuit 22 is eliminated, that is: the influence of the circuit process technology and temperature on the output voltage of the operational amplifier output circuit 22 is eliminated, and when the circuit is determined, the output voltage of the operational amplifier output circuit 22 is only related to the input voltage of the reference voltage generating circuit, the current of the second reference current source I2 and the resistance value of the fourth resistor R4, so that the output voltage of the operational amplifier output circuit 22 is kept constant; and, when the input voltage V of the reference voltage generating circuit_RGinWhen zero, the output voltage V of the operational amplifier output circuit 22_refis-NI₂R, just so, just can be as required, through the adjustment connection at the input of first direct current level shift circuit 31 and the current of the second reference current source I2 between the power supply, obtain the size of required output voltage accurately to satisfy user's demand, promote user experience.

It should be noted that: the difference between the reference voltage generation circuit of the second embodiment and the reference voltage generation circuit of the third embodiment is that: the reference voltage generating circuit of the second embodiment can obtain the reference voltage larger than N +1 times of the input voltage, and the reference voltage generating circuit of the third embodiment can obtain the reference voltage smaller than N +1 times of the input voltage. In practical application, a user may determine to use the reference voltage generating circuit of the second embodiment or the reference voltage generating circuit of the third embodiment as needed.

In the first to third embodiments, the first dc level shift circuit 31 performs the first displacement on the voltage inputted thereto equal to the second dc level shift circuit 32 performs the second displacement on the voltage inputted thereto.

Example four

In the present embodiment, as shown in fig. 7, the first dc level converting circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: the third resistor R3 and the fourth resistor R4, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: a: 1; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

Here, A, N is generally a positive integer in practical use.

The operating principle of the reference voltage generating circuit shown in fig. 7 is:

for convenience of description, in the following description, the input voltage of the reference voltage generating circuit is referred to as V_RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oThe first displacement of the first dc level conversion circuit 31 is referred to as Δ V₁The input voltage of the second DC level shifter 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe second displacement of the second dc level shift circuit 32 is referred to as Δ V₂The voltage at the junction formed by the first PMOSMP1, the third resistor R3 and the fourth resistor R4 is referred to as V₁The voltage at the junction formed by the first transistor Q1, the third resistor R3, and the first resistor R1 is referred to as V₂The voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+ΔV₁(25)

V_1in＝V₁(8)

V_1o＝V₂(9)

V₂＝(A+1)V₁(26)

combining and replacing the above formulas to obtain:

$V_2=(1+\frac{1}{A}){\mathrm{\ΔV}}_1---\left(27\right)$

the reference voltage generation circuit shown in fig. 7 also has the following relationship:

V_ref＝(N+1)V_IN-NV₂(13)

V_IP＝V_IN(14)

V_IP＝V_2o(15)

V_2o＝V_2in+ΔV₂(28)

V_2in＝V_RGin(17)

by combining and replacing equations (11) to (15), equation (27) and equation (28), the following results can be obtained:

$V_{\mathrm{ref}}=(N+1)V_{\mathrm{RGin}}+(N+1){\mathrm{\ΔV}}_2-N(1+\frac{1}{A}){\mathrm{\ΔV}}_1---\left(29\right)$

from equation (29), it can be seen that the voltage V when the first operational amplifier A0 outputs_refI.e., when the voltage output by the operational amplifier output circuit 22 is constant, i.e., when the voltage V output by the first operational amplifier a0 is constant_refWith the input voltage V of the reference voltage generating circuit_RGinThe sizes of N and A are related; at the time of circuit determination, the magnitude of the voltage outputted from the operational amplifier output circuit 22 is only equal to the input voltage V of the reference voltage generating circuit_RGinIs required to satisfy the requirements of the first and second PMOSMP1, 2, the first and second transistors Q1, Q2, and the voltage between the base and emitterThen the method is finished; that is, when the circuit is determined, and Δ V₁≠ΔV₂When it is satisfiedThat is, the voltage V output by the first operational amplifier A0 can be realized_refIs only equal to the input voltage V of the reference voltage generating circuit_RGinIs related to the size of (a).

Here, it should be noted that: the structure of the reference voltage generating circuit provided in this embodiment is the same as that of the reference voltage generating circuit provided in the first embodiment, except that: in this embodiment, the first displacement is not equal to the second displacement, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: a: 1; in the first embodiment, the first displacement is equal to the second displacement, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: 1: N.

EXAMPLE five

In this embodiment, as shown in fig. 8, the first dc level shift circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: the third resistor R3 and the fourth resistor R4, and the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: 1: N; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

In the reference voltage generating circuit shown in FIG. 8, V of the first PMOSMP1 and the second PMOSMP2_gsSimilarly, V of the first transistor Q1 and the second transistor Q2_beSimilarly, in practical applications, both the first transistor Q1 and the second transistor Q2 may be NPN transistors. Wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer.

The operating principle of the reference voltage generating circuit shown in fig. 8 is:

for convenience of description, in the following description, the first input voltage of the reference voltage generating circuit is referred to as V_1RGinThe second input voltage of the reference voltage generating circuit is referred to as V_2RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oApplying a second direct currentThe input voltage of the flat-converting circuit 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe voltage at the junction formed by the third resistor R3, the fourth resistor R4, and the non-inverting input of the first operational amplifier A0 is referred to as V₁The voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+V_gs-V_be(7)

V_1in＝V_1RGin(30)

$V_{1o}=(1+\frac{1}{N})V_1---\left(31\right)$

ΔV＝V_gs-V_be(11)

combining, replacing and the like the formula (7), the formula (11), the formula (30) and the formula (31), then it can be obtained:

$V_1=\frac{N}{N+1}\mathrm{\ΔV}+\frac{N}{N+1}{V}_{1\mathrm{RGin}}---\left(32\right)$

the reference voltage generation circuit shown in fig. 8 also has the following relationship:

V_ref＝(N+1)V_IN-NV_2o(33)

V_IP＝V_IN(14)

V_2o＝V_2in+V_gs-V_be(16)

V_2in＝V_2RGin(34)

V_IP＝V₁(35)

by combining and replacing the formula (11), the formula (14), the formula (16), and the formulas (32) to (35), the following results are obtained:

$V_{\mathrm{ref}}=-N{V}_{2\mathrm{RGin}}+(N+1)\frac{N}{N+1}{V}_{1\mathrm{RGin}}+(N+1)\frac{N}{N+1}\mathrm{\ΔV}-\mathrm{N\ΔV}$

V_ref＝-NV_2RGin+NV_1RGin(36)

as can be seen from equation (36), the voltage V output from the first operational amplifier a0_refI.e. the magnitude of the voltage output by the operational amplifier output circuit 22, and the first input voltage V of the quasi-voltage generating circuit_1RGinA second input voltage V_2RGinAnd the size of N; the output voltage of the operational amplifier output circuit 22 is only equal to the first input voltage V of the reference voltage generation circuit at the time of circuit determination_1RGinAnd a second input voltage V_2RGinIs independent of the gate-source voltages of the first and second PMOSMP1, 2 and the voltages between the base and emitter of the first and second transistors Q1, Q2, in other words, by adjusting the input voltage at the non-inverting input of the first operational amplifier a0, the influence of the device parameters of the first and second dc level converting circuits 31, 32, i.e. the transistor parameters, on the output voltage of the operational amplifier output circuit 22 is eliminated, i.e.: the influence of the circuit process technology and temperature on the output voltage of the operational amplifier output circuit 22 is eliminated, and when the circuit is determined, the output voltage of the operational amplifier output circuit 22 is only related to the input voltage of the reference voltage generating circuit, so that the output voltage of the operational amplifier output circuit 22 is kept constant; and, when the first input voltage V of the reference voltage generating circuit_1RGinAnd a second input voltage V_2RGinWhen both are zero, the output voltage V of the operational amplifier output circuit 22_refAlso zero.

In the reference voltage generating circuit provided in this embodiment, the first displacement of the voltage input to the first dc level converting circuit 31 is equal to the second displacement of the voltage input to the second dc level converting circuit 32.

In practice, the first displacement may not be equal to the second displacement, in which caseHereinafter, it is assumed that the first displacement of the first dc level conversion circuit 31 is referred to as Δ V₁The input voltage of the second DC level shifter 32 is referred to as V_2inAt this time, the ratio of the resistances of the third resistor R3 and the fourth resistor R4 is: 1: A, then:

$\begin{array}{c}{V}_{\mathrm{ref}}=(N+1)\×(\frac{A}{A+1}{\mathrm{\ΔV}}_1+\frac{A}{A+1}{V}_{1\mathrm{RGin}})-N\×(V_{2\mathrm{RGin}}+{\mathrm{\ΔV}}_2)\\ =-{\mathrm{NV}}_{2\mathrm{RGin}}+\frac{(N+1)A}{A+1}{V}_{1\mathrm{RGin}}+\frac{(N+1)A}{A+1}{\mathrm{\ΔV}}_1-\mathrm{N\Δ}{V}_2\end{array}---\left(37\right)$

from equation (37), it can be seen that the voltage V when the first operational amplifier A0 outputs_refI.e., the voltage output by the op amp output circuit 22 is constant, i.e., when the circuit is determined and the voltage V output by the first op amp a0 is constant_refIs only equal to the first input voltage V of the reference voltage generating circuit_1RGinAnd a second input voltage V_2RGinIs related to the gate-source voltage of the first and second PMOSMP1, 2, the first and second triodes Q1, 2When the voltage between the base and the emitter of the tube Q2 is not related, it is only necessary to satisfyThen the method is finished; that is, when Δ V₁≠ΔV₂When it is satisfiedThat is, the voltage V output by the first operational amplifier A0 can be realized_refIs only equal to the first input voltage V of the reference voltage generating circuit_1RGinAnd a second input voltage V_2RGinIs related to the size of (a).

EXAMPLE six

In this embodiment, as shown in fig. 9, the first dc level conversion circuit 31 may include: a first PMOSMP1 and a first transistor Q1; the second dc level shift circuit 32 may include: a second PMOSMP2 and a second transistor Q2; the voltage adjusting circuit 21 may include: a third resistor R3, a fourth resistor R4, and a third reference current source I1, wherein the ratio of the resistances of the third resistor R3 to the fourth resistor R4 is: 1: N; the operational amplifier output circuit 22 may include: the first resistor R1, the second resistor R2 and the first operational amplifier a0, and the ratio of the resistances of the first resistor R1 and the second resistor R2 is: 1: N.

In the reference voltage generating circuit shown in fig. 9, V of the first PMOSMP1 and the second PMOSMP2_gsSimilarly, V of the first transistor Q1 and the second transistor Q2_beSimilarly, in practical applications, both the first transistor Q1 and the second transistor Q2 may be NPN transistors. Wherein, V_gsRepresenting the gate-source voltage, V, of PMOS_beWhich represents the voltage between the base and emitter of the transistor, N is typically a positive integer.

The operating principle of the reference voltage generating circuit shown in fig. 9 is:

for convenience of description, in the following description, the first input of the reference voltage generating circuit is describedPressure is called V_1RGinThe second input voltage of the reference voltage generating circuit is referred to as V_2RGinThe input voltage of the first dc level converting circuit 31 is referred to as V_1inThe output voltage of the first dc level converting circuit 31 is referred to as V_1oThe input voltage of the second DC level shifter 32 is referred to as V_2inThe output voltage of the second DC level shifter 32 is referred to as V_2oThe voltage at the junction formed by the third resistor R3, the fourth resistor R4, and the non-inverting input of the first operational amplifier A0 is referred to as V₁The third resistor R3 has a resistance R, and the current of the third reference current source is called I₃The voltage at the non-inverting input of the first operational amplifier A0 is referred to as V_IPThe voltage at the inverting input of the first operational amplifier A0 is referred to as V_INThe voltage output from the first operational amplifier A0 is referred to as V_ref。

When the reference voltage generating circuit operates, the following relationship exists:

V_1o＝V_1in+V_gs-V_be(7)

V_1in＝V_1RGin(30)

$V_{1o}=(1+\frac{1}{N})V_1-I_{3}R---\left(38\right)$

ΔV＝V_gs-V_be(11)

combining, replacing and the like the formula (7), the formula (11), the formula (30) and the formula (38), then it can be obtained:

$V_1=\frac{N}{N+1}\mathrm{\ΔV}+\frac{N}{N+1}{V}_{1\mathrm{RGin}}+\frac{{\mathrm{NI}}_{3}R}{N+1}---\left(39\right)$

the reference voltage generation circuit shown in fig. 9 also has the following relationship:

V_ref＝(N+1)V_IN-NV_2o(33)

V_IP＝V_IN(14)

V_2o＝V_2in+V_gs-V_be(16)

V_2in＝V_2RGin(34)

V_IP＝V₁(35)

by combining and replacing the formula (11), the formula (14), the formula (16), the formulas (33) to (35), and the formula (39), the following results can be obtained:

$V_{\mathrm{ref}}=-{\mathrm{NV}}_{2\mathrm{RGin}}+(N+1)\frac{N}{N+1}{V}_{1\mathrm{RGin}}+(N+1)\frac{N}{N+1}\mathrm{\ΔV}-\mathrm{N\ΔV}+{\mathrm{NI}}_{3}R$

V_ref＝-NV_2RGin+NV_1RGin+NI₃R(40)

as can be seen from equation (40), the voltage V output from the first operational amplifier a0_refI.e. the magnitude of the voltage output by the operational amplifier output circuit 22, and the first input voltage V of the reference voltage generating circuit_1RGinA second input voltage V_2RGinCurrent I of the third reference current source₃The resistance values R and N of the third resistor R3 are related; the output voltage of the operational amplifier output circuit 22 is only equal to the first input voltage V of the reference voltage generation circuit at the time of circuit determination_1RGinA second input voltage V_2RGinCurrent I of the third reference current source₃And the resistance value R of the third resistor R3 is related to the gate-source voltage of the first pmos mp1 and the second pmos mp2, and the voltage between the base and the emitter of the first transistor Q1 and the second transistor Q2, in other words, by adjusting the input voltage of the non-inverting input terminal of the first operational amplifier a0, the device parameters of the first dc level converting circuit 31 and the second dc level converting circuit 32, i.e. the transistor parameters, are eliminated from the operational amplifierThe effect of the output voltage of the amplifier output circuit 22 is: eliminates the influence of circuit process technology and temperature on the output voltage of the operational amplifier output circuit 22, and makes the output voltage of the operational amplifier output circuit 22 only equal to the first input voltage V of the reference voltage generating circuit when the circuit is determined_1RGinA second input voltage V_2RGinIs dependent on the magnitude of the current I of the third reference current source₃And the resistance R of the third resistor R3, thereby keeping the output voltage of the operational amplifier output circuit 22 constant; and, when the first input voltage V of the reference voltage generating circuit_1RGinAnd a second input voltage V_2RGinWhen both are zero, the output voltage V of the operational amplifier output circuit 22_refIs NI₃R, just so, just can be according to needs, through the adjustment connection power supply Vcc and the current of the third reference current source I3 between the noninverting input of the first operational amplifier A0 in operational amplifier output circuit 22, obtain the size of required output voltage accurately to satisfy user's demand, promote user experience.

In practical applications of the reference voltage generating circuits according to the first to sixth embodiments, as shown in fig. 10A and 10B, each of the first dc level shifting circuit 31 and the second dc level shifting circuit 32 further includes an auxiliary circuit.

As shown in fig. 10A, in practical applications, the first dc level converting circuit 31 may include: a first pmos mp1, a first transistor Q1, a second operational amplifier a1, a first N-channel metal oxide semiconductor field effect transistor (NMOS) MN1, a fourth reference current source I4, and a fifth reference current source I5; wherein, the auxiliary circuit includes: a first NMOSMN1, a fourth reference current source I4, a fifth reference current source I5, and a second operational amplifier a 1.

The role of the auxiliary circuit in the first dc level conversion circuit 31 shown in fig. 10A is: the gate-source voltage of the first PMOSMP1 is ensured to be constant, and the voltage between the base and the emitter of the first triode Q1 is ensured to be constant, so that the voltage output by the operational amplifier output circuit 22 is constant; specifically, the fourth reference current source I4 is used to ensure the gate-source voltage of the first pmos mp1 to be constant, the negative feedback effect of the second operational amplifier a1 and the first nmos mn1 is used, and the fifth reference current source I5 is used to ensure the voltage between the base and the emitter of the first triode Q1 to be constant.

Accordingly, as shown in fig. 10B, in practical applications, the second dc level shift circuit 32 may include: a second pmos mp2, a second transistor Q2, a third operational amplifier a2, a second nmos mn2, a sixth reference current source I6, and a seventh reference current source I7; wherein, the auxiliary circuit includes: a second NMOSMN2, a sixth reference current source I6, a seventh reference current source I7, and a third operational amplifier a 2.

The role of the auxiliary circuit in the second dc level shift circuit 32 shown in fig. 10B is: the gate-source voltage of the second PMOSMP2 is ensured to be constant, and the voltage between the base and the emitter of the second triode Q2 is ensured to be constant, so that the voltage output by the operational amplifier output circuit 22 is constant; specifically, the sixth reference current source I6 is used to ensure the gate-source voltage of the second pmos mp2 to be constant, and the negative feedback effect of the third operational amplifier a2 and the second nmos mn2 and the seventh reference current source I7 are used to ensure the voltage between the base and the emitter of the second triode Q2 to be constant.

Based on the reference voltage generation circuit of the above embodiment, an embodiment of the present invention further provides an integrated circuit, which includes the reference voltage generation circuit.

The integrated circuit can be any analog device requiring a precise reference voltage, such as: reference voltage generators, sensors, video filters, and devices using operational amplifiers, etc.

Based on the reference voltage generating circuit of the above embodiment, an embodiment of the present invention further provides a reference voltage generating method, including: a voltage adjusting circuit of the reference voltage generating circuit keeps constant a voltage output from an operational amplifier output circuit of the reference voltage generating circuit.

Specifically, the reference voltage generating circuit receives a constant input voltage;

the voltage adjusting circuit adjusts the input voltage of the first input end of the operational amplifier output circuit, and the operational amplifier output circuit outputs constant voltage according to the adjusted input voltage of the first input end and the adjusted input voltage of the second input end of the operational amplifier output circuit.

Wherein, the voltage adjusting circuit adjusting the input voltage of the first input terminal of the operational amplifier output circuit specifically comprises: the voltage adjusting circuit adjusts the input voltage of a first direct current level conversion circuit of the reference voltage generating circuit; alternatively, the voltage adjustment circuit divides the input voltage of the first input terminal of the operational amplifier output circuit.

Here, the voltage adjusting circuit adjusts an input voltage of the first dc level converting circuit of the reference voltage generating circuit, specifically:

the voltage adjusting circuit divides the input voltage of the first input end of the operational amplifier output circuit and feeds the voltage obtained by voltage division back to the first direct current level conversion circuit;

the first direct current level conversion circuit performs first displacement on input voltage input into the first direct current level conversion circuit to form input voltage of a first input end of the operational amplifier output circuit.

Correspondingly, the second direct current level conversion circuit carries out second displacement on the input voltage input into the second direct current level conversion circuit to form the input voltage of the second input end of the operational amplifier output circuit, so that the operational amplifier output circuit outputs constant voltage according to the adjusted input voltage of the first input end and the adjusted input voltage of the second input end.

Here, in practical applications, the first displacement may be equal to the second displacement, and the first displacement may not be equal to the second displacement.

In an embodiment, the voltage adjustment circuit may divide the input voltage of the first input terminal of the operational amplifier output circuit by serially connecting resistors.

In an embodiment, the voltage adjustment circuit may divide the input voltage at the first input terminal of the output circuit of the operational amplifier by combining a series voltage division of resistors and a voltage division of a current source.

In one embodiment, when the voltage adjusting circuit adjusts the input voltage of the first input terminal of the operational amplifier output circuit by dividing the input voltage of the first input terminal of the operational amplifier output circuit by the voltage adjusting circuit, the first direct-current level converting circuit performs a first displacement on the input voltage input to the first direct-current level converting circuit to form the input voltage of the first input terminal of the operational amplifier output circuit; correspondingly, the second direct current level conversion circuit carries out second displacement on the input voltage input into the second direct current level conversion circuit, and the input voltage of the second input end of the operational amplifier output circuit is formed.

In various embodiments of the present invention, the keeping of the voltage output by the operational amplifier output circuit constant means: the standard deviation of the compensation voltage of the reference voltage generating circuit is less than or equal to 13.5 mV.

Meanwhile, in order to better explain the technical scheme of the embodiment of the present invention, the output voltage can be kept constant, the present invention also performs experimental comparison between the reference voltage generating circuit shown in fig. 1 and the reference voltage generating circuit provided in the first embodiment of the present invention, and the experimental conditions are as follows: temperature 30 ℃ to the compensation voltage V_offsetSampling for 200 times; wherein, V_offset＝V_ref-V_in，V_refIndicating the voltage, V, output by the reference voltage generating circuit_inWhich represents the input voltage of the reference voltage generating circuit, i.e. the input voltage received by the second dc level shifting circuit.

FIG. 11A is a diagram of the compensation voltage V of the reference voltage generation circuit shown in FIG. 1_offsetAccording to the change chart of the sampling times, the compensation voltage V is obtained by sampling 200 times and sampling 200 times_offsetThe standard deviation calculation can be carried out to obtain: 200 times sampling compensation voltage V_offsetHas a standard deviation of31.6 mV; FIG. 11B shows a compensation voltage V of the reference voltage generating circuit according to an embodiment of the present invention_offsetAccording to the change chart of the sampling times, the compensation voltage V is obtained by sampling 200 times and sampling 200 times_offsetThe standard deviation calculation can be carried out to obtain: 200 times sampling compensation voltage V_offsetThe standard deviation of (A) was 13.5 mV. Wherein, the calculation formula of the standard deviation is as follows:when calculating, n is 200, l_iRepresenting the compensation voltage V obtained by each sampling_offset。

It can be seen from the experimental results that the compensation voltage V of the reference voltage generating circuit provided in the embodiment of the present invention_offsetIs much smaller than the compensation voltage V of the reference voltage generating circuit shown in fig. 1_offsetThis indicates that: the reference voltage generating circuit provided by the embodiment of the invention generates more stable reference voltage.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (18)

1. A reference voltage generation circuit configured to receive a constant input voltage, the reference voltage generation circuit comprising: an operational amplifier output circuit and a voltage adjusting circuit; wherein,

the voltage adjusting circuit is configured to adjust an input voltage of a first input terminal of the operational amplifier output circuit;

the operational amplifier output circuit is configured to output a constant voltage according to the adjusted input voltage of the first input terminal and the adjusted input voltage of the second input terminal of the operational amplifier output circuit.

2. The circuit of claim 1, wherein the reference voltage generation circuit further comprises: a first DC level conversion circuit and a second DC level conversion circuit; wherein,

the first direct current level conversion circuit is configured to perform first displacement on input voltage input into the first direct current level conversion circuit to form input voltage of a first input end of the operational amplifier output circuit;

the second direct current level conversion circuit is configured to perform second displacement on the input voltage input to the second direct current level conversion circuit to form the input voltage of the second input end of the operational amplifier output circuit.

3. The circuit of claim 2, wherein the voltage adjustment circuit is configured to adjust the input voltage of the first dc level shifting circuit.

4. The circuit of claim 3, wherein the voltage adjustment circuit is configured to divide an input voltage at the first input terminal of the operational amplifier output circuit and feed back the divided voltage to the first DC level shifter circuit.

5. The circuit of claim 2, wherein the voltage adjustment circuit is configured to divide an input voltage at the first input of the operational amplifier output circuit.

6. An integrated circuit comprising a reference voltage generation circuit configured to receive a constant input voltage, the reference voltage generation circuit comprising: an operational amplifier output circuit and a voltage adjusting circuit; wherein,

the voltage adjusting circuit is configured to adjust an input voltage of a first input terminal of the operational amplifier output circuit;

the operational amplifier output circuit is configured to output a constant voltage according to the adjusted input voltage of the first input terminal and the adjusted input voltage of the second input terminal of the operational amplifier output circuit.

7. The integrated circuit of claim 6, wherein the reference voltage generation circuit further comprises: a first DC level conversion circuit and a second DC level conversion circuit; wherein,

the first direct current level conversion circuit is configured to perform first displacement on input voltage input into the first direct current level conversion circuit to form input voltage of a first input end of the operational amplifier output circuit;

the second direct current level conversion circuit is configured to perform second displacement on the input voltage input to the second direct current level conversion circuit to form the input voltage of the second input end of the operational amplifier output circuit.

8. The integrated circuit of claim 7, wherein the voltage adjustment circuit is configured to adjust the input voltage of the first DC level shifter circuit.

9. The integrated circuit of claim 8, wherein the voltage adjustment circuit is configured to divide an input voltage at the first input terminal of the operational amplifier output circuit and feed back the divided voltage to the first dc level shifting circuit.

10. The integrated circuit of claim 7, wherein the voltage adjustment circuit is configured to divide the input voltage at the first input of the operational amplifier output circuit.

11. A method of reference voltage generation, the method comprising:

the reference voltage generating circuit receives a constant input voltage;

the voltage adjusting circuit of the reference voltage generating circuit adjusts the input voltage of the first input end of the operational amplifier output circuit of the reference voltage generating circuit;

and the operational amplifier output circuit outputs constant voltage according to the adjusted input voltage of the first input end and the adjusted input voltage of the second input end.

12. The method of claim 11, wherein the voltage adjustment circuit of the reference voltage generation circuit adjusts the input voltage at the first input of the operational amplifier output circuit of the reference voltage generation circuit, comprising:

the voltage adjusting circuit adjusts an input voltage of a first direct current level conversion circuit of the reference voltage generating circuit.

13. The method of claim 12, wherein the voltage adjustment circuit adjusts the input voltage of the first dc level shifter circuit of the reference voltage generation circuit to:

the voltage adjusting circuit divides the input voltage of the first input end of the operational amplifier output circuit and feeds the voltage obtained by division back to the first direct-current level conversion circuit of the reference voltage generating circuit;

the first direct current level conversion circuit carries out first displacement on input voltage input into the first direct current level conversion circuit to form input voltage of a first input end of the operational amplifier output circuit;

correspondingly, the second direct current level conversion circuit of the reference voltage generation circuit carries out second displacement on the input voltage input into the second direct current level conversion circuit, and the input voltage of the second input end of the operational amplifier output circuit is formed.

14. The method of claim 11, wherein the voltage adjustment circuit of the reference voltage generation circuit adjusts the input voltage at the first input of the operational amplifier output circuit of the reference voltage generation circuit, comprising:

the voltage adjusting circuit divides an input voltage of a first input end of the operational amplifier output circuit.

15. The method of claim 13 or 14, wherein the voltage adjustment circuit divides the input voltage at the first input terminal of the operational amplifier output circuit by serially dividing the voltage through resistors; or, the voltage adjusting circuit divides the input voltage of the first input end of the operational amplifier output circuit by combining the serial resistance voltage division and the current source voltage division.

16. The method of claim 14, further comprising:

the first direct current level conversion circuit of the reference voltage generation circuit carries out first displacement on input voltage input into the first direct current level conversion circuit to form input voltage of a first input end of the operational amplifier output circuit;

and the second direct current level conversion circuit of the reference voltage generation circuit carries out second displacement on the input voltage input into the second direct current level conversion circuit to form the input voltage of the second input end of the operational amplifier output circuit.

17. A method of reference voltage generation, the method comprising:

the reference voltage generating circuit receives a constant input voltage;

the reference voltage generating circuit outputs a constant voltage; wherein,

the value of the output voltage is entirely determined by the input voltage.

18. The method of claim 17, wherein the reference voltage generation circuit outputs a constant voltage of: the standard deviation of the compensation voltage of the reference voltage generating circuit is less than or equal to 13.5 mV.