CN105677967B - A method of promoting ASIC arithmetic accuracy - Google Patents
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Abstract
Description
技术领域technical field
本发明公开一种提升ASIC算法精度的方法，属于计算机技术领域。The invention discloses a method for improving the accuracy of an ASIC algorithm, which belongs to the technical field of computers.
背景技术Background technique
ASIC，是一种为专门目的而设计的集成电路。是指应特定用户要求和特定电子系统的需要而设计、制造的集成电路。ASIC的特点是面向特定用户的需求，ASIC在批量生产时与通用集成电路相比具有体积更小、功耗更低、可靠性提高、性能提高、保密性增强、成本降低等优点。随着科技发展，出现数字ASIC，数字ASIC实现加减乘除等运算的算法时，需要小心处理，因为数字ASIC中用”0””1”来代表高低电平，不可能出现小数，尤其是对除法的处理，不当的算法，将导致最终运算结果的巨大偏差，从而影响整个ASIC设计。本发明针对数字ASIC中加减乘除等运算的高精度实现，提出了一种提升ASIC算法精度的方法，可用于半导体领域，可以减小算法中间过程带来的精度损耗，而且可以实现向下取整、向上取整、四舍五入或者根据实际情况自设定的取整规则。该方法具有通用性强、实施简便等特点，具有广阔的应用前景。ASIC is an integrated circuit designed for a special purpose. Refers to integrated circuits designed and manufactured in response to specific user requirements and the needs of specific electronic systems. The characteristic of ASIC is that it is oriented to the needs of specific users. Compared with general-purpose integrated circuits, ASIC has the advantages of smaller size, lower power consumption, improved reliability, improved performance, enhanced confidentiality, and reduced cost when mass-produced. With the development of science and technology, digital ASICs appear. When digital ASICs implement algorithms such as addition, subtraction, multiplication, and division, they need to be handled carefully, because "0" and "1" are used to represent high and low levels in digital ASICs, and decimals cannot appear, especially for The processing of division and improper algorithm will lead to a huge deviation of the final calculation result, which will affect the entire ASIC design. Aiming at the high-precision realization of operations such as addition, subtraction, multiplication, and division in digital ASICs, the present invention proposes a method for improving the accuracy of ASIC algorithms, which can be used in the field of semiconductors, can reduce the accuracy loss caused by the intermediate process of the algorithm, and can realize downward selection Rounding, rounding up, rounding up, or self-set rounding rules according to the actual situation. This method has the characteristics of strong versatility and simple implementation, and has broad application prospects.
发明内容Contents of the invention
本发明针对现有技术中数字ASIC的不当算法，将导致最终运算结果的巨大偏差，从而影响整个ASIC设计的问题，提供一种提升ASIC算法精度的方法，具有通用性强、实施简便等特点，具有广阔的应用前景。The present invention aims at the problem that the improper algorithm of the digital ASIC in the prior art will lead to a huge deviation of the final calculation result, thereby affecting the design of the entire ASIC, and provides a method for improving the accuracy of the ASIC algorithm, which has the characteristics of strong versatility and easy implementation. with broadly application foreground.
本发明提出的具体方案是：The concrete scheme that the present invention proposes is:
一种提升ASIC算法精度的方法：A method to improve the accuracy of ASIC algorithm:
在针对ASIC设计进行中间运算过程中，设置算法减损模块和取整运算模块；In the process of performing intermediate calculations for ASIC design, set up the algorithm impairment module and the rounding operation module;
算法减损模块用于算法中间过程中保留更多的有效位数，取整运算模块根据实际情况采取整规则对结果进行取整；The algorithm impairment module is used to retain more effective digits in the middle process of the algorithm, and the rounding operation module adopts the rounding rule to round the result according to the actual situation;
具体过程为在针对ASIC设计进行中间运算之前对分子部分的数据利用算法减损模块进行减损因子δ调整，使得在做除法之前提高分子的有效位数，进而除法之后的结果保留更多的有效位数，并利用取整运算模块根据实际情况采取的取整规则来对结果进行取整处理，以减少运算中间过程带来的精度损耗。The specific process is to use the algorithm impairment module to adjust the impairment factor δ on the data of the molecular part before performing intermediate calculations for the ASIC design, so that the number of effective digits of the molecule is increased before the division, and the result after the division retains more effective digits. , and use the rounding rule adopted by the rounding operation module according to the actual situation to round the result, so as to reduce the precision loss caused by the intermediate operation process.
所述减损因子δ根据在ASIC设计中计算的需要，在21,22,23,24,25,…，2n中选取，通过移位来实现乘法。The impairment factor δ is selected from 21, 22, 23, 24, 25, .
所述取整运算模块采取的取整规则为向下取整、向上取整、四舍五入或者根据实际情况自设定的取整规则。The rounding rule adopted by the rounding operation module is rounding down, rounding up, rounding up, or a rounding rule set by itself according to the actual situation.
一种提升ASIC算法精度的系统，用于所述的方法，包括算法减损模块和取整运算模块，算法减损模块用于算法中间过程中保留更多的有效位数，取整运算模块根据实际情况采取整规则对结果进行取整；A system for improving the accuracy of an ASIC algorithm, used for the method, including an algorithm impairment module and a rounding operation module, the algorithm impairment module is used to retain more effective digits in the middle of the algorithm, and the rounding operation module is based on the actual situation Use the integer rule to round the result;
具体过程为在针对ASIC设计进行中间运算之前对分子部分的数据利用算法减损模块进行减损因子δ调整，使得在做除法之前提高分子的有效位数，进而除法之后的结果保留更多的有效位数，并利用取整运算模块根据实际情况采取的取整规则来对结果进行取整处理，以减少运算中间过程带来的精度损耗。The specific process is to use the algorithm impairment module to adjust the impairment factor δ on the data of the molecular part before performing intermediate calculations for the ASIC design, so that the number of effective digits of the molecule is increased before the division, and the result after the division retains more effective digits. , and use the rounding rule adopted by the rounding operation module according to the actual situation to round the result, so as to reduce the precision loss caused by the intermediate operation process.
所述取整运算模块采取的取整规则为向下取整、向上取整、四舍五入或者根据实际情况自设定的取整规则。The rounding rule adopted by the rounding operation module is rounding down, rounding up, rounding up, or a rounding rule set by itself according to the actual situation.
本发明的有益之处是：The benefits of the present invention are:
本发明针对数字ASIC中加减乘除等运算的高精度实现，提出了一种提升ASIC算法精度的方法，可用于半导体领域，可以减小算法中间过程带来的精度损耗，而且可以实现向下取整、向上取整、四舍五入或者根据实际情况自设定的取整规则。该方法具有通用性强、实施简便等特点，具有广阔的应用前景。Aiming at the high-precision realization of operations such as addition, subtraction, multiplication, and division in digital ASICs, the present invention proposes a method for improving the accuracy of ASIC algorithms, which can be used in the field of semiconductors, can reduce the accuracy loss caused by the intermediate process of the algorithm, and can realize downward selection Rounding, rounding up, rounding up, or self-set rounding rules according to the actual situation. This method has the characteristics of strong versatility and simple implementation, and has broad application prospects.
附图说明Description of drawings
图1是本发明方法算法减损过程示意图。Fig. 1 is a schematic diagram of the algorithm reduction process of the method of the present invention.
具体实施方式Detailed ways
一种提升ASIC算法精度的方法：A method to improve the accuracy of ASIC algorithm:
在针对ASIC设计进行中间运算过程中，设置算法减损模块和取整运算模块；In the process of performing intermediate calculations for ASIC design, set up the algorithm impairment module and the rounding operation module;
算法减损模块用于算法中间过程中保留更多的有效位数，取整运算模块根据实际情况采取整规则对结果进行取整；The algorithm impairment module is used to retain more effective digits in the middle process of the algorithm, and the rounding operation module adopts the rounding rule to round the result according to the actual situation;
具体过程为在针对ASIC设计进行中间运算之前对分子部分的数据利用算法减损模块进行减损因子δ调整，使得在做除法之前提高分子的有效位数，进而除法之后的结果保留更多的有效位数，并利用取整运算模块根据实际情况采取的取整规则来对结果进行取整处理，以减少运算中间过程带来的精度损耗。The specific process is to use the algorithm impairment module to adjust the impairment factor δ on the data of the molecular part before performing intermediate calculations for the ASIC design, so that the number of effective digits of the molecule is increased before the division, and the result after the division retains more effective digits. , and use the rounding rule adopted by the rounding operation module according to the actual situation to round the result, so as to reduce the precision loss caused by the intermediate operation process.
利用上述方法，根据发明内容及附图，对本发明做进一步说明。Utilizing the above method, the present invention will be further described according to the content of the invention and the accompanying drawings.
以实现一个的算法做例子。to achieve a algorithm as an example.
假设a＝51,b＝18,c＝11,那么在ASIC设计中，如果仅仅用来实现，ASIC的运算结果默认是向下取整的，y＝83。Suppose a=51, b=18, c=11, then In ASIC design, if only the To achieve, the operation result of ASIC is rounded down by default, y=83.
用本发明一种提升ASIC算法精度的方法来实现的话，假设减损因子δ＝16，经过算法减损模块得到的运算结果在取整运算模块中可以实现向上取整，四舍五入或者根据实际情况自设定的取整规则，最终结果y＝z[m,n]+f(z[n-1:0])，其中，m为z的最高比特位，n取值与减损因子有关，2n＝δ。If it is implemented by a method of improving the accuracy of the ASIC algorithm of the present invention, assuming the impairment factor δ=16, the calculation result obtained by the algorithm impairment module In the rounding operation module, upward rounding, rounding, or self-set rounding rules can be realized according to the actual situation, and the final result is y=z[m,n]+f(z[n-1:0]), where, m is the highest bit of z, the value of n is related to the impairment factor, 2 n =δ.
若是采用向上取整，根据z[3:0]是否为0来判定最终运算结果是否加1：非0，则加1；否则舍弃。在此z＝1335，z[3:0]＝4’b0111＝4’d7，最终运算结果y＝z[10:4]+f(z[3:0])＝83+1＝84。If rounding up is used, determine whether the final operation result is added to 1 according to whether z[3:0] is 0: if it is not 0, add 1; otherwise, discard it. Here z=1335, z[3:0]=4'b0111=4'd7, the final operation result y=z[10:4]+f(z[3:0])=83+1=84.
若是采用四舍五入，根据z[3:0]是否为不小于8来判定最终运算结果是否加1：不小于8，则加1；否则舍弃。在此z＝1335，z[3:0]＝4‘b0111＝4’d7，最终运算结果y＝z[10:4]+f(z[3:0])＝83+0＝83。If rounding is used, it is determined whether the final operation result is plus 1 according to whether z[3:0] is not less than 8: if it is not less than 8, add 1; otherwise discard. Here z=1335, z[3:0]=4'b0111=4'd7, the final operation result y=z[10:4]+f(z[3:0])=83+0=83.
若是根据实际情况自设定的取整规则，比如二舍三入，根据z[3:0]是否为不小于4来判定最终运算结果是否加1：不小于4，则加1；否则舍弃。在此z＝1335，z[3:0]＝4‘b0111＝4’d7，最终运算结果y＝z[10:4]+f(z[3:0])＝83+1＝84。If the rounding rules are set according to the actual situation, such as rounding, judge whether the final operation result is added 1 according to whether z[3:0] is not less than 4: if it is not less than 4, add 1; otherwise discard. Here z=1335, z[3:0]=4'b0111=4'd7, the final operation result y=z[10:4]+f(z[3:0])=83+1=84.
假设减损因子δ＝32，经过算法减损模块得到的运算结果在取整运算模块中可以实现向上取整，四舍五入或者根据实际情况自设定的取整规则，最终结果y＝z[m,n]+f(z[n-1:0])，其中，m为z的最高比特位，n取值与减损因子有关，2n＝δ。Assuming the impairment factor δ=32, the calculation result obtained by the algorithm impairment module In the rounding operation module, upward rounding, rounding, or self-set rounding rules can be realized according to the actual situation, and the final result is y=z[m,n]+f(z[n-1:0]), where, m is the highest bit of z, the value of n is related to the impairment factor, 2 n =δ.
若是采用向上取整，根据z[4:0]是否为0来判定最终运算结果是否加1：非0，则加1；否则舍弃。在此z＝2670，z[4:0]＝5’b01110＝5’d15，最终运算结果y＝z[10:5]+f(z[4:0])＝83+1＝84。If rounding up is used, determine whether the final operation result is added to 1 according to whether z[4:0] is 0: if it is not 0, add 1; otherwise, discard it. Here z=2670, z[4:0]=5'b01110=5'd15, the final operation result y=z[10:5]+f(z[4:0])=83+1=84.
若是采用四舍五入，根据z[4:0]是否为不小于16来判定最终运算结果是否加1：不小于16，则加1；否则舍弃。在此z＝2670，z[4:0]＝5‘b01110＝5’d15，最终运算结果y＝z[10:5]+f(z[4:0])＝83+0＝83。If rounding is used, determine whether the final operation result is plus 1 according to whether z[4:0] is not less than 16: if it is not less than 16, add 1; otherwise, discard it. Here z=2670, z[4:0]=5'b01110=5'd15, the final operation result y=z[10:5]+f(z[4:0])=83+0=83.
假设减损因子δ＝8，经过算法减损模块得到的运算结果向下取整，舍弃0.5；在取整运算模块中可以实现向上取整，四舍五入或者根据实际情况自设定的取整规则，最终结果y＝z[m,n]+f(z[n-1:0])，其中，m为z的最高比特位，n取值与减损因子有关，2n＝δ。Assuming the impairment factor δ=8, the calculation result obtained by the algorithm impairment module Round down and discard 0.5; in the rounding operation module, you can realize rounding up, rounding or self-set rounding rules according to the actual situation, and the final result is y=z[m,n]+f(z[n- 1:0]), where m is the highest bit of z, and the value of n is related to the impairment factor, 2 n =δ.
若是采用向上取整，根据z[2:0]是否为0来判定最终运算结果是否加1：非0，则加1；否则舍弃。在此z＝667，z[2:0]＝3’b011＝3’d3，最终运算结果y＝z[10:3]+f(z[2:0])＝83+1＝84。If rounding up is used, determine whether the final operation result is added to 1 according to whether z[2:0] is 0: if it is not 0, add 1; otherwise, discard it. Here z=667, z[2:0]=3'b011=3'd3, the final operation result y=z[10:3]+f(z[2:0])=83+1=84.
若是采用四舍五入，根据z[2:0]是否为不小于4来判定最终运算结果是否加1：不小于4，则加1；否则舍弃。在此z＝667，z[2:0]＝3‘b011＝3’d3，最终运算结果y＝z[10:3]+f(z[2:0])＝83+0＝83。If rounding is used, determine whether the final calculation result is plus 1 according to whether z[2:0] is not less than 4: if it is not less than 4, add 1; otherwise, discard it. Here z=667, z[2:0]=3'b011=3'd3, the final operation result y=z[10:3]+f(z[2:0])=83+0=83.
假设减损因子δ＝4，，经过算法减损模块得到的运算结果向下取整，舍弃0.75；在取整运算模块中可以实现向上取整，四舍五入或者根据实际情况自设定的取整规则，最终结果y＝z[m,n]+f(z[n-1:0])，其中，m为z的最高比特位，n取值与减损因子有关，2n＝δ。Assuming the impairment factor δ=4, the calculation result obtained by the algorithm impairment module Round down and discard 0.75; in the rounding operation module, you can realize rounding up, rounding up or self-set rounding rules according to the actual situation, and the final result is y=z[m,n]+f(z[n- 1:0]), where m is the highest bit of z, the value of n is related to the impairment factor, 2 n =δ.
若是采用向上取整，根据z[1:0]是否为0来判定最终运算结果是否加1：非0，则加1；否则舍弃。在此z＝333，z[1:0]＝2’b01＝2’d1，最终运算结果y＝z[10:2]+f(z[1:0])＝83+1＝84。If rounding up is used, determine whether the final operation result is added 1 according to whether z[1:0] is 0: if it is not 0, add 1; otherwise, discard it. Here z=333, z[1:0]=2'b01=2'd1, the final operation result y=z[10:2]+f(z[1:0])=83+1=84.
若是采用四舍五入，根据z[1:0]是否为不小于4来判定最终运算结果是否加1：不小于2，则加1；否则舍弃。在此z＝333，z[1:0]＝2‘b01＝2’d1，最终运算结果y＝z[10:2]+f(z[1:0])＝83+0＝83。If rounding is used, it is judged whether the final calculation result is plus 1 according to whether z[1:0] is not less than 4: if it is not less than 2, add 1; otherwise discard. Here z=333, z[1:0]=2'b01=2'd1, the final operation result y=z[10:2]+f(z[1:0])=83+0=83.
假设减损因子δ＝2，经过算法减损模块得到的运算结果向下取整，舍弃0.875；在取整运算模块中可以实现向上取整，四舍五入或者根据实际情况自设定的取整规则，最终结果y＝z[m,n]+f(z[n-1:0])，其中，m为z的最高比特位，n取值与减损因子有关，2n＝δ。Assuming the impairment factor δ=2, the calculation result obtained by the algorithm impairment module Round down and discard 0.875; in the rounding operation module, you can realize rounding up, rounding up or self-set rounding rules according to the actual situation, and the final result is y=z[m,n]+f(z[n- 1:0]), where m is the highest bit of z, the value of n is related to the impairment factor, 2 n =δ.
若是采用向上取整，根据z[0]是否为0来判定最终运算结果是否加1：非0，则加1；否则舍弃。在此z＝166，z[1:0]＝1’b0，最终运算结果y＝z[10:1]+f(z[0])＝83+0＝83。而向上取整应该是84。If rounding up is used, determine whether the final operation result is added 1 according to whether z[0] is 0: if it is not 0, add 1; otherwise, discard it. Here z=166, z[1:0]=1'b0, and the final operation result y=z[10:1]+f(z[0])=83+0=83. And rounded up should be 84.
若是采用四舍五入，根据z[0]是否为不小于1来判定最终运算结果是否加1：不小于1，则加1；否则舍弃。在此z＝166，z[0]＝1‘b0，最终运算结果y＝z[10:1]+f(z[0])＝83+0＝83。If rounding is used, determine whether the final operation result is added 1 according to whether z[0] is not less than 1: if it is not less than 1, add 1; otherwise, discard it. Here z=166, z[0]=1'b0, and the final operation result y=z[10:1]+f(z[0])=83+0=83.
此例，如果选取减损因子δ＝2，会导致向上取整出错，所以，如果用向上取整的话，选取此减损因子是不合适的。减因损子的选取由具体的设计者根据需要的计算结果决定，为了易于硬件电路实现，可在21,22,23,24,25,…，2n中选取，通过移位来实现乘法，选取的值越大，出错几率越低。配合中间计算结果z[n-1:0]来矫正最终结果。In this example, if the impairment factor δ=2 is selected, an error of rounding up will result. Therefore, if rounding up is used, it is inappropriate to select this impairment factor. The selection of the factor subtraction factor is determined by the specific designer according to the required calculation results. In order to facilitate the realization of the hardware circuit, it can be selected from 2 1 , 2 2 , 2 3 , 2 4 , 2 5 ,..., 2 n , by shifting Bits are used to implement multiplication. The larger the value selected, the lower the chance of error. Cooperate with the intermediate calculation result z[n-1:0] to correct the final result.
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