CN105676195A - Debugging system for secondary radar receiver - Google Patents
Debugging system for secondary radar receiver Download PDFInfo
- Publication number
- CN105676195A CN105676195A CN201610028178.6A CN201610028178A CN105676195A CN 105676195 A CN105676195 A CN 105676195A CN 201610028178 A CN201610028178 A CN 201610028178A CN 105676195 A CN105676195 A CN 105676195A
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- chip microcomputer
- receiver
- signal source
- debugging system
- debugging
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- 230000010355 oscillation Effects 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 19
- 238000004891 communication Methods 0.000 abstract description 3
- 230000035945 sensitivity Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4004—Means for monitoring or calibrating of parts of a radar system
- G01S7/4021—Means for monitoring or calibrating of parts of a radar system of receivers
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- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
The invention discloses a debugging system for a secondary radar receiver, belongs to the technical field of wireless communication, and solves the technical problem existing in an existing debugging method that the debugging efficiency is too low. The debugging system for the secondary radar receiver includes a single-chip microcomputer, a signal modulator, a radio frequency signal source and a local oscillator signal source; the single-chip microcomputer is connected with the radio frequency signal source, the local oscillator signal source and the receiver; and the signal modulator is connected with the radio frequency signal source.
Description
Technical field
The present invention relates to wireless communication technology field, specifically, relate to the debugging system of a kind of secondary radar receiver.
Background technology
Along with the development of wireless communication technology, secondary radar receiver being it is also proposed higher requirement, be in particular in that the requirement of sensitivity and unevenness is high, dynamic range is big, the aspects such as capacity of resisting disturbance is strong. The index of equipment under test is tested by what traditional index debugging adopted is multiple stage instrument, instrument item by item, and test period length, process are complicated. If debugging hardware circuit again defective after test, concrete grammar is to increase debugging electric capacity, resistance, π type attenuation network etc., have impact on the quality of product and manufacturing schedule to a great extent.
Existing debugging process needs three adjustor's collaborative works just can complete debugging, concrete debugging process is: after first adjustor sets frequency, by computer serial port, second adjustor sends whether tune-up data, observation oscilloscope, detection sensitivity and noise meet requirement. If defective, change tune-up data, continue through serial ports and send tune-up data, until sensitivity and noise meet index request and just stop sending. 3rd adjustor, by closing power supply, makes FPGA power down in receiver preserve data. Because receiver has a lot of frequencies, so one receiver of debugging needs to debug many times. That is three adjustors to pass through repeatedly to have coordinated debugging, but usually causes corrupt data because of asynchronous, has a strong impact on product quality, and debugs receiver needs 30 minutes. Therefore, there is the technical problem that debugging efficiency is too low in existing adjustment method.
Summary of the invention
It is an object of the invention to provide the debugging system of a kind of secondary radar receiver, there is the technical problem that debugging efficiency is too low solving existing adjustment method.
The present invention provides the debugging system of a kind of secondary radar receiver, including single-chip microcomputer, signal modulator, radio-frequency signal source and local oscillation signal source;
Described single-chip microcomputer connects described radio-frequency signal source, described local oscillation signal source and receiver;
Described signal modulator connects described radio-frequency signal source.
Further, this debugging system also includes electrical level transferring chip and driving chip;
Described single-chip microcomputer connects the digital signal panel in described receiver by described electrical level transferring chip;
Described single-chip microcomputer connects described radio-frequency signal source, described local oscillation signal source and described receiver by described driving chip, and described driving chip is also connected with the digital signal panel in described receiver.
Further, described receiver includes frequency mixer and analog signal processing plate;
Described radio-frequency signal source and described local oscillation signal source are connected to described frequency mixer, and described frequency mixer connects described analog signal processing plate.
Further, this debugging system also includes FPGA;
Described FPGA is connected with described signal modulator.
Further, this debugging system also includes dual-output power supply;
The outfan of described dual-output power supply connects described receiver, and the control end of described dual-output power supply connects described single-chip microcomputer.
Preferably, it is connected by relay between described single-chip microcomputer with described dual-output power supply.
Further, this debugging system also includes wireless receiver and remote controllers;
Described single-chip microcomputer connects described wireless receiver;
Described remote controllers control described single-chip microcomputer by described wireless receiver.
Further, described single-chip microcomputer is also associated with button controller.
Further, described single-chip microcomputer is also associated with display screen.
Preferably, by showing that driving plate is connected between described single-chip microcomputer with described display screen.
Present invention offers following beneficial effect: in the debugging system of secondary radar receiver provided by the invention, single-chip microcomputer connect radio-frequency signal source, local oscillation signal source and receiver, and connected radio-frequency signal source by signal modulator. When receiver is debugged, it is possible to by Single-chip Controlling radio-frequency signal source, local oscillation signal source and receiver, and by signal modulator, radio-frequency signal source is modulated. When sensitivity and noise meet the standard value prestored in single-chip microcomputer, debugging can be completed. Therefore, in technical scheme provided by the invention, whole debugging process is all performed accurately automatically by single-chip microcomputer, does not have the nonsynchronous problem of debugging process, and the time debugging a receiver can foreshorten to 2 minutes, thus significantly improve the debugging efficiency of receiver.
Other features and advantages of the present invention will be set forth in the following description, and, becoming apparent from description of part, or understand by implementing the present invention. The purpose of the present invention and other advantages can be realized by structure specifically noted in description, claims and accompanying drawing and be obtained.
Accompanying drawing explanation
For the technical scheme in the clearer explanation embodiment of the present invention, below required accompanying drawing during embodiment is described is done simple introduction:
Fig. 1 is the schematic diagram of the debugging system of the secondary radar receiver that the embodiment of the present invention provides.
Detailed description of the invention
Describing embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the process that realizes reaching technique effect can fully understand and implement according to this. As long as it should be noted that do not constitute conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
As it is shown in figure 1, the embodiment of the present invention provides the debugging system of a kind of secondary radar receiver, including single-chip microcomputer, signal modulator, radio-frequency signal source and local oscillation signal source. Wherein, single-chip microcomputer connects radio-frequency signal source, local oscillation signal source and receiver, and signal modulator connects radio-frequency signal source. Whole debugging process is compiled in single-chip microcomputer with C language, such that it is able to there is single-chip microcomputer automatically to perform whole debugging process.
As a preferred version, this debugging system also includes electrical level transferring chip and driving chip.Single-chip microcomputer connects the digital signal panel in receiver by electrical level transferring chip, enables single-chip microcomputer to be sent tune-up data to digital signal panel by serial ports. Digital signal panel is a field programmable gate array (Field-ProgrammableGateArray is called for short FPGA), and tune-up data includes the sensitivity of each frequency of receiver and the standard value of noise.
Single-chip microcomputer connects radio-frequency signal source, local oscillation signal source and receiver by driving chip, and driving chip is also connected with the digital signal panel in receiver, make single-chip microcomputer in debugging process, radio-frequency signal source, local oscillation signal source can be controlled, reach the corresponding frequency of each frequency. Driving chip can transfer the sensitivity of current frequency and the standard value of noise from digital signal panel.
Further, this debugging system also includes a FPGA of additionally setting, and this FPGA is connected with signal modulator. This FPGA adopt VerilogHDL be programmed, for control signal manipulator output modulation signal.
In the present embodiment, in receiver except digital signal panel, also include frequency mixer and analog signal processing plate. Radio-frequency signal source and local oscillation signal source are connected to frequency mixer, and frequency mixer connects simulation signal-processing board. Local oscillation signal source sends local oscillation signal, and radio-frequency signal source sends radiofrequency signal, local oscillation signal and radiofrequency signal and is mixed in frequency mixer, produces intermediate-freuqncy signal, and this intermediate-freuqncy signal is processed by analog signal processing plate.
Further, also including dual-output power supply in this debugging system, the outfan of dual-output power supply connects receiver, and the control end of dual-output power supply connects single-chip microcomputer. Wherein, by being connected by relay between single-chip microcomputer with dual-output power supply. When sensitivity and noise meet the standard value of this frequency, single-chip microcomputer will control relay and turn off dual-output power supply, makes digital signal panel (FPGA) power down of receiver, thus preserving the tune-up data of current frequency. Then, single-chip microcomputer controls relay again and opens dual-output power supply, makes digital signal panel power on, and proceeds the debugging of next frequency.
Further, this debugging system also includes wireless receiver and remote controllers, and single-chip microcomputer connects wireless receiver, and remote controllers pass through wireless receiver control single chip computer. Adjustor can utilize remote controllers, and single-chip microcomputer is remotely operated, thus monitoring, managing the debugging efforts of single-chip microcomputer. Adopt wireless receiver operation single-chip microcomputer, it is possible to solve in the process of debugging, to debug cable because touching the problem of the loose contact occurred, thus ensure that receiver accuracy of parameters in debugging process.
It addition, single-chip microcomputer is also associated with button controller, for instance entering apparatus such as keyboards. Adjustor can also utilize button controller that single-chip microcomputer is operated, and the program in single-chip microcomputer is compiled and revises.
In the present embodiment, single-chip microcomputer is also associated with display screen, and this display screen is preferably the LCDs of resolution 320 × 240. Further, by showing that driving plate is connected between single-chip microcomputer with this display screen, display drives the display signal of plate reception processing single chip, realizes the display of image on a display screen.
The specific works process of the debugging system of the secondary radar receiver that the embodiment of the present invention provides is as follows:
Utilize C language program of compiled whole debugging process in single-chip microcomputer, and utilize VerilogHDL program of compiled modulation signal in FPGA, the debugging of machine can be received.
Single-chip microcomputer passes through electrical level transferring chip, by the digital signal panel of the sensitivity of each frequency of receiver and the standard value input receiver of noise.
When each frequency is debugged, single-chip microcomputer controls the frequency in radio-frequency signal source and local oscillation signal source by driving chip, and transfers the sensitivity of current frequency and the standard value of noise from digital signal panel by driving chip.
FPGA control signal manipulator output modulation signal, is modulated radio-frequency signal source signal. After modulation, the local oscillation signal that local oscillation signal source sends and radio-frequency signal source send radiofrequency signal and are mixed in frequency mixer, produce intermediate-freuqncy signal, and this intermediate-freuqncy signal is processed by analog signal processing plate. If sensitivity and noise are unsatisfactory for the standard value of current frequency, are then changed modulation signal by FPGA, and continue through signal modulator output modulation signal. When sensitivity and noise meet the standard value of current frequency, single-chip microcomputer will control relay and turn off dual-output power supply, making the digital signal panel power down of receiver, thus preserving the tune-up data of current frequency, completing the debugging of this frequency.
Then, single-chip microcomputer controls relay again and opens dual-output power supply, makes digital signal panel power on, and proceeds the debugging of next frequency.
Utilize the debugging system that the embodiment of the present invention provides, all automatically performed accurately by single-chip microcomputer in the whole process that receiver is debugged, do not have the nonsynchronous problem of debugging process, and the time debugging a receiver can foreshorten to 2 minutes, thus significantly improve the debugging efficiency of receiver.
Furthermore it is also possible in the program of single-chip microcomputer increase maintenance subprogram, this maintenance subprogram can on a display screen to adjustor provide to phase normal operation time major parameter achievement data, assistant adjustment person quickly finishes maintenance task.
While it is disclosed that embodiment as above, but described content is only to facilitate the embodiment understanding the present invention and adopt, is not limited to the present invention. Technical staff in any the technical field of the invention; under the premise without departing from spirit and scope disclosed in this invention; any amendment and change can be done in the formal and details implemented; but the scope of patent protection of the present invention, still must be as the criterion with the scope that appending claims defines.
Claims (10)
1. the debugging system of a secondary radar receiver, it is characterised in that include single-chip microcomputer, signal modulator, radio-frequency signal source and local oscillation signal source;
Described single-chip microcomputer connects described radio-frequency signal source, described local oscillation signal source and receiver;
Described signal modulator connects described radio-frequency signal source.
2. debugging system according to claim 1, it is characterised in that also include electrical level transferring chip and driving chip;
Described single-chip microcomputer connects the digital signal panel in described receiver by described electrical level transferring chip;
Described single-chip microcomputer connects described radio-frequency signal source, described local oscillation signal source and described receiver by described driving chip, and described driving chip is also connected with the digital signal panel in described receiver.
3. debugging system according to claim 1, it is characterised in that described receiver includes frequency mixer and analog signal processing plate;
Described radio-frequency signal source and described local oscillation signal source are connected to described frequency mixer, and described frequency mixer connects described analog signal processing plate.
4. debugging system according to claim 1, it is characterised in that also include FPGA;
Described FPGA is connected with described signal modulator.
5. debugging system according to claim 1, it is characterised in that also include dual-output power supply;
The outfan of described dual-output power supply connects described receiver, and the control end of described dual-output power supply connects described single-chip microcomputer.
6. debugging system according to claim 5, it is characterised in that be connected by relay between described single-chip microcomputer with described dual-output power supply.
7. debugging system according to claim 1, it is characterised in that also include wireless receiver and remote controllers;
Described single-chip microcomputer connects described wireless receiver;
Described remote controllers control described single-chip microcomputer by described wireless receiver.
8. debugging system according to claim 1, it is characterised in that described single-chip microcomputer is also associated with button controller.
9. debugging system according to claim 1, it is characterised in that described single-chip microcomputer is also associated with display screen.
10. debugging system according to claim 9, it is characterised in that by showing that driving plate is connected between described single-chip microcomputer with described display screen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610028178.6A CN105676195A (en) | 2016-01-15 | 2016-01-15 | Debugging system for secondary radar receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610028178.6A CN105676195A (en) | 2016-01-15 | 2016-01-15 | Debugging system for secondary radar receiver |
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| Publication Number | Publication Date |
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| CN105676195A true CN105676195A (en) | 2016-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610028178.6A Pending CN105676195A (en) | 2016-01-15 | 2016-01-15 | Debugging system for secondary radar receiver |
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| CN (1) | CN105676195A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106199526A (en) * | 2016-06-27 | 2016-12-07 | 芜湖航飞科技股份有限公司 | A kind of secondary radar receiver noise trap |
| CN112255598A (en) * | 2020-10-14 | 2021-01-22 | 四川九洲空管科技有限责任公司 | FPGA remote online debugging method, device and system based on optical fiber communication |
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| CN201421501Y (en) * | 2009-06-12 | 2010-03-10 | 阴大兴 | Secondary radar universal detector |
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| GB2477103A (en) * | 2010-01-21 | 2011-07-27 | Qinetiq Ltd | Passive monitoring of Mode S radar ground stations |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106199526A (en) * | 2016-06-27 | 2016-12-07 | 芜湖航飞科技股份有限公司 | A kind of secondary radar receiver noise trap |
| CN112255598A (en) * | 2020-10-14 | 2021-01-22 | 四川九洲空管科技有限责任公司 | FPGA remote online debugging method, device and system based on optical fiber communication |
| CN112255598B (en) * | 2020-10-14 | 2023-09-26 | 四川九洲空管科技有限责任公司 | FPGA remote online debugging method, device and system based on optical fiber communication |
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Application publication date: 20160615 |
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