CN105634861A - New type serial error code tester - Google Patents

Abstract

The invention discloses a novel serial bit error tester, which is characterized in that it includes: a clock synthesis module, which generates a reference clock signal of 100MHz-12.5GHz; a bit error detection module, which collects bit error information; and is integrated in FPGA; The graphics sequence generation module takes the reference clock signal as a reference, generates a data sequence with bit error information according to the collected bit error information, and the graphic format of the data sequence has multiple; the main control module is used for the clock synthesis module, The error code detection module and the programmable graphic sequence generation module perform data interaction and control. The serial bit error tester designed based on FPGA in the invention is a continuously variable rate bit error tester, which can be oriented to a serial information transmission system with variable data transmission rate and interface level.

Description

A new type of serial bit error tester

technical field

The invention relates to the technical field of communication, in particular to a novel serial code error tester.

Background technique

Looking at the development process of data transmission, at first it was serial, then parallel, and now it is back to serial. Today, serial technology has become the dominant technology in data transmission systems, whether it is disk interface, system bus, chip interconnection, or buses such as USB, IEEE1394, PCIExpress, RapidIO, FC (Fiber Channel), etc., are used without exception. A serial bus was introduced to improve performance, and the traditional parallel bus technology was almost eliminated. High-speed serial transmission technology is more and more popular in the market due to its high transmission rate and convenient interface. Various high-speed serial transmission standards emerge in an endless stream. The transmission rate of the serial bus has exceeded 10Gb/s, and the interface levels are also different. .

However, behind the increase in transmission rate is the increase in the difficulty of designing transmission paths and new challenges in testing transmission systems, such as accurate transmission error measurement, more accurate signal quality analysis, etc., to ensure that the full picture of high-speed signal transmission can be analyzed, Provide reference for the design, verification and troubleshooting of serial bus devices, so as to effectively evaluate and predict the data transmission performance of devices and systems.

With the rapid development of serial transmission technology, the serial bit error tester serving it is also growing rapidly. In order to adapt to the test of higher-speed serial transmission, it is necessary to build a more complete high-speed serial transmission test solution, and expand to provide more test functions, including: jitter, drift, delay and compatibility with more serial transmission standards etc., to form a complete comprehensive testing capability for signal integrity and serial transmission performance testing. Higher test rate and more complete signal analysis capability are the future development trend of serial bit error tester.

Contents of the invention

The purpose of the present invention is to overcome or alleviate at least part in the above-mentioned shortcoming, a kind of novel serial bit error tester is provided hereby, it is characterized in that comprising:

Clock synthesis module, which generates a reference clock signal from 100MHz to 12.5GHz;

A bit error detection module collects bit error information;

The programmable graphics sequence generation module takes the reference clock signal as a reference, generates a data sequence with bit error information according to the collected bit error information, and the graphic format of the data sequence has multiple types;

The main control module is used for data interaction and control of the clock synthesis module, error code detection module and programmable graphic sequence generation module.

Preferably, the clock synthesis module includes

Low-frequency integrated phase-locked loop, which inputs a 10MHz clock signal and outputs a 50MHz-100MHz clock signal;

High-frequency integrated phase-locked loop, which inputs a clock signal of 50MHz to 100MHz and outputs a clock signal of 100MHz to 4000MHz;

A shaping drive circuit, which inputs a clock signal of 100MHz to 4000MHz;

A plurality of different frequency multiplication circuits, which respectively input clock signals of 100MHz-4000MHz, and respectively output clock signals of 100MHz-4000MHz, 4GHz-8GHz and 8GHz-12.5GHz;

The high-speed multiplex switch selects the output of any one of multiple different frequency multiplier circuits; the high-speed multiplex switch is controlled by the main control module through the bus.

Preferably, the programmable graphics sequence generation module includes:

The clock management circuit receives the reference clock signal output by the clock synthesis module, and generates clock signals of each frequency band according to the reference clock signal, and the generation of clock signals of each frequency band is controlled by the main control module through the bus;

A character pattern generator, which is controlled by the main control module to generate editable word patterns in various graphic formats through the bus, and inserts bit error code information into the editable word pattern;

A PRBS graphic generator, which is controlled by the main control module to generate pseudo-random graphics in multiple graphic formats, and inserts bit error code information in the pseudo-random graphics;

A serial-to-parallel conversion circuit, which converts the data sequence of the editable word graphics or pseudo-random graphics, from serial data to parallel data;

The time delay circuit converts the data sequence of the editable word graphics or pseudo-random graphics into parallel data, performs amplitude program control, offset program control and output impedance conversion, and then outputs it.

Preferably, the bit error detection module includes:

The interface circuit receives the digital signal of the system under test in the form of optical signal or electrical signal;

a decoding circuit, for decoding the digital signal;

A local sequence pattern generator, outputting a local data sequence of a pre-stored local word pattern or a local pseudo-random pattern;

The bit error detection circuit compares the decoded digital signal with the local data sequence to realize the bit error analysis of the digital signal;

The capture storage circuit saves the result of bit error analysis of the digital signal for calling by the main control module.

In addition, the capture and storage circuit captures the data sequence of the decoded digital signal, and only filters and stores the data sequence including bit error information.

Further, the error detection circuit includes:

Extraction circuits to extract different kinds of data sequences;

The operation circuit performs operations on the data sequence to obtain intermediate results;

The intermediate results are stored in DPRAM to store the intermediate results of different data sequences;

The extraction circuit, the arithmetic circuit and the intermediate result storage DPRAM communicate with the main control module through the bus.

The serial bit error tester designed based on FPGA in the invention is a continuously variable rate bit error tester, which can be oriented to a serial information transmission system with variable data transmission rate and interface level.

Description of drawings

These and other aspects of the invention will now be described in more detail with reference to the accompanying drawings, which show presently preferred embodiments of the invention. in:

Fig. 1 is the overall block diagram of the present embodiment;

Fig. 2 is the working block diagram of clock synthesis module;

Fig. 3 is the working block diagram of programmable graphics sequence generation module;

Fig. 4 is the working block diagram of bit error detection module;

Figure 5 is a working block diagram of the capture circuit.

detailed description

Below in conjunction with accompanying drawing and specific example, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention All modifications of the valence form fall within the scope defined by the appended claims of the present application.

As shown in Figure 1, a new type of serial bit error tester, which includes integrated in the FPGA: a clock synthesis module to generate a reference clock signal of 100MHz ~ 12.5GHz; The code error information is detected; the programmable graphic sequence generation module takes the reference clock signal as a reference, and generates a data sequence with bit error code information according to the collected bit error code information. There are various graphic formats for the data sequence; the main control module, It is used for data interaction and control of clock synthesis module, error code detection module and programmable graphic sequence generation module.

Through the above design scheme, the new serial bit error tester involved in this embodiment forms modules based on FPGA to collect and detect bit error information in real time, and the reference clock signal at 100MHz～12.5GHz is used as a reference condition Under this condition, the bit error information of the digital signal can be detected, and it is suitable for digital signals transmitted at various rates.

Preferably as shown in Figure 2, the clock synthesis module includes a low-frequency integrated phase-locked loop, which inputs a 10MHz clock signal and outputs a 50MHz-100MHz clock signal; a high-frequency integrated phase-locked loop, which inputs a 50MHz-100MHz clock signal and outputs 100MHz～4000MHz clock signal; shaping drive circuit, which inputs 100MHz～4000MHz clock signal; multiple different frequency multiplication circuits, which respectively input 100MHz～4000MHz clock signal, and output 100MHz～4000MHz, 4GHz～8GHz and 8GHz respectively ～12.5GHz clock signal; high-speed multi-channel selection switch, selects the output of any one of multiple frequency multiplication circuits; the high-speed multi-channel selection switch is controlled by the main control module through the bus. Combined with the above design scheme, since the frequency needs to be continuously variable within the range of 100MHz to 12.5GHz, and has high frequency stability, resolution and spectral purity, this embodiment uses a low-frequency integrated phase-locked loop and a high-frequency integrated Phase-locked loop frequency synthesis is used to realize continuously variable clock generation. In addition, considering the large span of the clock frequency, it should be implemented in a segmented manner, that is, the clock frequency is divided into three segments by multiple frequency multipliers. Among them, the 100MHz-4000MHz clock can be directly generated by the post-stage PLL, while the 4GHz-8GHz and 8GHz-12.5GHz clocks in the higher frequency bands are generated by 2 or 4 frequency multiplication.

As shown in Figure 3, the clock management circuit of this embodiment adopts high-speed, broadband digital phase-locked loop technology and synchronous frequency division and multiplication technology to generate various clock signals required by the system;

Word pattern generator and PRBS pattern generator, according to the settings of the user in the main control module, generate a variety of pseudo-random patterns and programmable word patterns, and can perform pattern format conversion and error code insertion;

Due to the high speed and continuous adjustable, the generation of pseudo-random graphics and programmable word graphics needs to be realized by a special method, that is, using parallel processing, firstly generating n-way pseudo Random graphics, the rate of each graphics is only 1/n of the clock frequency, and then synthesize one graphics through the graphics synthesizer;

The delay output drive circuit mainly completes the equalization processing, amplitude programming, offset programming and output impedance transformation of the output signal, so as to realize the requirements of adjustable rate and level of high-speed digital signal.

As shown in Figure 4, the error detection circuit is mainly composed of optical/electrical interface circuit, input drive, clock recovery and distribution, delay adjustment, serial-to-parallel conversion, line decoding, local graphics sequence generation, sequence synchronization, error detection, capture Memory and other circuit components.

Among them, the clock recovery and distribution circuit mainly uses integrated phase-locking technology to recover the clock signal from the received digital signal, and performs clock distribution management. The rest of the circuit components are all necessary to realize the bit error detection circuit, which is mainly convenient for this embodiment to detect the bit error information of the system under test by comparing the received data sequence with the local data sequence, and to detect the bit error information of the transmission signal The quality of the input data is evaluated, and the bit error analysis of the input data is completed, so it will not be described in detail.

In this embodiment, the capture and storage circuit captures the data sequence of the decoded digital signal, and only filters and then stores the data sequence including the bit error information, so as to detect the bit error information and store efficiency.

Specifically as shown in Figure 5, the capture storage circuit of the present embodiment is mainly composed of filter, sequence length counter, sequence length/filtering result buffer FIFO, DDR write count, comparator, DDR manager, input data buffer FIFO, DDR, DDR interface circuit , 2 choose 1 and other circuits.

The capture circuit mainly adopts DDR as the data memory to meet the high-speed data access, and in order to improve the capture efficiency, this embodiment adopts the instant capture method of capturing first and then filtering, which can save the delay circuit required for filtering and overcome Usually, the delayed capture method of filtering first and then capturing takes up too many resources. The core of this scheme is to add control characters before and after the unfiltered data sequence, and always write it into the memory, and record the first and last storage addresses of the data sequence at the same time, judge the filter information of the sequence after the data sequence is written, if it matches, then Continue to capture from the stored address of the data sequence that has been written, otherwise restart from the beginning of the data sequence to store the address.

Claims (5)

1. A novel serial bit error tester, characterized in that it comprises: Clock synthesis module, which generates a reference clock signal from 100MHz to 12.5GHz; A bit error detection module collects and detects bit error information; The programmable graphics sequence generation module takes the reference clock signal as a reference, generates a data sequence with bit error information according to the collected bit error information, and the graphic format of the data sequence has multiple types; The main control module is used for data interaction and control of the clock synthesis module, the error detection module and the programmable graphic sequence generation module. 2. novel serial bit error tester according to claim 1, is characterized in that, The clock synthesis module includes, Low-frequency integrated phase-locked loop, which inputs a 10MHz clock signal and outputs a 50MHz-100MHz clock signal; High-frequency integrated phase-locked loop, which inputs a clock signal of 50MHz to 100MHz and outputs a clock signal of 100MHz to 4000MHz; A shaping drive circuit, which inputs a clock signal of 100MHz to 4000MHz; A number of different frequency multiplication circuits input clock signals of 100MHz~4000MHz respectively, and output clock signals of 100MHz~4000MHz, 4GHz~8GHz and 8GHz~12.5GHz respectively; The high-speed multiplex switch selects the output of any one of multiple different frequency multiplier circuits; the high-speed multiplex switch is controlled by the main control module through the bus. 3. novel serial bit error tester according to claim 1, is characterized in that, The programmable graphics sequence generation module includes: The clock management circuit receives the reference clock signal output by the clock synthesis module, and generates clock signals of each frequency band according to the reference clock signal, and the generation of clock signals of each frequency band is controlled by the main control module through the bus; A character pattern generator, which is controlled by the main control module to generate editable word patterns in various graphic formats through the bus, and inserts bit error code information into the editable word pattern; A PRBS graphic generator, which is controlled by the main control module to generate pseudo-random graphics in multiple graphic formats, and inserts bit error code information in the pseudo-random graphics; A serial-to-parallel conversion circuit, which converts the data sequence of the editable word graphics or pseudo-random graphics, from serial data to parallel data; The time delay circuit converts the data sequence of the editable word graphics or pseudo-random graphics into parallel data, performs amplitude program control, offset program control and output impedance conversion, and then outputs it. 4. novel serial bit error tester according to claim 1, is characterized in that, described bit error detection module comprises: The interface circuit receives the digital signal of the system under test in the form of optical signal or electrical signal; The decoding circuit decodes the received digital signal; A local sequence pattern generator, outputting a local data sequence of a pre-stored local word pattern or a local pseudo-random pattern; The bit error detection circuit compares the decoded digital signal with the local data sequence to realize the detection of the digital signal; The capture storage circuit saves the result of bit error analysis of the digital signal for calling by the main control module. 5. The novel serial bit error tester according to claim 4, wherein the capturing and storing circuit captures the data sequence of the decoded digital signal, and only filters and stores the data sequence including the bit error information.