CN105609506A - Split gate flash memory structure - Google Patents

Abstract

The invention relates to the technical field of fabrication of a semiconductor, in particular to a split gate flash memory structure. The lower surface of a control gate which is partially arranged on a horizontal part of an L-shaped word line gate is lower than the upper surface of a floating gate, thus, the control gate and the floating gate have partial longitudinal overlapped region to increase the coupling area of the control gate and the floating gate, the coupling coefficient of the control gate on the floating gate is increased, and the flash memory program efficiency is further improved; a corner of an erase gate near to the floating gate is a round angle, thus, a tunneling oxide layer with uniform thickness and relatively high quality can be formed during subsequent film forming, and the phenomenon of erase degradation is improved; and meanwhile, the horizontal part of the T-shaped structured erase gate is arranged on a part of the floating gate, so that the erase gate and the floating gate have partial horizontal overlapped region to increase the coupling area of the erase gate and the floating gate, and the coupling coefficient of the erase gate on the floating gate is increased.

Description

Split Gate Flash Memory Structure

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a split-gate flash memory structure.

Background technique

Currently, in a flash memory with a split gate structure, program efficiency and erasing speed are two important quality indicators. The coupling coefficient of the control gate (Controlgate) to the floating gate (floating gate) plays a vital role in the writing speed; under the same operating conditions, a higher coupling coefficient can bring a faster writing speed; and The dielectric strength of the tunnel oxide layer between the floating gate and the erase gate is critical to the degradation of erase performance.

The existing technology is based on the traditional capacitor structure, that is, the planar upper and lower plates, to realize the coupling effect of the control gate to the floating gate, and to provide the floating gate with the voltage necessary for source-side hot electron injection (Source-side hotel electron injection). The coupling efficiency (coefficient) is limited by the plate spacing, the coupling area and the dielectric constant of the intermediate medium. It is difficult to increase the coupling coefficient while maintaining the spacing and dielectric constant.

In flash memory with a split gate structure, erasing is achieved through the polysilicon to polysilicon Fowler-Nordheim electron tunneling effect (poly-to-polyFowler-Nordheim electron tunneling) between the floating gate and the erase gate. At the corner of the floating gate and erase gate contacts. When erasing (Erase), under the action of an electric field, electron tunneling occurs at the corner of the floating gate, and each time the electrons are erased, they must pass through the tunneling oxide layer. If the intrinsic quality of the oxide layer is poor, then in the strong Under the action of an electric field, the tunnel oxide will be damaged after many cycles, and the erasing speed will gradually slow down (Erasedegradation). Under the current structural model, the shape of the corner of the floating gate is relatively sharp. In the subsequent process, the film quality and thickness uniformity of the tunnel oxide layer are likely to be poor, and a strong electric field will be formed during erasing, which will damage the oxide layer. , resulting in a decline in erasing speed. These are unexpected to those skilled in the art.

Contents of the invention

In view of the above existing problems, the present invention discloses a split-gate flash memory structure, including:

The substrate is provided with an active region and a drain region;

an erasing gate disposed above the source region;

a divided gate structure disposed on the substrate between the source region and the drain region, the divided gate structure includes a floating gate, a control gate and an L-shaped word line gate including a horizontal part and a vertical part, And the upper surface of the horizontal portion of the L-shaped word grid is lower than the upper surface of the floating gate;

Wherein, the control gate is disposed above the floating gate and the horizontal portion of the L-shaped word line grid, and the lower surface of the control gate partially located above the horizontal portion of the L-shaped word line grid is lower than the horizontal portion of the L-shaped word line grid. On the upper surface of the floating gate, the control gate and the floating gate have a partial vertical overlapping area, so as to increase the coupling area between the control gate and the floating gate.

In the above split-gate flash memory structure, the horizontal portion of the L-shaped word line gate is 180-220 angstroms thinner than the thickness of the control gate.

In the above split-gate flash memory structure, the material of the L-shaped word line gate is polysilicon or metal.

In the above split-gate flash memory structure, the floating gate is a square structure, and the corners of the floating gate adjacent to the erasing gate are rounded.

In the above split-gate flash memory structure, wherein the shape of the erase gate is a T-shaped structure including a horizontal part and a vertical part, and the horizontal part of the T-shaped structure is located on part of the floating gate so that the erase gate The erasing gate and the floating gate have a partial horizontal overlapping area, so as to increase the coupling area between the erasing gate and the floating gate.

In the above split-gate flash memory structure, a tunnel oxide layer is provided between the sub-gate structure and the erasing gate.

In the above split-gate flash memory structure, a gate dielectric layer is disposed between the L-shaped word line gate and the substrate.

In the above split-gate flash memory structure, the material of the gate dielectric layer is silicon dioxide or a material with a high dielectric constant.

The above invention has the following advantages or beneficial effects:

The invention discloses a split-gate flash memory structure, by setting the lower surface of the control gate partly above the horizontal part of the L-shaped word line gate to be lower than the upper surface of the floating gate so that the control gate and the floating gate have a partial longitudinal overlap area, to increase the coupling area of the control gate and the floating gate, thereby improving the coupling coefficient CR (couplingratio) of the control gate to the floating gate, thereby improving the flash memory writing efficiency; and by setting the corner of the floating gate adjacent to the erasing gate as a circle angle, so that a tunnel oxide layer with uniform thickness and high quality can be formed in the subsequent film formation, which improves the erasing degradation phenomenon; The erasing gate and the floating gate have a partial horizontal overlapping area to increase the coupling area of the erasing gate and the floating gate, thereby increasing the coupling coefficient of the erasing gate to the floating gate.

Description of drawings

The invention and its characteristics, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings may not be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

FIG. 1 is a schematic structural diagram of a split-gate flash memory structure in Embodiment 1 of the present invention;

FIG. 2 is a schematic structural diagram of a split-gate flash memory structure in Embodiment 2 of the present invention.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Embodiment one:

As shown in FIG. 1, this embodiment relates to a split-gate flash memory structure, which includes a substrate 1 provided with a source region 22 and a drain region 21, an erasing gate 7 disposed on the source region 22, and A divided gate structure on the substrate 1 between the source region 22 and the drain region 21, and the divided gate structure includes a floating gate 5, a control gate 6 and an L-shaped word line gate 4 including a horizontal part and a vertical part , and the upper surface of the horizontal portion of the L-shaped word line grid 4 is lower than the upper surface of the floating gate; wherein, the control gate 6 is arranged above the floating gate 5 and the horizontal portion of the L-shaped word line grid 4, and partly located in the L-shaped The lower surface of the control gate 6 above the horizontal portion of the word line gate 4 is lower than the upper surface of the floating gate 5 so that the control gate 6 and the floating gate 5 have a partial vertical overlapping area (that is, the control gate 6 partially surrounds the floating gate 5 vertically) , to increase the coupling area of the control gate 6 and the floating gate 5, thereby improving the coupling coefficient of the control gate 6 to the floating gate 5, and then improving the writing efficiency of the flash memory, wherein, setting the L-shaped word line gate can reduce the word line gate 4 The thickness of the horizontal part releases space for the partial longitudinal overlapping region formed by the control gate 6 and the floating gate 5 . In the embodiment, compared with the conventional technology, the areas of the control gate 6 and the floating gate 5 in the horizontal plane remain unchanged.

On this basis, further, the horizontal portion of the L-shaped word wire grid 4 is 180-220 angstroms thinner than the thickness of the control grid 6 (for example, 180 angstroms, 190 angstroms, 200 angstroms or 220 angstroms, etc.).

In a preferred embodiment of the present invention, the material of the L-shaped word wire grid 4 is polysilicon or metal.

In a preferred embodiment of the present invention, a gate dielectric layer 3 is provided between the above-mentioned L-shaped word wire grid 4 and the substrate 1 .

On this basis, further, the material of the gate dielectric layer 3 can be silicon dioxide or a high dielectric constant material, so that the threshold voltage (Vt) can be optimized and the select gate (select gate, SG for short) can be significantly reduced. (The selection gate is the word line gate) gate dielectric leakage current.

In a preferred embodiment of the present invention, a tunnel oxide layer 8 is provided between the above-mentioned sub-gate structure and the erasing gate 7 .

In a preferred embodiment of the present invention, the above-mentioned erasing gate 7 may be T-shaped.

In a preferred embodiment of the present invention, tunneling is provided between the above sub-gate structure and the erasing gate 7 (it can also be said to be between the stacked structure formed by the floating gate 5 and the control gate 6 and the erasing gate 7). Oxide layer 8.

In a preferred embodiment of the present invention, the above-mentioned floating gate 5 may have a square structure.

In addition, the present invention increases the coupling area of the control gate 6 and the floating gate 5, which can increase the coupling coefficient of the control gate to the floating gate, thereby improving the writing efficiency of the flash memory. The principle is as follows:

1. The principle of increasing the coupling coefficient:

$\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; G</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; G</span>}}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; \&Element;</span>\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; c</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}\mathrm{<span\; class="notranslate">\; G</span>}}$

Where ∈ is a constant, d is the distance between the plates (control gate and floating gate), C _FG is the capacitance of the floating gate, and S is the area of the plates. When ∈, d, and C _FG are all constant, the value of CR can be increased by changing S .

2. Increase the coupling coefficient to increase the writing speed Principle:

In flash memory with a split gate structure, data is written through source-side hot electron injection (Source-side hot electron injection). There must be a voltage on the floating gate. Under the same external operating conditions, a higher coupling coefficient Can bring faster writing speed.

Embodiment two:

As shown in Figure 2, this embodiment is roughly the same as Embodiment 1, the only difference is that in this embodiment, the corners of the floating gate 5 adjacent to the erasing gate 7 are set as rounded corners, so that in the subsequent film formation, a film with uniform thickness and high quality can be formed. The high tunnel oxide layer 8 improves the phenomenon of erasing degradation; however, the smooth floating gate shape makes the coupling area between the floating gate 5 and the erasing gate 7 smaller, resulting in a gap between the erasing gate 7 and the floating gate 5 The coupling coefficient between them is reduced; in order to make up for this loss, at the same time, the shape of the erasing gate 7 in this embodiment is set as a T-shaped structure including a horizontal part and a vertical part, and the horizontal part of the T-shaped structure is located on part of the floating gate 5 In addition, the erasing gate 7 and the floating gate 5 have a partial horizontal overlapping area, so as to increase the coupling area between the erasing gate 7 and the floating gate 5 , thereby improving the coupling coefficient of the erasing gate 7 to the floating gate 5 .

In this embodiment, part of the horizontal overlapping area between the erasing gate 7 and the floating gate 5 will cause the horizontal overlapping area between the control gate 6 and the floating gate 5 to be reduced. 5 has a partial vertical overlapping area, so the coupling coefficient of the control gate 6 to the floating gate 5 can be maintained.

Those skilled in the art should understand that those skilled in the art can implement variations by combining the existing technology and the foregoing embodiments, and details are not described here. Such variations do not affect the essence of the present invention, and will not be repeated here.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Within the scope of the technical solution of the invention, many possible changes and modifications can be made to the technical solution of the present invention by using the methods and technical content disclosed above, or be modified into equivalent embodiments with equivalent changes, which does not affect the essence of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. a separate type flash memory in grating structure, is characterized in that, comprising:

Substrate, is provided with source region and drain region;

Erase gate, is arranged on described source region;

Grid dividing structure, is arranged on the described substrate between described source region and drain region described pointGrid structure comprises floating boom, control gate and comprises the L of a horizontal component and a vertical componentShape word wiregrating, and upper lower than described floating boom of the upper surface of the horizontal component of described L shaped word wiregratingSurface;

Wherein, described control gate is arranged at the horizontal component of described floating boom and described L shaped word wiregratingOn, and part be positioned at described control gate on the horizontal component of described L shaped word wiregrating underIt is vertical that surface makes described control gate and described floating boom have part lower than the upper surface of described floating boomTo overlapping region, to increase the coupling area of described control gate and described floating boom.

2. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inThe horizontal component of L shaped word wiregrating is than the thin thickness of described control gate 180～220 dusts.

3. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inThe material of L shaped word wiregrating is polysilicon or metal.

4. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inFloating boom is cube structure, and the turning that described floating boom closes on described erase gate is set to fillet.

5. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inErase gate be shaped as the T shape structure that comprises horizontal component and vertical component and described T shapeThe horizontal component of structure is positioned at and on the described floating boom of part, makes described erase gate and described floating boomThere is part of horizontal overlapping region, to increase the coupling area of described erase gate and described floating boom.

6. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inBetween grid dividing structure and described erase gate, be provided with tunneling oxide layer.

7. separate type flash memory in grating structure as claimed in claim 1, is characterized in that, described inBetween L shaped word wiregrating and described substrate, be provided with gate dielectric layer.

8. separate type flash memory in grating structure as claimed in claim 7, is characterized in that, described inThe material of gate dielectric layer is silica or high dielectric constant material.