CN105511984B - A kind of processor and fault-tolerance approach with fault-tolerant architecture based on active link [HTML] Backup Data - Google Patents
A kind of processor and fault-tolerance approach with fault-tolerant architecture based on active link [HTML] Backup Data Download PDFInfo
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Abstract
The invention discloses a kind of processor fault-tolerance structure and method based on active link [HTML] Backup Data, including Pyatyi flowing structure, flowing water control module, check code module, PC registers and enhanced register file REF；The fault-tolerant architecture carries out dynamic monitoring to source operand and target operand, if source operand and target operand are equal and storage address is different, establishes backup link for both, and linking relationship is stored in enhanced register file REF；Source operand and source, the linking relationship of target operand are read out at the same time in execution process instruction, if there is mistake in some source operand, its corresponding backup linking relationship is then utilized, the Backup Data identical with source operand is read and carries out follow-up processor operation.Processor structure disclosed by the invention takes full advantage of the data redundancy backup in different registers unit, improves the reliability of processor by Dynamic Maintenance data backup linking relationship table.
Description
Technical field
The invention belongs to microprocessor reliability field, is related to a kind of fault-tolerant architecture and method of architecture level, specifically
It is related to a kind of processor fault-tolerance structure and method based on active link [HTML] Backup Data.
Background technology
Register file keeps in node as the data between cache and processor functional component, and there are data to preserve
Time length and accessed high two distinguishing features of frequency, These characteristics not only add the simple grain of register file internal data
Son upset probability, and propagation of the wrong data in processor is accelerated, so as to easily cause the failure of system task, therefore
Register file is one of storage organization most sensitive to single particle effect inside processor.
In order to improve the reliability of data in register file, current major programme includes：(1) side based on full custom
Method designs the register file of Flouride-resistani acid phesphatase, specifically refers to document《A kind of 10, which read 6 radiation hardenings for writing register file, sets
Meter》With《The Design of Reinforcement of 32 × 32 three port register heaps》Deng；(2) data in register file are compiled using EDAC
Code, specifically refers to document《A kind of synchronous error correction the pipeline design for SEU》、《A radiation hardened by
design register file with lightweight error detection and correction》And the patent No.
For the patent of ZL200510043107.5《The implementation method of five-level tolerant flowing structure in the integer unit of microprocessor》Deng；
(3) backup of sensitive data is realized using idling-resource, the program belongs to research hotspot in recent years, specifically refers to document
《Using register lifetime predictions to protect register files against soft
errors》、《Increasing register file immunity to transient errors》、《An efficient
technique to tolerate MBU faults in register file of embedded processors》Deng.
The development process of scheme (1) needs modeling to put forward ginseng and Optimized Iterative, and the cycle is longer, and Flouride-resistani acid phesphatase structure can not be kept away
Introducing extra power consumption and accessing for exempting from is delayed；Once the error accumulation in register file exceedes the error correction and detection ability of EDAC,
Protection mechanism based on scheme (2) is then ineffective；And scheme (3) is directed to developing the idle storage money inside register file
Source, backs up sensitive data using idling-resource, but develops, is relatively large using the cost of idling-resource, usually leads
Cause processor performance reduction, power consumption increase etc..
Scheme (1), (2) do not consider the situation when data in different register file cells are identical with (3), i.e., not
When considering that the data in register file have redundancy backup.
The content of the invention
For problems of the prior art, the present invention provides a kind of processor based on active link [HTML] Backup Data and holds
Wrong structure and method.Detected inside processor the input source operand of ALU it is consistent with output target operand and both
When storage address in register file is different, then establish the link therebetween, this link makes both backup each other, when it
In any one part of data when there is abnormal or mistake, use another data to complete follow-up processor and operate.
The present invention is to be achieved through the following technical solutions：
A kind of processor fault-tolerance structure based on active link [HTML] Backup Data, including Pyatyi flowing structure, flowing water control mould
Block, check code module, PC registers and enhanced register file REF；
Pyatyi flowing structure includes fetching module I F, decoding module ID, execution module EX, storage access module MA, adaptive
Answer write-back modules A WB and four groups of level inter-registers；Five modules in Pyatyi flowing structure between level inter-register FD, level by posting
Storage DE, level inter-register EM and level inter-register MW are sequentially connected, and wherein fetching module I F is located at Pyatyi flowing structure first place,
Adaptive write-back modules A WB is at end；
The output copy inquiry control signal of adaptive write-back modules A WB is connected to decoding module ID, is used for realization exception
In the case of source operand copy inquiry；The output of adaptive write-back modules A WB is connected to the input of PC registers, is used for realization
Processor abnormal patterns give an order the write operation of PC；The output order PC of PC registers is connected to fetching module I F；PC registers
Output and copy inquiry control signal realize inquiry, reading and use of the processor to redundancy backup data jointly；
Flowing water control module is connected with the Enable Pin of level inter-register FD, DE, EM and MW, for being made according to processor state
The sampling of energy or prohibitive levels inter-register；
Check code module encodes input data according to error correction and detection coding rule, export as input data and
Its check code；The input of check code module comes from adaptive write-back modules A WB, and output is connected to enhanced register file
The write port of REF；
Enhanced register file ERF has four to write five readings totally nine ports, and each port is necessary comprising realization read-write
Control signal；All read ports are connected with decoding module ID；
Whether decoding module ID detects its signal inquiry flag bit inputted in copy inquiry control signal first effective；Translate
Code module I D is by the feedback information of five read ports, and information and other information in copy inquiry control signal are to level inter-register
DE is transmitted；The feedback information of five read ports includes first, second source operand and check code SP1, SP2, and first, second
Source operand copy information SC1, SC2 and target operand copy information DC；
Level inter-register DE is under the control of flowing water control module, and after the output of above-mentioned decoding module ID is deposited, output is extremely
Execution module EX；
Execution module EX includes with detection and compares the enhanced ALU of ability, is operated according to first, second source of input
Number and check code SP1, SP2 verify the correctness of source operand；Arithmetic is carried out according to first, second source operand at the same time
Or logical operation obtains the target operand as operation result, final relatively first, second source operand and target operand
It is whether equal, when data are equal and storage address is different, then output support backup comparative result, otherwise export do not support it is standby
The comparative result of part；Execution module EX by two comparative results CRA and CRB of first, second source operand, target operand and
Other undressed inputs are further exported to level inter-register EM；
Level inter-register EM is under the control of flowing water control module, and after the output of above-mentioned execution module EX is deposited, output is extremely
Storage access module MA；
Storage access module MA, completes to access the operation of memory, and further transmits the module to level inter-register MW
Output；
Level inter-register MW is defeated after the output of above-mentioned storage access module MA is deposited under the control of flowing water control module
Go out to adaptive write-back modules A WB；
Adaptive write-back modules A WB completes the write operation inside processor, when source operand is incorrect, will instruct at present
PC write-in PC registers, while to copy inquiry control signal be configured；In the presence of without exception, enhanced deposit is completed
The write operation of device file ERF.
Preferably, enhanced register file ERF, including data register file and control register file, Liang Zhecun
The number of storage unit is identical and corresponds, but bit wide is different；The operand of data register file store instruction and its school
Code is tested, and wherein three ports of enhanced register file ERF are used alone by data register file；Control register
The link information of file storage Backup Data includes copy address and flag bit, and copy flag bit indicates the operand of current accessed
With the presence or absence of Backup Data, copy address indicates storage address of the Backup Data in data register file；Enhanced register
Remaining six port of file ERF are used alone by control register file.
Further, the operand of data register file store instruction includes calculating required source operand and calculating completing
Target operand afterwards.
Further, wherein three ports of enhanced register file ERF are target operand data write port WD, first
Source operand data read port RS1 and the second source operand data read port RS2；Enhanced register file ERF remaining six
A port is the first source operand control information read port RCS1, the second source operand control information read port RCS2, target behaviour
Control information of counting read port RCD, target operand control information write port WCD, the first source operand control information write port
WCS1 and the second source operand control information write port WCS2.
Preferably, execution module EX, including the first source operand correction verification module, the second source operand correction verification module, ALU,
First comparator and the second comparator, the first source operand correction verification module carry out the first source operand and its check code of input
Verification, and check results are connected to first comparator；Second source operand correction verification module to the second source operand of input and
Its check code is verified, and check results are connected to the second comparator；First source operands and second source of the ALU to input
Operand carries out arithmetic or logical operation, and output target operand is connected to first and second comparator and level inter-register EM；
The input of first and second comparator further includes first and second source operand, and two comparators grasp first and second source according to check results
Count and judged with the equality of target operand, if check results are abnormal, without comparing, directly pass through CRA and CRB
Output verification is abnormal, if check results are normal, compare first and second source operand and whether target operand is equal, compare knot
Fruit is equally provided by CRA and CRB.
Preferably, copy inquiry control signal includes the copy address of inquiry flag bit and first, second source operand；Look into
Ask flag bit to promote backward with assembly line from decoding module ID, until adaptive write-back modules A WB is reset.
Preferably, four write ports are respectively that target operand data write port WD, target operand control information write end
Mouth WCD, the first source operand control information write port WCS1, wherein the second source operand control information write port WCS2, target
Operand data write port WD is by the output driving of check code module, three control information write ports WCD, WCS1 and WCS2
Output with adaptive write-back modules A WB is connected；Five read ports are respectively the first source operand data read port RS1,
Two source operand data read port RS2, the first source operand control information read port RCS1, the second source operand control information are read
Port RCS2 and target operand control information read port RCD.
Preferably, whether effective decoding module ID detects its signal inquiry flag bit inputted in copy inquiry control signal
When；If it is effective to inquire about flag bit, to inquiring about copy address specified data register file in control signal included in copy
In unit carry out read operation, while the input for the decoding module ID that the output with control register file is connected is set to
0；If inquiring about, flag bit is invalid, and the instruction to level inter-register FD outputs is parsed into row decoding, and according to decoding as a result, at the same time
Read operation is initiated to five read ports of enhanced register file ERF, so as to obtain first, second source operand and check code
SP1, SP2, first, second source operand copy information SC1, SC2 and target operand copy information DC.
A kind of method of the processor fault-tolerance structure of the active link [HTML] Backup Data based on described in more preferable scheme, wherein
The adaptive write-back modules A WB, inputs the judgement of information progress write operation according to it, comprises the following steps that：
Step1：Judge whether the source operand that current processor uses is correct, if mistake, turns to Step2；Otherwise, turn
To Step4；
Step2；Current instruction PC is write into PC registers, and judge current erroneous source operand whether Backup Data
Whether effective with judging to inquire about flag bit, if Backup Data, inquiry flag bit is effective, then it is invalid to inquire about mark position, and
Turn to Step3；Otherwise data are not backed up, inquiry flag bit is invalid, and the inquiry flag bit put in copy inquiry control signal is effective,
And control signal is inquired about into by copy in the copy address for the source operand that malfunctions and passes to decoding module ID；
Step3：There is the mistake that can not recover in source operand, and processor enters abnormal patterns；
Step4：It will then inquire about that mark position is invalid, to the comparative result CRA of first and second source operand and target operand
Judged with CRB, if CRA or CRB shows that source operand is identical with target operand, turn to Step5；Otherwise turn to
Step8；
Step5：Whether effective detect the copy flag bit of target operand, if invalid, turn to Step6；Otherwise turn to
Step7；
Step6；The address of target operand is written to the corresponding control register file unit of source operand address, will
The address of source operand is written to the corresponding control register copy address field in target operand address, while puts corresponding unit
Copy flag bit is effective, turns to Step9；
Step7：The copy mark position of the corresponding control register file unit in target operand address is invalid, at the same time
The address of target operand is written to the corresponding control register file unit of source operand address, by the address of source operand
The corresponding control register copy address field in target operand address is written to, the copy flag bit of juxtaposition corresponding unit is effective,
Turn to Step9；
Step8：Whether effective detect the copy flag bit of target operand, if invalid, turn to Step9；Otherwise turn to
Step10；
Step9：The check bit of target operand is calculated, and target operand and check bit are write into target operand at the same time
The corresponding data register file unit in address, terminates；
Step10：The copy mark position of the corresponding control register file unit in target operand address is invalid, turn
To Step9.
Compared with prior art, the present invention has technique effect beneficial below：
A kind of processor fault-tolerance structure based on active link [HTML] Backup Data of the present invention, to different registers file
Identical data in unit establishes the link, and both is backuped each other, when wherein there is abnormal or mistake in any one part of data,
Follow-up processor is completed using another data to operate, which takes full advantage of the redundancy of processor internal data, greatly
Width improves the data reliability of register file.
Enhanced register file REF of the present invention, on the premise of keeping data register file constant, increase
3 read the 3 control register files for writing six ports, for dynamically keeping the linking relationship between Backup Data, can be complete parallel
The backup information inquiry of Cheng Yuan, target operand, avoid performance reduction to the full extent.
The enhanced ALU for having detection and comparing ability in execution module EX of the present invention, can be in real time to place
The data handled in reason device are compared, and there are identical data inside processor, initial mark is carried out to identical data,
So as to lay the foundation to establish the link of Backup Data.
Adaptive write-back modules A WB of the present invention, according to check results and the data backup situation of operand, intelligence
Link information in the renewal control register file of change, especially when the corresponding storage unit in target operand address is certain number
According to A backup when, it is necessary to destroy the backup link before data A, target operand address is updated by present instruction, after renewal
Through not being the Backup Data of data A, meanwhile, when mistake occurs in the source operand with Backup Data, control the weight of assembly line
Open.
The propulsion of processor pipeline and obstruction are managed collectively by flowing water control module in the present invention, check code module
Generation for write-back check code.Flowing water control module and check code module are used for the work(for aiding in this paper content of the invention
It can realize.
Brief description of the drawings
Fig. 1 is the processor fault-tolerance structure diagram based on active link [HTML] Backup Data described in present example.
Fig. 2 is the schematic diagram of the enhanced register file ERF described in present example.
Fig. 3 is that the enhanced ALU for having detection and comparing ability in the execution module EX described in present example shows
It is intended to.
Fig. 4 is the fault tolerance judgment logic flow schematic diagram of the processor based on the present invention.
Embodiment
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
Illustrated as the presently preferred embodiments using the processor of a Pyatyi flowing water in present example, and using this
Invent the processor fault-tolerance structure based on active link [HTML] Backup Data proposed.
The hardware circuit of processor is as shown in Figure 1, the processor includes Pyatyi flowing structure, flowing water control mould
Block, check code module, PC registers and enhanced register file REF；
Pyatyi flowing structure includes fetching module I F, decoding module ID, execution module EX, storage access module MA, adaptive
Answer write-back modules A WB and four groups of level inter-registers；Five modules in Pyatyi flowing structure between level inter-register FD, level by posting
Storage DE, level inter-register EM and level inter-register MW are sequentially connected, and wherein fetching module I F is located at Pyatyi flowing structure first place,
Adaptive write-back modules A WB is at end；
The output copy inquiry control signal of adaptive write-back modules A WB is connected to decoding module ID, is used for realization exception
In the case of source operand copy inquiry, wherein copy inquiry control signal include inquiry flag bit and first, second source operation
Several copy addresses, inquiry flag bit promotes backward from decoding module ID with assembly line, until adaptive write-back modules A WB is weighed
It is new to set；Another part output of adaptive write-back modules A WB is connected to the input of PC registers, is used for realization processor exception
Pattern gives an order the write operation of PC；The output order PC of PC registers is connected to fetching module I F；The output of PC registers and pair
This inquiry control signal realizes inquiry, reading and use of the processor to redundancy backup data jointly；
Flowing water control module is connected with the Enable Pin of level inter-register FD, DE, EM and MW, is mainly used for according to processor shape
State enables or the sampling of prohibitive levels inter-register；
Check code module encodes input data, exports as input according to specific error correction and detection coding rule
Data and its check code；The input of check code module comes from adaptive write-back modules A WB, and output is connected to enhanced deposit
The write port of device file REF；
Enhanced register file ERF, as shown in Fig. 2, writing 5 reading, 9 ports with 4, each port is read comprising realization
Write necessary control signal；Four write ports are respectively that target operand data write port WD, target operand control information are write
Port WCD, the first source operand control information write port WCS1, wherein the second source operand control information write port WCS2, mesh
Mark operand data write port WD by check code module output driving, three control information write port WCD, WCS1 and
Outputs of the WCS2 with adaptive write-back modules A WB is connected；Five read ports are respectively the first source operand data read port
RS1, the second source operand data read port RS2, the first source operand control information read port RCS1, the control of the second source operand
Information read port RCS2 and target operand control information read port RCD, all read ports are connected with decoding module ID；
Enhanced register file ERF, as shown in Fig. 2, including data register file and control register file, both
The number of storage unit is identical, but bit wide is different, and corresponds.The operand of data register file store instruction and its
Check code, wherein three ports of enhanced register file ERF are used alone by data register file；Data register text
The operand of part store instruction includes calculating the target operand after the completion of required source operand and calculating；Three ports point
Wei not target operand data write port WD, the first source operand data read port RS1 and the second source operand data read port
RS2；Control register file stores the link information of Backup Data, mainly includes copy address and flag bit, copy flag bit
Indicate that the operand of current accessed whether there is Backup Data, copy address instruction Backup Data depositing in data register file
Store up address；Remaining six port of enhanced register file ERF are used alone by control register file；Six port difference
For the first source operand control information read port RCS1, the second source operand control information read port RCS2, object run numerical control
Information read port RCD processed, target operand control information write port WCD, the first source operand control information write port WCS1 and
Second source operand control information write port WCS2.
Decoding module ID detect first its input signal inquiry flag bit it is whether effective, that is, inquiry copy inquiry control
Whether the wherein bit flag position in signal is effective, if inquiry flag bit is effective, to being inquired about included in copy in control signal
Unit in the specified data register file of copy address carries out read operation, while by the output phase with control register file
The input of the decoding module ID of connection is set to 0；If inquiring about, flag bit is invalid, and the instruction to level inter-register FD outputs carries out
Decoding parsing, and according to decoding as a result, at the same time to enhanced register file ERF five read ports initiate read operation so that
Obtain first, second source operand and check code SP1, SP2；First, second source operand copy information SC1, SC2 and target behaviour
Count copy information DC.Decoding module ID inquires about the feedback information (SP1, SP2, SC1, SC2 and DC) of five read ports, copy
Information and other information in control signal are transmitted to level inter-register DE；
Level inter-register DE is under the control of flowing water control module, and after the output of above-mentioned decoding module ID is deposited, output is extremely
Execution module EX；
Execution module EX, as shown in figure 3, including with the enhanced ALU for detecting and comparing ability, it is according to the of input
First, the second source operand and check code SP1, SP2 verify the correctness of source operand；At the same time according to first, second source
Operand carries out arithmetic or logical operation and obtains operation result i.e. target operand, final relatively first, second source operand and
Whether target operand is equal, and when data are equal and storage address is different, then the comparative result of backup is supported in output, otherwise defeated
Go out the comparative result for not supporting backup；Execution module EX is by two comparative result CRA and CRB, mesh of first, second source operand
Mark operand and other undressed inputs are further exported to level inter-register EM；
Execution module EX, as shown in figure 3, including the first source operand correction verification module, the second source operand correction verification module,
ALU, first comparator and the second comparator, first source operand and its check code of the first source operand correction verification module to input
Verified, and check results are connected to first comparator；Second source operand correction verification module operates the second source of input
Number and its check code are verified, and check results are connected to the second comparator；ALU is to the first source operand of input and
Two source operands carry out arithmetic or logical operation, and output target operand is connected between first and second comparator and level and is deposited
Device EM；The input of first and second comparator further includes first and second source operand, and two comparators are according to check results to first and second
The equality of source operand and target operand judges, if check results are abnormal, without comparing, directly passes through CRA
It is abnormal with CRB output verifications, if check results are normal, compare first and second source operand and whether target operand is equal, than
Equally provided compared with result by CRA and CRB；
Level inter-register EM is under the control of flowing water control module, and after the output of above-mentioned execution module EX is deposited, output is extremely
Storage access module MA；
Storage access module MA, further dissection process is not done to input, the main operation for completing to access memory, and to
Level inter-register MW further transmits the output of the module；
Level inter-register MW is defeated after the output of above-mentioned storage access module MA is deposited under the control of flowing water control module
Go out to adaptive write-back modules A WB；
Adaptive write-back modules A WB completes the write operation inside processor, when source operand is incorrect, will instruct at present
PC write-in PC registers, while to copy inquire about control signal, including inquiry flag bit and first, second source operand pair
This address is reasonably set；In the presence of without exception, the write operation of enhanced register file ERF is completed.Fig. 4 is processing
The fault tolerance judgment logical flow chart of device, the flow chart contain adaptive write-back modules A WB according to input information, realize correct
The principle of write operation, it is specific as follows,
Step1：Judge whether the source operand that current processor uses is correct, if mistake, turns to Step2；Otherwise, turn
To Step4；
Step2；Current instruction PC is write into PC registers, and judges whether the source operand of current erroneous backs up number
According to, whether effective judge to inquire about flag bit, if Backup Data, inquiry flag bit is effective, then it is invalid to inquire about mark position, and
Turn to Step3；Otherwise inquiry flag bit is invalid, and the inquiry flag bit put in copy inquiry control signal is effective, and the source that will malfunction
The copy address of operand inquires about control signal by copy and passes to decoding module ID；
Step3：There is the mistake that can not recover in source operand, and processor enters abnormal patterns；
Step4：Effectively no matter at this time, then whether it is invalid to inquire about mark position, and first and second source operand and target are grasped
The comparative result CRA and CRB to count is judged, if CRA or CRB shows that source operand is identical with target operand, is turned to
Step5；Otherwise Step8 is turned to；
Step5：Whether effective detect the copy flag bit of target operand, if invalid, turn to Step6；Otherwise turn to
Step7；
Step6；The address of target operand is written to the corresponding control register file unit of source operand address, will
The address of source operand is written to the corresponding control register copy address field in target operand address, while puts corresponding unit
Copy flag bit is effective, turns to Step9；
Step7：The copy mark position of the corresponding control register file unit in target operand address is invalid, at the same time
The address of target operand is written to the corresponding control register file unit of source operand address, by the address of source operand
The corresponding control register copy address field in target operand address is written to, the copy flag bit of juxtaposition corresponding unit is effective,
Turn to Step9；
Step8：Whether effective detect the copy flag bit of target operand, if invalid, turn to Step9；Otherwise turn to
Step10；
Step9：The check bit of target operand is calculated, and target operand and check bit are write into target operand at the same time
The corresponding data register file unit in address, terminates；
Step10：The copy mark position of the corresponding control register file unit in target operand address is invalid, turn
To Step9.
The present invention by consider the data in different register file cells it is identical when situation, pass through establish dynamic
Safeguard the Backup Data chained list of identical data, take full advantage of the data redundancy inside processor, there is provided one kind more adds
Kind system-level Scheme of Strengthening, improves the controllability and reliability of processor.
Claims (9)
1. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data, it is characterised in that including Pyatyi flowing water
Structure, flowing water control module, check code module, PC registers and enhanced register file REF；
Pyatyi flowing structure includes fetching module I F, decoding module ID, execution module EX, storage access module MA, adaptive returns
Writing module AWB and four groups of level inter-registers；Five modules in Pyatyi flowing structure pass through level inter-register FD, level inter-register
DE, level inter-register EM and level inter-register MW are sequentially connected, and wherein fetching module I F is located at Pyatyi flowing structure first place, adaptive
Write-back modules A WB is answered at end；
The output copy inquiry control signal of adaptive write-back modules A WB is connected to decoding module ID, is used for realization abnormal conditions
The copy inquiry of lower source operand；The output of adaptive write-back modules A WB is connected to the input of PC registers, is used for realization processing
Device abnormal patterns give an order the write operation of PC；The output order PC of PC registers is connected to fetching module I F；PC registers it is defeated
Go out and realize inquiry, reading and use of the processor to redundancy backup data jointly with copy inquiry control signal；
Flowing water control module is connected with the Enable Pin of level inter-register FD, DE, EM and MW, for being enabled according to processor state or
The sampling of prohibitive levels inter-register；
Check code module encodes input data, exports as input data and its school according to error correction and detection coding rule
Test code；The input of check code module comes from adaptive write-back modules A WB, and output is connected to enhanced register file REF
Write port；
Enhanced register file ERF has four to write five readings totally nine ports, and necessary control is read and write in each port comprising realization
Signal processed；All read ports are connected with decoding module ID；
Whether decoding module ID detects its signal inquiry flag bit inputted in copy inquiry control signal first effective；Decode mould
By the feedback information of five read ports, information and other information that copy is inquired about in control signal pass block ID to level inter-register DE
Pass；The feedback information of five read ports includes first, second source operand and check code SP1, SP2, first, second source behaviour
Count copy information
SC1, SC2 and target operand copy information DC；
Level inter-register DE is under the control of flowing water control module, and after the output of above-mentioned decoding module ID is deposited, output extremely performs
Module EX；
Execution module EX includes with detection and compares the enhanced ALU of ability, according to first, second source operand of input and
Check code SP1, SP2 verify the correctness of source operand；Arithmetic is carried out according to first, second source operand at the same time or is patrolled
Volume computing obtains the target operand as operation result, and whether final relatively first, second source operand and target operand
Equal, when data are equal and storage address is different, then the comparative result of backup is supported in output, is otherwise exported and is not supported backup
Comparative result；Execution module EX is by two comparative results CRA and CRB of first, second source operand, target operand and other
Undressed input is further exported to level inter-register EM；
Level inter-register EM is under the control of flowing water control module, and after the output of above-mentioned execution module EX is deposited, output extremely stores
Access modules MA；
Storage access module MA, completes to access the operation of memory, and further transmits the defeated of the module to level inter-register MW
Go out；
Level inter-register MW is under the control of flowing water control module, and after the output of above-mentioned storage access module MA is deposited, output is extremely
Adaptive write-back modules A WB；
Adaptive write-back modules A WB completes the write operation inside processor, when source operand is incorrect, the PC that will instruct at present
PC registers are write, while copy inquiry control signal is configured；In the presence of without exception, enhanced register text is completed
The write operation of part ERF.
2. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 1, it is special
Sign is, the enhanced register file ERF, including data register file and control register file, both store
The number of unit is identical and corresponds, but bit wide is different；The operand of data register file store instruction and its verification
Code, and wherein three ports of enhanced register file ERF are used alone by data register file；Control register text
The link information of part storage Backup Data includes copy address and flag bit, and the operand of copy flag bit instruction current accessed is
It is no that there are Backup Data, storage address of the copy address instruction Backup Data in data register file；Enhanced register text
Remaining six port of part ERF are used alone by control register file.
3. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 2, it is special
Sign is that the operand of data register file store instruction includes calculating the target after the completion of required source operand and calculating
Operand.
4. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 2, it is special
Sign is that wherein three ports of enhanced register file ERF are target operand data write port WD, the first source operand
Data read port RS1 and the second source operand data read port RS2；Remaining six port of enhanced register file ERF are
First source operand control information read port RCS1, the second source operand control information read port RCS2, target operand control
Information read port RCD, target operand control information write port WCD, the first source operand control information write port WCS1 and
Two source operand control information write port WCS2.
5. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 1, it is special
Sign is, the execution module EX, including the first source operand correction verification module, the second source operand correction verification module, ALU,
One comparator and the second comparator, the first source operand correction verification module carry out school to the first source operand and its check code of input
Test, and check results are connected to first comparator；Second source operand correction verification module to the second source operand of input and its
Check code is verified, and check results are connected to the second comparator；ALU grasps the first source operand of input and the second source
Count and carry out arithmetic or logical operation, and output target operand is connected to first and second comparator and level inter-register EM；The
First, the input of two comparators further includes first and second source operand, and two comparators operate first and second source according to check results
The equality of number and target operand judges, directly defeated by CRA and CRB without comparing if check results are abnormal
It is abnormal to go out verification, if check results are normal, compare first and second source operand and whether target operand is equal, comparative result
Equally provided by CRA and CRB.
6. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 1, it is special
Sign is that copy inquiry control signal includes the copy address of inquiry flag bit and first, second source operand；Inquire about flag bit
Promoted backward with assembly line from decoding module ID, until adaptive write-back modules A WB is reset.
7. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 1, it is special
Sign is that four write ports are respectively target operand data write port WD, target operand control information write port WCD,
One source operand control information write port WCS1, wherein the second source operand control information write port WCS2, target operand number
Output driving according to write port WD by check code module, three control information write ports WCD, WCS1 and WCS2 with it is adaptive
The output of write-back modules A WB is answered to be connected；Five read ports are respectively the first source operand data read port RS1, the operation of the second source
Number data read port RS2, the first source operand control information read port RCS1, the second source operand control information read port RCS2
And target operand control information read port RCD.
8. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data according to claim 1, it is special
Sign is, decoding module ID detect its signal inquiry flag bit inputted in copy inquiry control signal it is whether effective when；If look into
Inquiry flag bit is effective, then to inquiring about the unit in control signal in the specified data register file of copy address included in copy
Read operation is carried out, while the input for the decoding module ID that the output with control register file is connected is set to 0；If inquiry
Flag bit is invalid, then the instruction to level inter-register FD outputs is parsed into row decoding, and according to decoding as a result, at the same time to enhanced
Five read ports of register file ERF initiate read operation, so that first, second source operand and check code SP1, SP2 are obtained,
First, second source operand copy information SC1, SC2 and target operand copy information DC.
9. a kind of processor with fault-tolerant architecture based on active link [HTML] Backup Data based on described in claim 6 is fault-tolerant
Method, it is characterised in that the adaptive write-back modules A WB, the judgement of information progress write operation, specific step are inputted according to it
It is rapid as follows：
Step 1：Judge whether the source operand that current processor uses is correct, if mistake, turns to
Step2；Otherwise, Step4 is turned to；
Step2；Current instruction PC is write into PC registers, and judges whether the source operand of current erroneous Backup Data and is sentenced
Whether disconnected inquiry flag bit is effective, if Backup Data, inquiry flag bit is effective, then it is invalid to inquire about mark position, and turns to
Step3；Otherwise data are not backed up, inquiry flag bit is invalid, and the inquiry flag bit put in copy inquiry control signal is effective, and will
The copy address of error source operand inquires about control signal by copy and passes to decoding module ID；
Step3：There is the mistake that can not recover in source operand, and processor enters abnormal patterns；
Step4：To then inquire about that mark position is invalid, comparative result CRA to first and second source operand and target operand and
CRB is judged, if CRA or CRB shows that source operand is identical with target operand, turns to Step5；Otherwise Step8 is turned to；
Step5：Whether effective detect the copy flag bit of target operand, if invalid, turn to
Step6；Otherwise Step7 is turned to；
Step6；The address of target operand is written to the corresponding control register file unit of source operand address, source is grasped
The address counted is written to the corresponding control register copy address field in target operand address, while puts the copy of corresponding unit
Flag bit is effective, turns to Step9；
Step7：The copy mark position of the corresponding control register file unit in target operand address is invalid, while by mesh
The address of mark operand is written to the corresponding control register file unit of source operand address, and the address of source operand is write
To the corresponding control register copy address field in target operand address, the copy flag bit of juxtaposition corresponding unit is effective, turns to
Step9；
Step8：Whether effective detect the copy flag bit of target operand, if invalid, turn to
Step9；Otherwise Step10 is turned to；
Step9：The check bit of target operand is calculated, and target operand and check bit are write into target operand address at the same time
Corresponding data register file unit, terminates；
Step10：The copy mark position of the corresponding control register file unit in target operand address is invalid, turn to
Step9。
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