CN105303999A - Defect detection and correction of pixel circuits for AMOLED displays - Google Patents

Abstract

A method of testing an array-based semiconductor device for defects during fabrication of the semiconductor device detects defects in said entities forming the semiconductor device at an intermediate stage in the fabrication of multiple types of entities forming the semiconductor device; determines whether the detected defects exceed preselected thresholds for the types of entities in which said detects are detected; if the detected defects do not exceed said preselected thresholds, continues the fabrication of the semiconductor device; and if the detected defects exceed said preselected thresholds, identifies the types of defects detected, repairs the identified defects, and continues the fabrication of the semiconductor device. According to the invention, defects and nonuniformity in a manufacturing period can be identified.

Description

Defect Detection and Correction of Pixel Circuits for AMOLED Displays

technical field

The present invention relates generally to active matrix organic light emitting device (AMOLED) displays, and in particular to determining aging conditions requiring compensation of pixels of such displays, and to detection of defects and non-uniformities in such displays system.

Background technique

There is currently a need for techniques for providing accurate measurements of display temporal and spatial information and methods of applying such information to improve display uniformity in AMOLED displays. Baseline measurements that accurately determine pixel characteristics are also required for aging compensation purposes.

Both OLEDs and thin-film transistors (TFTs) used in AMOLED displays exhibit uneven performance on the display panel due to production issues. Such problems can be resolved if defects and non-uniformities can be identified when the panels are being produced (eg, during or immediately after fabrication).

Contents of the invention

According to one embodiment, there is provided a system for detecting defects in an array-based semiconductor device during its manufacture by (a) during the manufacture of the various types of entities forming the semiconductor device an intermediate stage detecting a defect in said entity forming said semiconductor device; (b) determining whether the detected defect exceeds a preselected threshold for the type of said entity from which the defect was detected; (c) if said detected if the defect does not exceed the preselected threshold, continue the manufacture of the semiconductor device; and (d) if the detected defect exceeds the preselected threshold, identify the type of the detected defect and repair Defects are identified and fabrication of the semiconductor device continues.

In one embodiment, the array-based semiconductor device is an active matrix organic light emitting device (AMOLED) display panel, and the various types of bodies include at least driving transistors, OLEDs, and signal lines. The preselected threshold is variable as the number of detected defects increases, and the type of defect is identified by a test tailored to the type of entity in which the defect was detected. Defects may be detected in the entity by measuring the voltage or current in a single pixel and comparing the measured value with a preselected threshold for said voltage or current. The current measured may be the current flowing to the light emitting device of the pixel and the voltage measured may be the voltage at the connection of the pixel circuit to the light emitting device of the pixel. A defect may be detected in said entity by preselecting a reference level of current or voltage based on the lowest level of current or voltage in a normal pixel, and comparing the measured current or voltage with the corresponding preselected said reference level. level for comparison.

The foregoing and additional aspects and embodiments of the invention will become apparent to those skilled in the art from the detailed description of various embodiments and/or aspects with reference to the accompanying drawings (they will be briefly described hereinafter). Obvious.

Description of drawings

The foregoing and other advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description and upon reference to the accompanying drawings.

1 is a block diagram of an AMOLED display with reference pixels for modifying data for parameter compensation control;

FIG. 2A is a block diagram of a driving circuit of a pixel of an AMOLED capable of testing aging parameters;

FIG. 2B is a circuit diagram of a driving circuit of a pixel in AMOLED pixels;

3 is a block diagram of a system for determining one of the baseline aging parameters of a device under test;

4A is a block diagram of the current comparator in FIG. 3 for comparing a reference current level with a device under test for aging compensation;

Figure 4B is a detailed circuit diagram of the current comparator in Figure 4A;

Figure 4C is a detailed block diagram of the device under test in Figure 3 connected to the current comparator in Figure 4A;

5A is a signal timing diagram of signals for the current comparator of FIGS. 3-4 in determining the current output of the device under test;

5B is a signal timing diagram of a signal for correcting a bias current of the current comparator in FIGS. 3 to 4;

6 is a block diagram of a reference current system for compensating aging of the AMOLED display in FIG. 1;

7 is a block diagram of a system for adjusting multiple brightness files used by a display under different circumstances;

8 is a block diagram of a video frame for calibration of pixels in a display; and

Figure 9 shows the use of a small current applied to the reference pixel for more accurate aging compensation.

10 is a schematic diagram of a display having a pixel matrix including rows of reference pixels.

11 is a timing diagram of aging compensation by applying a reset cycle prior to programming, during which the pixel is programmed with a reset value.

12A is a circuit diagram of a pixel circuit with IR drop compensation.

12B is a timing diagram of normal operation of the pixel circuit of FIG. 12A.

12C is a timing diagram for direct TFT readout of the pixel circuit of FIG. 12A.

12D is a timing diagram for direct OLED readout of the pixel circuit of FIG. 12A.

13A is a circuit diagram of a pixel circuit with charge base compensation.

13B is a timing diagram of normal operation of the pixel circuit of FIG. 13A.

13C is a timing diagram for direct TFT readout of the pixel circuit of FIG. 13A.

13D is a timing diagram for direct OLED readout of the pixel circuit of FIG. 13A.

13E is a timing diagram for indirect OLED readout of the pixel circuit of FIG. 13A.

14 is a circuit diagram of a bias pixel circuit.

FIG. 15A is a circuit diagram of a pixel circuit having signal lines connected to the OLED and the pixel circuit.

15B is a circuit diagram of a pixel circuit having patterned ITO electrodes as signal lines.

Fig. 16 is a schematic diagram of a pad arrangement for probing of a panel.

FIG. 17 is a circuit diagram of a pixel circuit used for backplane testing.

FIG. 18 is a circuit diagram of a pixel circuit for full display testing.

Figure 19 is a schematic perspective view of a display panel adapted to receive a probecard.

FIG. 20 is a schematic front view of the display panel shown in FIG. 1 , showing locations of probe pads for receiving probe cards.

Figure 21 shows a pair of probe pads connected to a multiplexer for providing probe signals to the probe pads.

FIG. 22 is a schematic circuit diagram of one of the probe pads shown in FIG. 3 connected to receive display signals.

23 is a schematic diagram of an inspection system for performing measurements of an AMOLED panel and various corrective actions that may be used to repair defects identified through analysis of the measurements.

FIG. 24 is a schematic circuit diagram of a pixel circuit with signal WR.

Fig. 25 is a circuit diagram of a pair of pixel circuits suitable for detection.

While the invention is capable of various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. The present invention can cover all modifications, equivalents and substitutions within the spirit and scope of the present invention as defined by the appended claims of the present invention.

detailed description

FIG. 1 is an electronic display system 100 having an active matrix region or pixel array 102 in which an array of active pixels 104a-d are arranged in a row and column configuration. For ease of illustration, only two rows and two columns are shown. The outside of the active matrix region (pixel array 102 ) is a peripheral region 106 in which peripheral circuits for driving and controlling the region of the pixel array 102 are arranged. Peripheral circuitry includes a gate or address driver circuit 108 , a source or data driver circuit 110 , a controller 112 , and an optional supply voltage (eg, Vdd) driver 114 . The controller 112 controls the gate driver 108 , the source driver 110 and the supply voltage driver 114 . Under the control of controller 12 , gate driver 108 operates address or select lines SEL[i] and SEL[i+1], etc., for each row of pixels 104 in pixel array 102 . In the pixel sharing configuration described below, the gate or address drive circuit 108 can also optionally operate on the global select lines GSEL[j] and /GSEL[j], and the global select lines GSEL[j] and /GSEL[j] Multiple rows of pixels 104a-d in pixel array 102 operate, such as every two rows of pixels 104a-d. The voltage data lines carry voltage programming information to each pixel 104 indicative of the brightness of each light emitting device in the pixel 104 . A storage element, such as a capacitor, in each pixel 104 stores voltage programming information until a light emission or drive cycle turns on the light emitting device. An optional supply voltage driver 114 under the control of controller 112 controls a supply voltage (EL_Vdd) line for each row of pixels 104 a - d in pixel array 102 .

Display system 100 may also include a current source circuit that provides a fixed current on the current bias line. In some configurations, a reference current can be provided to the current source circuit. In this configuration, the current source controller controls the timing of application of the bias current on the current bias line. In a configuration in which the reference current is not supplied to the current source circuit, the current source address driver controls the application timing of the bias current on the current bias line.

As is well known, each pixel 104a-d in the display system 100 needs to be programmed with information indicative of the brightness of the light emitting device in the pixel 104a-d. A frame defines a period of time that includes a programming cycle or phase in which each pixel in display system 100 is programmed with a programming voltage indicative of brightness and a drive or light emitting cycle or phase. Each light emitting device in each pixel is turned on during the driving period to emit light at a brightness corresponding to the programming voltage stored in the storage element. Thus, a frame is one static image among many still images that make up the complete moving image displayed on display system 100 . There are at least two schemes for programming and driving pixels: row-by-row or frame-by-frame. In row-by-row programming, a row of pixels is programmed and then driven, and then the next row of pixels is programmed and driven. In frame-by-frame programming, all rows of pixels in the display system 100 are programmed first, and then all frames are driven row by row. Either scheme can use a short vertical blanking time at the beginning or end of each frame during which the pixels are neither programmed nor driven.

On the same physical substrate on which the pixel array 102 is arranged, components located outside the pixel array 102 may be arranged in a peripheral region 106 around the pixel array 102 . These components include gate driver 108 , source driver 110 and optional supply voltage controller 114 . Alternatively, some components in the peripheral area may be arranged on the same substrate as the pixel array 102, while other components are arranged on a different substrate, or all components in the peripheral area may be arranged on the same substrate as the pixel array 102. substrates on different substrates. The gate driver 108 , the source driver 110 , and the power supply voltage controller 114 together constitute a display driving circuit. The display drive circuitry in some configurations may include gate drivers 108 and source drivers 110 , but not supply voltage controllers 114 .

The display system 100 also includes a current supply and readout circuit 120 for reading output data from data output lines VD[k] and VD[k+1], etc., for each column of pixels 104a and 104c in the pixel array 102 . At the edge of pixel array 102, a set of column reference pixels 130 are mounted at the end of each column, such as the columns of pixels 104a and 104c. Column reference pixels 130 may also receive input signals from controller 112 and output data signals to current supply and readout circuitry 120 . Column reference pixel 130 includes a drive transistor and an OLED, but is not part of pixel array 102 that displays an image. As will be explained below, column reference pixels 130 are not driven during most programming cycles because they are not part of pixel array 102 displaying an image and are therefore not affected by the duration of the programming voltage compared to pixels 104a and 104c. Aging due to application. Although only one column reference pixel 130 is shown in FIG. 1, it should be understood that there may be any number of column reference pixels, although in this example two to five such reference pixels may be used per column of pixels. Each row of pixels in array 102 also includes a row reference pixel 132 located at the end of each row of pixels 104a-d, such as pixels 104a and 104b. Row reference pixels 132 include drive transistors and OLEDs, but are not part of pixel array 102 that displays an image. As will be explained, row reference pixels 132 have the function of providing a benchmark check of the pixel's luminance curve, which is determined at the time of production.

FIG. 2A shows a block diagram of a driving circuit 200 for the pixel 104 of FIG. 1 . The driving circuit 200 includes a driving device 202 , an organic light emitting device ("OLED") 204 , a memory element 206 and a switching device 208 . The voltage source 212 is connected to the driving device 202 . The select line 214 is connected to the switching device to activate the driver circuit 200 . The data line 216 enables the programming voltage to be applied to the driving device 202 . Monitor line 218 enables the output of OLED 204 and/or driver 202 to be monitored. Alternatively, monitor line 218 and data line 216 may be combined into one line (ie, Data/Mon) so that both programming and monitoring functions are performed on one line.

FIG. 2B shows an example of a circuit implementing the driving circuit 200 in FIG. 2A. As shown in FIG. 2B , the driving device 202 is a driving transistor, which in this example is a thin film transistor made of amorphous silicon. In this example, storage element 206 is a capacitor. The switching device 208 includes a selection transistor 226 and a monitoring transistor 230 for switching different signals to the driver circuit 200 . Select line 214 is connected to select transistor 226 and monitor transistor 230 . During the read time, select line 214 is pulled high. A programming voltage may be applied via programming voltage input line 216 . The monitor voltage can be read from monitor line 218 connected to monitor transistor 230 . Signals may be sent to select lines 214 in parallel with the pixel programming cycle. As will be explained below, the driving circuit 200 may be tested periodically by applying a reference voltage to the gate of the driving transistor.

There are several techniques for extracting electrical characteristic data from a device under test (DUT), such as display system 100 . The device under test (DUT) can be any material (or device) including, but not limited to, light emitting diodes (LEDs) or OLEDs. Such testing can effectively determine the aging (and/or uniformity) of OLEDs in a panel comprised of an array of pixels, such as array 102 in FIG. 1 . In memory in controller 112 in FIG. 1, this extracted data may be stored in a lookup table as raw or processed data. The look-up table can be used to compensate for any shifts in the electrical parameters of the backplane or OLED (eg shifts in threshold voltage or shifts in OLED operating voltage). Although the OLED display in FIG. 1 is used in these examples, the techniques described herein may be applied to any display technology including, but not limited to, OLEDs, liquid crystal displays (LCDs), light emitting diode displays, or plasma displays, among others. In the case of OLEDs, the measured electrical information can provide an indication of any aging that may have occurred.

Current can be applied to the device under test and the output voltage can be measured. In this example, voltage is measured using an analog-to-digital converter (ADC). An aged device such as an OLED needs a higher programming voltage than a new OLED to have the same output. This method gives a direct measurement of this voltage change of the device under test. The direction of current flow can be in any direction, but for illustration purposes the current is typically fed into a device under test (DUT).

FIG. 3 is a block diagram of a comparison system 300 that may be used to determine a baseline value for a device under test 302 to determine the effects of aging on the device under test 302 . The comparison system uses two reference currents to determine the baseline current output of the device under test 302 . Device under test 302 may be a drive transistor such as drive transistor 202 in FIG. 2B or an OLED such as OLED 204 in FIG. 2B . Of course, other types of display devices can also be tested using the system shown in FIG. 3 . The device under test 302 has a programming voltage input 304 held at a constant level to output a current. The current comparator 306 has a first reference current input 308 and a second reference current input 310 . The reference current input 308 is connected to a first reference current source 312 via a switch 314 . A second current input 310 of the comparator 306 is connected to a second reference current source 316 via a switch 318 . The output 320 of the device under test 302 is also connected to the second current input 310 . Current comparator 306 includes a comparison output 322 .

By keeping the voltage at input 304 constant, the output current of device under test 302 is also constant. This current depends on the characteristics of the device under test 302 . A constant current is established for a first reference current from a first reference current source 312 and applied to a first input 308 of a current comparator 306 via a switch 314 . The second reference current is adjusted to different levels, where each level is connected to the second input 310 of the comparator 306 via a switch 318 . The second reference current is mixed with the output current of the device under test 302 . Since the first reference current level and the second reference current level are known, the difference between the two reference current levels at the output 322 of the current comparator 306 is the current level of the device under test 302 . The resulting output current is stored for the device under test 302 and compared to a current periodically measured based on the same programmed voltage level during the lifetime operation of the device under test 302 to determine the effects of aging.

For each device in the display, the determined device current obtained can be stored in a look-up table. As the device under test 302 ages, the current will change from the desired level and thus the programming voltage may be changed to compensate for the effect of aging based on the baseline current determined through the calibration process in FIG. 3 .

FIG. 4A is a block diagram of a current comparator circuit 400 that may be used to compare a reference current to, for example, the current of the device under test 302 in FIG. 3 . The current comparator circuit 400 has a control node 402 that allows various current inputs such as two reference currents and currents of a device under test such as the pixel driving circuit 200 in FIG. 1 . The current is a positive current when the current of the driving transistor 202 is compared or a negative current when the current of the OLED 204 is compared. The current comparator circuit 400 also includes an operational transimpedance amplifier circuit 404 , a preamplifier 406 , and a voltage comparator circuit 408 that generates a voltage output 410 . The combined current is input to the operational transimpedance amplifier circuit 404 and converted into a voltage. This voltage is input to the preamplifier and a voltage comparator circuit 408 determines whether the current difference is positive or negative and outputs either the current difference or a zero value.

4B is a circuit diagram of components of an example of the current comparator circuit 400 in FIG. 4A that may be used to compare currents as described in the process in FIG. 3 for a device under test, such as device 302 . The operational transimpedance amplifier circuit 404 includes an operational amplifier 412 , a first voltage input 414 (CMP_VB), a second voltage input 416 (CMP_VB), a current input 418 and a bias current source 420 . The operational transimpedance amplifier circuit 404 also includes two calibration switches 424 and 426 . As will be explained below, in this example, various currents such as the current of the device under test 302 shown in FIG. 3 , a variable first reference current, and a fixed second reference current are connected to the current input 418 . Of course, the fixed second reference current can be set to zero if desired.

The first reference current input is connected to the negative input of operational amplifier 412 . Thus, the negative input of the operational amplifier 412 is connected to the output current of the device under test 302 in FIG. 3 and one or two reference currents. The positive input of the operational amplifier 412 is connected to the first voltage input 414 . The output of operational amplifier 412 is connected to the gate of transistor 432 . Resistor 434 is connected between the negative input of operational amplifier 412 and the source of transistor 432 . A resistor 436 is connected between the source of transistor 432 and the second voltage input 416 .

The drain of transistor 432 is directly connected to the drain of transistor 446 and to the gate of transistor 446 via calibration switch 426 . The sampling capacitor 444 is connected between the gate of the transistor 446 and the power supply voltage line 411 through the switch 424 . The source of transistor 446 is also connected to supply voltage line 411 . The drain and gate of transistor 446 are connected to the gate terminals of transistors 440 and 442, respectively. The sources of transistors 440 and 442 are connected together and to bias current source 438 . The drains of transistors 440 and 442 are connected to transistors 448 and 450, respectively, which are connected to supply voltage line 411 in a diode-connected configuration. As shown in FIG. 4B , transistors 440 , 442 , 448 , and 450 and bias current source 438 are components of preamplifier 406 .

The drain of transistor 442 and the drain of transistor 440 are respectively connected to the gate of transistor 452 and the gate of transistor 454 . The drains of transistors 452 and 454 are connected to transistors 456 and 458 . The drain of transistor 456 and the drain of transistor 458 are connected to the source of transistor 460 and the source of transistor 462 , respectively. The drain and gate terminals of transistors 460 and 462 are connected to the drain and gate terminals of transistors 464 and 466 , respectively. The source terminals of transistors 464 and 466 are connected to supply voltage line 411 . The source and drain of transistor 464 are connected to the source and drain of transistor 468 , and the source and drain of transistor 466 are connected to the source and drain of transistor 470 . The gates of transistors 456 and 458 are connected to enable input 472 . An enable input 472 is also connected to the gates of dual transistors 468 and 470 .

Buffer circuit 474 is connected to the drain of transistor 462 and the gate of transistor 460 . The output voltage 410 is connected to a buffer circuit 476 connected to the drain of transistor 460 and the gate of transistor 462 . Buffer circuit 474 is used to balance buffer circuit 476 . Transistors 452 , 454 , 456 , 458 , 460 , 462 , 464 , 466 , 468 , and 470 and buffer circuits 474 and 476 constitute voltage comparator circuit 408 .

The current comparator system 400 may be based on any integrated circuit technology including but not limited to CMOS semiconductor fabrication. In this example, the components of the current comparator system 400 are CMOS devices. For a given reference current level from the first current input 418 (I _ref ), the values of the input voltages of the input voltages 414 and 416 are determined. In this example, input voltages 414 and 416 are at the same voltage level. The voltage inputs 414 and 416 to the operational amplifier 412 may be controlled by using a digital-to-analog converter (DAC) arrangement not shown in FIG. 4 . If the voltage range of the DAC is insufficient, a level shifter can also be added. The bias current can be generated by a voltage controlled current source such as a transimpedance amplifier circuit or a transistor such as a thin film transistor.

FIG. 4C shows a detailed block diagram of one example of a testing system, such as system 300 shown in FIG. 3 . The test system in FIG. 4C is connected to a device under test 302 , where the device under test 302 may be a pixel driving circuit such as the pixel driving circuit 200 shown in FIG. 2 . In this example, all drive circuits for a flat panel display are tested. The gate driver circuit 480 is connected to the select lines of all drive circuits. Gate driver circuit 480 includes an enable input, which in this example enables device under test 302 when the input signal is low.

The device under test 302 receives data signals from the source driver circuit 484 . Source driver circuit 484 may be a source driver such as source driver 120 in FIG. 1 . The data signal is a programming voltage of a predetermined value. When the gate driver circuit 480 activates the device, the device under test 302 outputs current on the monitor line. The output from the monitor line of the device under test 302 is connected to an analog multiplexing circuit 482 which enables multiple devices to be tested. In this example, the analog multiplexing circuit 482 allows the multiplexing of 210 inputs, but of course any number of inputs can be multiplexed.

The signal output of the device under test 302 is connected to the reference current input 418 of the operational transimpedance amplifier circuit 404 . In this example, a variable reference current source is connected to the current input 418 as described in FIG. 3 . In this example, there is no fixed current such as the first reference current in FIG. 3 . Therefore, the value of the first reference current source in FIG. 3 is considered to be zero in this example.

5A is a timing diagram of the signals of the current comparator shown in FIGS. 4A-4C. The timing diagram in FIG. 5A shows the gate enable signal 502 of the gate driver 480 in FIG. Each repetition of the test process is set to a predetermined level and connected to the current input terminal 418), the current reference signal 506 generated, the calibration signal 508 controlling the calibration switch 426, the calibration signal 510 controlling the calibration switch 424, connected to the Comparator enable signal 512 on input 472 and output voltage 514 on output 410 . The CSE enable signal 504 is held high to ensure that any leakage on the monitor line of the device under test 302 is eliminated in the final current comparison.

In the first phase 520, the gate enable signal 502 is pulled high and therefore, the output of the device under test 302 in FIG. 4C is zero. Therefore, the current input to the current comparator 400 is only the leakage current from the monitor line of the device under test 302 . The output of reference current 506 is also set to zero so that the optimal quiescent state of transistors 432 and 436 in FIGS. 4B and 4C is only minimally affected by line leakage or offsets of the readout circuitry. Calibration signal 508 is set high, which causes calibration switch 426 to close. Calibration signal 510 is set high, which causes calibration switch 424 to close. The comparator enable signal 512 is set low and thus the output of the voltage comparator circuit 408 is reset to a logic one. Accordingly, the leakage current is input to current input 418 and a voltage representing the leakage current of the monitor line on the panel is stored on capacitor 444 .

In the second phase 522 , the gate enable signal 502 is pulled low and thus the output of the device under test 302 produces an unknown current at the set programming voltage input from the source driver circuit 484 . The current from the device under test 302 is input through the current input 418 together with a reference current 506 set to a first predetermined value and opposite to the current direction of the device under test. Thus, the current input 418 is the difference between the reference current 506 and the current from the device under test 302 . Calibration signal 510 is briefly set low to open switch 424 . Then, the calibration signal 508 is set low and thus the switch 426 is opened. Calibration signal 510 controlling switch 424 is then set high to close switch 424 , thereby stabilizing the voltage on the gate terminal of transistor 446 . The comparator enable signal 512 remains low and therefore there is no output from the voltage comparator circuit 408 .

In the third phase 524 , the comparator enable signal 512 is pulled high and the voltage comparator 408 produces an output on the voltage output 410 . In this example, a positive voltage output logic 1 of the output voltage signal 514 indicates a positive current, thus indicating that the current of the device under test 302 is greater than the predetermined reference current. A zero voltage on the voltage output 410 indicates a negative current, which indicates that the current of the device under test 302 is less than the reference current of a predetermined level. In this way, any difference between the current of the device under test and the reference current is amplified and detected by the current comparator circuit 400 . Then, based on the detected structure, the value of the reference current is shifted to a second predetermined level and stages 520, 522 and 524 are repeated. Adjusting the reference current enables the comparison circuit 400 to be used by a test system to determine the current output of the device under test 302 .

FIG. 5B is a timing diagram of signals applied to the test system shown in FIG. 4C in order to determine an optimal bias current value for the bias current source 420 in FIG. 4B of the operational transimpedance amplifier circuit 404 . In order to obtain the maximum signal-to-noise ratio (SNR) of the current comparator circuit 400, the current comparator must be calibrated. The calibration is achieved by finetuning of the bias current source 420 . The optimum bias current level for bias current source 420 minimizes noise power (which is also a function of line leakage) during measurement of the pixel. Therefore, there is a need to capture line leakage during calibration of the current comparator.

The timing diagram in FIG. 5B shows the gate enable signal 552 of the gate driver 480 in FIG. A comparator enable signal 558 connected to enable input 472, a current reference signal generated by a variable reference current source (which is set to a predetermined level during each repetition of the test process and connected to current input 418) 560 and an output voltage 562 on output 410 .

The CSE enable signal 554 is held high to ensure that any leakage on the line is included in the calibration process. To prevent the device under test 302 from outputting current from any data input, the gate enable signal 552 is also held high. In a first phase 570 , the calibration signal 556 is pulled high, thereby closing the calibration switch 426 . Another calibration signal is pulled high to close the calibration switch 424 . To reset the voltage output from the voltage comparator circuit 408, the comparator enable signal 558 is pulled low. Any leakage current from the monitor line of device under test 302 is converted to a voltage stored in capacitor 444 .

The second stage 572 is entered when the calibration signal input to switch 424 is pulled low and then calibration signal 556 is pulled low, opening switch 426 . Then, the signal input to the switch 424 is pulled high to close the switch 424 . A small current is output to current input 418 from the reference current source. The small current value is the minimum value corresponding to the minimum detectable signal (MDS) range of the current comparator 400 .

The third stage 574 is entered when the comparator enable signal 558 is pulled high, enabling the voltage comparator circuit 408 to read the input. The output of voltage comparator circuit 408 on output 410 should be positive, which indicates a positive current compared to the leakage current.

The fourth stage 576 is entered when the calibration signal 556 is pulled high again, thereby closing the calibration switch 426 . To reset the voltage output from the voltage comparator circuit 408, the comparator enable signal 558 is pulled low. Any leakage current from the monitor line of device under test 302 is converted to a voltage stored in capacitor 444 .

Fifth stage 578 is entered when the calibration signal input to switch 424 is pulled low and then calibration signal 556 is pulled low, opening switch 426 . Then, the signal input to the switch 424 is pulled high, thereby closing the switch 424 . A small current is output to current input 418 from the reference current source. This small current is the minimum value corresponding to the minimum detectable signal (MDS) range of the current comparator 400 , but is a negative current as opposed to the positive current in the second phase 572 .

The sixth stage 580 is entered when the comparator enable signal 558 is pulled high, enabling the voltage comparator circuit 408 to read the input. The output of voltage comparator circuit 408 on output 410 should be zero, which represents a negative current compared to the leakage current.

Stages 570, 572, 574, 576, 578 and 580 are repeated. By adjusting the value of the bias current, eventually, the ratio of effective output voltage triggers between 1 and 0 reaches a maximum value representing the optimum bias current value.

FIG. 6 is a block diagram of compensation components of the controller 112 of the display system 100 in FIG. 1 . The compensation component includes an aging extraction part 600 , a backplane aging/matching module 602 , a color sharing/gamma correction module 604 , an OLED aging memory 606 and a compensation module 608 . The backplane with electronic components used to drive the display system 100 may be of any technology including, but not limited to, amorphous silicon, polycrystalline silicon, single crystal silicon, organic semiconductors, and oxide semiconductors. Furthermore, display system 100 may be any display material (or device) including, but not limited to, LEDs or OLEDs.

The aging extraction section 600 is connected to receive output data from the array 102 based on the input of the pixels of the array and corresponding to the output for testing the effects of aging on the array 102 . The aging extraction section 600 uses the output of the column reference pixels 130 as a baseline for comparison with the outputs of the valid pixels 104a-d to determine each of the pixels 104a-d on each column including the respective column reference pixels 130 affected by aging. Alternatively, the average value of the pixels in a column can be calculated and compared to the value of a reference pixel. The color sharing/gamma correction module 604 also obtains data from the column reference pixels 130 to determine appropriate color corrections to compensate for the aging effects of the pixels. Baselines for comparing contrast measurements may be stored in a look-up table in memory 606 . The backplane aging/matching module 602 calculates adjustments for the backplane of the display and components of the electronics. Compensation module 608 is provided with inputs from aging extraction section 600, backplane aging/matching module 602, and color sharing/gamma correction module 604 to modify the programming voltage input to pixels 104a-d in FIG. Make compensation. The compensation module 608 accesses the look-up table to obtain base data for each of the pixels 104a-d on the array 102 that will be used in conjunction with the calibration data. The compensation module 608 modifies the programming voltages of the pixels 104 a - d accordingly based on the values in the lookup table and the data obtained from the pixels in the display array 102 .

Controller 112 in FIG. 2 measures data from pixels 104a-d in display array 102 in FIG. 1 to properly normalize the data collected during the measurement. For pixels on each column, column reference pixels 130 assist in these functions. Column reference pixels 130 may be located outside the active viewing area represented by pixels 104a-d in FIG. 1, but such reference pixels may also be embedded within the active viewing area. Column reference pixels 130 hold controlled conditions, such as not aged or aged in a predetermined manner, to provide offset and cancellation information for measured data of pixels 104 a - d in display array 102 . This information helps the controller 112 cancel common mode noise from external sources such as room temperature or internal to the system itself such as leakage currents from other pixels 104a-d. Using a weighted average of several pixels on the array 102 can also provide information on overall panel characteristics to account for issues such as voltage drops due to resistance across the panel, ie current/resistance (IR) drops. Information applied from known and controlled sources for the column reference pixels 130 may be used in the compensation algorithm performed by the compensation module 608 to reduce any divergence-generated compensation errors. A selection of column reference pixels 130 may be made using data collected from an initial baseline measurement of the panel. Bad reference pixels are identified and alternative reference pixels 130 can be selected to ensure further reliability. Of course, it should be understood that for calibration and measurement purposes, row reference pixels 132 may be used instead of column reference pixels 130 and rows may be used instead of columns.

In a display that uses external readout circuitry to compensate for drift in pixel characteristics, the readout circuitry reads at least one of current, voltage, and charge from a pixel when the pixel is provided with a known input signal over time . The readout signal is translated into a drift in pixel parameters and used to compensate for pixel characteristic variations. These systems are primarily susceptible to offsets from variations in the readout circuitry due to various phenomena such as temperature variations, aging, and leakage. As described in Figure 10, reference pixel rows (hatched pixels in Figure 10) can be used to remove these effects from the readout circuitry, and these reference rows can be used in the display array. These reference pixel rows are biased in a manner that is substantially immune to aging. The readout circuit reads out these reference pixel rows, and also reads out the normal display rows. Afterwards, the readout value of the normal row is corrected by the reference value, so as to eliminate the undesired influence. Since each column is connected to a readout circuit, it is practical to use the reference pixel in the column to adjust the normal pixels for that column.

The main changes will be global influences on the panel such as temperature etc. that affect both the reference pixel and the pixel circuitry. In this case, this effect will be removed by the compensation value, so there will be a separate compensation for such phenomena.

In order to provide compensation for global phenomena without additional compensation factors or sensors, the influence of global phenomena is subtracted from the reference pixel. There are different ways to calculate the impact of global phenomena. However, the immediate impact is:

Average reference value: Here, the average value of the reference pixel values is used as the influence of the global phenomenon. This value can then be subtracted from all reference pixels. Therefore, if the reference values are modified using global phenomena, then it will be subtracted from these reference values. Therefore, when the pixel measurements are corrected by the reference value, the global influence in the pixel values remains unchanged. Therefore, this will be able to compensate for such effects.

Master reference pixels: Another approach is to use master reference pixels (master reference pixels can be a subset of reference pixels or completely different reference pixels). Similar to the previous method, the mean value of the main reference pixel is subtracted from the reference pixel circuit, which results in the effects of global phenomena remaining in the pixel measurements.

There are a variety of compensation methods that can utilize column reference pixels 130 in FIG. 1 . For example, in a thin film transistor measurement, the data value required for the output current of the column reference pixel 130 is subtracted from the data value of the pixels 104a-d of the same column in the active area (pixel array 102) to output same current. Measurements of column reference pixel 130 and pixels 104a-d may occur very close in time, eg, within the same video frame period. Any difference in current indicates the effects of aging on the pixels 104a-d. The obtained values can be used by the controller 112 to calculate appropriate adjustments to the programming voltages of the pixels 104a-d to maintain the same brightness over the lifetime of the display. Another role of the column reference pixel 130 is to provide a reference current for the other pixels 104 to use as a baseline and to determine the effect of aging on the current output of those pixels. Because reference pixels 130 and active pixels 104 have common data and supply lines, some common mode noise cancellation is inherent in the measurement, and thus reference pixels 130 may simplify data manipulation. In order to verify that the luminance curves of the pixels stored to compensate for the use of the controller during the production of the display are correct, the row reference pixels 132 may be periodically measured.

For a 1080p display, the measurement of the drive transistors and OLEDs of all drive circuits on the display, such as the drive circuit 200 in FIG. This results in malfunctioning or non-luminous pixels). It will also detect non-uniformities in the performance of drive transistors or OLEDs (which cause uneven brightness). This technology can replace optical inspection with a digital camera, making this expensive component unnecessary in production equipment. Since the color filter is a purely optical element, it is not possible to fully detect the AMOLED using the color filter in an electrical manner. In this case, aging-compensating techniques such as Ignis' MAXLIFE ^(TM) may be useful in combination with an optical detection step by providing additional diagnostic information and potentially reducing the complexity of optical detection.

These measurements provide more data than optical inspection can provide. Knowing whether point defects are due to shorted or open drive transistors or shorted or open OLEDs can help identify root causes or defects in the production process. For example, the most common cause of shorted OLEDs is particulate contamination that falls on the glass during handling and shorts the anode and cathode of the OLED. An increase in OLED shorts can indicate that the line should be shut down for chamber cleaning, or a search for a new source of particles (change in process, or equipment, or personnel, or material) can be initiated.

A relaxation system for compensating for aging effects, such as the MAXLIFE ^™ system, can correct for process non-uniformities, which improves display yield. However, measuring current and voltage relationships or characteristics in TFTs or OLEDs is also helpful for diagnosis. For example, the shape of an OLED current-voltage characteristic can reveal increased resistance. A possible reason could be a change in contact resistance between transistor source/drain metal and ITO (in bottom emitting AMOLED). If the OLEDs in the corners of the display show different current-voltage characteristics, then a possible cause could be mask misalignment during fabrication.

Streaks or circular areas on the display with different OLED current voltage characteristics may be caused by defects in the manifold used to disperse the organic vapors during the manufacturing process. In one possible scenario, small particles of OLED material may flake off from the upper shroud and fall onto the manifold, partially blocking the orifice. The measured data will show different OLED current-voltage characteristics in specific patterns, which will help to quickly diagnose problems. Due to the precision of the measurements (for example, a 4.8-inch display measures current with a resolution of 100 nA) and the measurement of the OLED current-voltage characteristics itself (instead of brightness), it is possible to detect changes that would not be detectable using optical detection.

This high precision data can be used in statistical process control to identify when a process begins to drift outside the control limits of the control. This enables early corrective action (during OLED or drive transistor (TFT) manufacturing) before defects are detected in the finished product. Since each TFT and OLED on each display is sampled, the measurement sample is maximized.

If both the drive transistor and the OLED are functioning properly, then readings within the expected range will be returned to the components. The pixel drive circuit requires that the OLED be off when the drive transistor is being measured (and vice versa), so if either the drive transistor or the OLED is in a short, then the other measurements will be inaccurate. If the OLED is shorted (so the current reading is MAX), then the data will show the drive transistor as open (current read MIN), but in reality, the drive transistor may be operational or open. If additional data on the drive transistor is needed, momentarily disconnect the supply voltage (EL_VSS) and let it float, this will get the correct drive transistor measurement indicating whether the TFT is actually operational or open circuit.

In the same way, if the drive transistor is shorted, the data will show the OLED as open (but the OLED may be operational or open). If additional data on the OLED is needed, disconnect the supply voltage (EL_VDD) and float it, this will get the correct OLED measurement indicating whether the OLED is actually operational or open circuit.

If both the OLED and the TFT in the pixel exhibit a short circuit, one element in the pixel will burn out rapidly during the measurement, which results in an open circuit and goes into a different state. These results are summarized in Table 1 below.

Table 1

7 shows a system diagram of a control system 700 for controlling the brightness of a display 702 over time based on different aspects. Display 702 may include an OLED array or other pixel-based display device. System 700 includes profile generator 704 and decider 706 . File generator 704 receives characteristic data from OLED characteristic table 710 , backplane characteristic table 712 and display specification file 714 . For different conditions, the file generator 704 generates different brightness files 720a, 720b...720n. Here, in order to improve power consumption, display lifetime and image quality, different brightness files 720a, 720b...720n may be defined based on OLED and backplane information. Moreover, based on different applications, one can select different files from the brightness files 720a, 720b...720n. For example, a time-dependent flat panel brightness profile can be used to display video output such as a movie, while for brighter applications the brightness can be reduced at a defined rate. Decider 706 may be software or hardware based and includes application input 730, environmental parameter input 732, backplane aging data input 734, and OLED aging data input 736 as factors for adjusting programmed voltages to ensure proper brightness of display 702.

In order to perfectly compensate for display aging, short-term and long-term changes in display characteristics are separated. One approach is to measure multiple points on the display with less time between measurements. Thus, a quick scan reveals short-term effects, while a normal aging extraction reveals long-term effects.

The previous implementation example of the compensation system used a conventional drive scheme where there was always a video frame displayed on the panel and the OLED and TFT circuits were constantly under electrical stress. The calibration of each pixel occurs by doing the calibration of each pixel during a video frame by changing the gray value of the active pixel to a desired value that causes a visual artifact of the measured sub-pixel to be seen during calibration ( visual artifact). If the frame rate of the video is X, then in a conventional video drive, each video frame is displayed on the pixel array 102 in FIG. 1 for 1/X second and the panel is always running the video frame. In contrast, the relaxed video drive in this example divides the frame time into four sub-frames as shown in FIG. 8 . FIG. 8 is a timing diagram of a frame 800 including a video subframe 802 , a dummy subframe 804 , a relaxed subframe 806 , and a replacement subframe 808 .

Video subframe 802 is the first subframe that is the actual video frame. This video frame is generated in the same manner as a conventional video driver, thereby programming the entire pixel array 102 in FIG. 1 with the video data received from the programming input. Dummy subframe 804 is an empty subframe sent to pixel array 102 without any actual data. The dummy subframe 804 is used to hold the same video frame displayed on the panel 102 for a period of time before the relaxation subframe 806 is applied. This increases the brightness of the panel.

The relaxation subframe 806 is the third subframe that is a black frame in which all the red, yellow, blue and white (RGBW) subpixels in the pixel array 102 have a grayscale value of zero. This darkens the panel and sets all pixels 104 to a predefined state ready for calibration and insertion of the next video subframe. The replacement subframe 808 is a short subframe that is generated separately for calibration. When the relaxation subframe 806 is complete and the panel goes black, the data replacement phase begins on the next video frame. Except for rows with replacement data, no video or blank data is sent to pixel array 102 during this phase. For rows that are not being replaced, only the gate driver's timer is triggered to shift the entire gate driver's token. This is done to speed up the scanning of the entire panel and also enable more measurements per frame.

Another method is used to further mitigate the measured sub-pixel visual artifacts within the replacement sub-frame 808 . The method is done by reprogramming the measured rows by using black once the calibration is done. This returns the subpixel to its previous state within the relaxed subframe 806 . However, there is still a small current passing through the OLED in the pixel, which causes the pixel to light up and draw attention to the outside world. Therefore, to redirect the current through the OLED, the controller 112 is programmed with a non-zero value to reduce the current from the pixel's drive transistor and keep the OLED off.

A disadvantage of having alternate subframes 808 is that the time of measurement is limited to a small fraction of the entire frame. This limits the number of subpixel measurements per frame. This limitation is acceptable during the operating hours of the pixel array 102 . However, for a quick baseline measurement of a panel, measuring the entire display would be a time-consuming task since each pixel must be measured. To overcome this problem, a baseline mode is added to the relaxation drive scheme. FIG. 8 also shows a baseline frame 820 for the drive scheme during the baseline measurement mode of the display. Baseline measurement frame 820 includes video subframe 822 and replacement subframe 824 . If the system is switched to baseline mode, the drive scheme is changed so that there are only two subframes in a baseline frame such as frame 820 . Video subframe 822 includes normal programming data for the image. In this example, as shown in FIG. 8, the substitute subframe (measurement subframe) 824 has a longer duration than the normal substitute frame. Longer subframes greatly increase the total number of measurements per frame and enable more accurate measurements of the panel because more pixels can be measured within that frame time.

The steep slope of the ΔV shift (electrical aging) at the initial OLED stress time results in a curve of efficiency drop versus ΔV shift that behaves differently for low values of ΔV compared to the high ΔV range. This can result in a highly non-linear Δη-ΔV curve which is very sensitive to the initial electrical aging of the OLED or to the OLED pre-aging process. Furthermore, the shape (duration and slope) of the initial ΔV offset drop can vary significantly from panel to panel due to process variations.

The use of reference pixels and corresponding OLEDs is explained above. Since thermal effects affect active and reference pixels equally, the use of such reference pixels counteracts the effect of thermal effects on the ΔV measurement. However, instead of using an OLED with no aging (zero stress) as a reference pixel such as column reference pixel 130 in FIG. 1 , a reference pixel of an OLED with a low level of stress can be used. The thermal shock to voltage is similar to that of non-aged OLEDs, so low-stress OLEDs can still be used to remove measurement noise due to thermal effects. At the same time, since the remaining OLED-based devices on the same panel have similar fabrication conditions, the slightly stressed OLED can serve as a good reference for counteracting the effect of process differences on the Δη-ΔV curves of effective pixels in a column. If such an OLED is used as a reference, the steep early ΔV shift will also be moderated.

To use a stressed OLED as a reference, the reference OLED is stressed with a constant low current (1/5 to 1/3 of the full current), whose voltage (for a certain applied current) must be used to neutralize the pixel OLED as follows Thermal and process issues of:

$\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; pixelOLED</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref\; OLED</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref\; OLED</span>}}}$

In this equation, W is the relative electrical aging obtained based on the difference between the voltage of the effective pixel OLED and the voltage of the reference pixel OLED divided by the voltage of the reference pixel OLED. FIG. 9 is a graph 900 showing a plot 902 of points for a stress current of 268 uA based on W values. As shown in graph 900, for high pressure OLEDs, the relationship between W value and brightness drop of a pixel OLED is nearly linear as shown.

FIG. 11 is a timing diagram 1100 of pixel compensation involving reset of the pixel circuit prior to programming. Depending on process parameters, the driven pixel circuitry may be affected by unwanted artifacts such as charge trapping or fast light transitions. For example, amorphous or polysilicon processes may result in charge trapping where the pixel circuit retains a residual amount of charge in the storage capacitor after a drive cycle. The metal oxide process may cause the pixel circuitry to be more prone to fast optical transitions, such as during fast video sequences, during which pixels change rapidly. These artifacts can affect the calibration of the pixel circuitry before the pixel current is measured (to compensate for aging, process non-uniformities, or other effects). To compensate for these artifacts, the timing sequence 1100 has a reset loop 1102 . During a reset cycle 1102, the pixel circuit to be measured is programmed with a reset voltage value corresponding to a maximum voltage value or a minimum voltage value depending on the process used to manufacture the display array. For example, in a display array manufactured according to an amorphous or polysilicon process, the reset voltage value may correspond to a full black value (the value that causes the pixel circuits to display black). For example, in a display fabricated using a metal oxide process, the reset voltage value may correspond to a full white value (a value that causes the pixel circuits to display white).

During the reset cycle 1102, the effects of previous measurements on the pixel circuit (e.g., residual charge traps in the pixel circuit) are removed, as are any effects due to short-term changes in the pixel circuit (e.g., fast optical transitions ). Following the reset cycle 1102, during a calibration cycle 1104, the pixel circuits are programmed with calibration voltages based on previous extracted data or parameters of the pixel circuits. Calibration voltages can also be based on predefined current, voltage or brightness. In a calibration loop 1104, the pixel current of the pixel circuit is then measured and the extracted data or parameters of the pixel circuit are updated based on the measured current.

During a programming cycle 1106 immediately following a calibration cycle 1104, the pixel circuits are programmed with video data that is calibrated using updated extraction data or parameters. Then, in a drive cycle 1108 immediately following the programming cycle 1106, the pixel circuits are driven to emit light based on the programmed video data.

Figure 12A illustrates a pixel circuit with IR drop compensation. Because V _monitor has no effect during programming and V _data has no effect during a measurement cycle, V _monitor and V _data can be the same line (or connected together). Transistors Ta and Tb may be shared between rows and columns. The columns may share the signal line EM (Emitting Light).

FIG. 12B is a timing chart illustrating the normal operation of the pixel circuit shown in FIG. 12A. Signal WR is active and programming data (V _P ) is written into capacitor CS. At the same time, the signal line EM is disconnected and thus the other side of the capacitor CS is connected to the reference voltage V _ref . Therefore, the voltage stored in capacitor CS is (V _ref -V _P ). During a drive (emission) cycle, signal line EM is active and WR is open. Therefore, the gate-source voltage becomes V _ref -V _P independent of V _DD .

Figure 12C is a timing diagram for direct TFT readout of the circuit of Figure 12A. The pixel circuit is programmed with a calibration voltage for a known target current. In the second cycle, RD is active and the pixel current is read through V _monitor . The V _monitor voltage during the second cycle should be low enough that the OLED does not turn on. The calibration voltage is modified until the pixel current becomes the same as the target current. The modified calibration voltage is used as a point in the TFT current-voltage characteristic to extract parameters for that point. It is also possible to apply current to the pixel through V _monitor when WR is active and V _data is set to a fixed voltage. At this time, the voltage generated on V _monitor is the TFT gate voltage corresponding to the corresponding current.

Figure 12D is a timing diagram for direct OLED readout in the circuit of Figure 12A. The pixel circuit is programmed with an off voltage such that the TFT does not supply any current. During the second cycle, RD is active and the OLED current is read through V _monitor . The V _monitor voltage during the second cycle is pre-calibrated based on the known target current. Modify the V _monitor voltage until the OLED current becomes the same as the target current. The modified V _monitor voltage was used as a point in the OLED current-voltage characteristics to extract parameters for that point. The signal line EM off state can be extended to the end of the read cycle while keeping the write line WR active. In this case, the remaining pixel operations for reading the OLED will be the same as the previous steps. It is also possible to apply current to the OLED through V _monitor . At this time, the voltage generated on V _monitor is the TFT gate voltage corresponding to the corresponding current.

Figure 13A illustrates a pixel circuit with charge-based compensation. The V _monitor readout line can be shared between adjacent columns, and the transistors Ta and Tb can be shared between rows. The V _monitor line can be the same line as the V _data line or connected to the V _data line. In this case, the V _data line may be a fixed voltage (V _ref ).

FIG. 13B is a timing chart illustrating the normal operation of the pixel circuit shown in FIG. 13A. When the WR (write) and RD (read) lines are active, the programming voltage V _P and the reference voltage V _ref are applied to the pixel circuit through the V _data line and the V _monitor line. The reference voltage V _ref should be low enough that the OLED does not turn on. The read line RD can be turned off faster than the write line WR. During this time interval, transistor T1 will start charging VOLED as the generated charge will be a function of TFT parameters and thus partly compensate for TFT differences. The pixel is also immune to IR drop because the source of transistor T1 is disconnected from the supply voltage _Vdd during the programming cycle.

Direct TFT readout is depicted in the timing diagram of Figure 13C. The pixel circuit is programmed with a calibration voltage for a known target current. During the second cycle, RD is active and the pixel current is read through the V _monitor line. The V _monitor voltage during the second cycle should be low enough that the OLED will not turn on. The calibration voltage is modified until the pixel current becomes the same as the target current. The modified calibration voltage is used as a point in the TFT current-voltage characteristic to extract parameters for that point. When the write line WR is active and the data line V _data is set to a fixed voltage, current can also be applied to the pixel through V _monitor . At this time, the voltage generated on V _monitor is the TFT gate voltage corresponding to the corresponding current.

Direct OLED readout is plotted in the timing diagram of Figure 13D. The pixel circuit is programmed with an off voltage such that TFTT1 does not supply any current. During the second cycle, readout line RD is active and the OLED current is read through the V _monitor line. The V _monitor voltage during the second cycle is pre-calibrated for a known target current. Modify the V _monitor voltage until the OLED current becomes the same as the target current. The modified V _monitor voltage was used as a point in the OLED current-voltage characteristics to extract parameters for that point. The emitter line EM can be left in the off state until the end of the read cycle and the write line WR is kept active. In this case, the remaining pixel operations for reading the OLED will be the same as the previous steps. It is also possible to apply current to the OLED through V _monitor . At this time, the voltage generated on V _monitor is the TFT gate voltage corresponding to the corresponding current.

Indirect OLED readout is plotted in the timing diagram of Figure 13E. Here, the pixel current is read out in a similar manner to the operation depicted in FIG. 12 . The only difference is that during programming, RD is off and thus the gate voltage of transistor T1 is set to the OLED voltage. Therefore, in order to make the pixel current equal to the target current, the calibration voltage needs to consider the influence of OLED voltage and TFT parameters. The OLED voltage can be extracted using this calibration voltage as well as the voltage extracted from the direct TFT readout. For example, if the two target currents are the same, then subtracting the calibration voltage extracted by this process from the calibration voltage extracted by the direct TFT readout will yield the OLED effect.

Figure 14 illustrates a biased pixel circuit where the second reference voltage _Vref2 can be the same as the supply voltage _Vdd , the rows and columns can share transistors Ta and Tb, the rows can share transistors Ta and Tc, and the columns can share pixels Monitor line V _monitor . In normal operation, the write line WR and readout line RD are active and the emission line EM is disabled, the pixel voltage monitor line V _monitor is connected to the reference current I _ref and the data line V _data is connected to the voltage from the source driver programming voltage. The gate of T1 is charged to a bias voltage related to the reference current and such that the voltage stored in capacitor CS is a function of _VP and the bias voltage.

Panels can be analyzed at different stages of manufacturing to detect defects using the system described in this article. The main inspection steps can be performed after panel fabrication, after OLED fabrication and/or after full assembly. At each stage, the information provided by the above systems can be used to identify defects, which can then be repaired using different methods such as laser repair.

FIG. 15A illustrates a pixel circuit with signal lines connected to OLEDs and TFTs, and FIG. 15B illustrates the pixel circuit and ITO electrodes patterned into signal lines. To be able to measure the panel, as shown in Figure 15A, there should be a direct path to each pixel for measuring the pixel current, or part of the electrode pattern can be used for the measurement path. In the latter case, as shown in Figure 15B, the electrodes (eg, ITO or any other material) are first patterned into vertical lines, and then the electrodes are patterned to the pixels after the measurement is done.

Figure 16 illustrates a typical arrangement of panels and the signals of the panels during testing. Every other signal is connected to one pad through a multiplexer with a default section connecting the signal to a default value. Each signal can be selected through a multiplexer to program the panel or measure current/voltage/charge from the pixel.

Figure 17 illustrates a pixel circuit that can be used in factory testing to identify defects in pixels after backplane fabrication. The following tests are defined based on the pixel circuit shown in FIG. 17, but similar tests can also be performed using a different pixel circuit.

In the first test:

WR is high (Data=high and Data=low and _Vdd =high)

Here, I _{th_low} is the lowest acceptable current allowed when Data=low, and I _{th_high} is the highest acceptable current allowed when Data=high.

In the second test:

static: WR is high (Data=high and Data=low);

Dynamic: WR goes high and WR goes low after programming (Data=low to high and Data=high to low).

I _{static_high} <I _{th_high_st} I _{static_high} >I _{th_high_st} I _{dyn_high} >I _{th_high_dyn} ? T2: normal I _{dyn_high} <I _{th_high_dyn} T2: open circuit T2: short circuit

I _{th_high_dyn} is the highest acceptable current for data high in case of dynamic programming.

I _{th_high_st} is the highest acceptable current for data high in case of static programming.

The following patterns can also be used:

Static: WR is high (Data=low and Data=high)

Dynamic: WR goes high and WR goes low after programming (Data=high to low)

Figure 18 is an example pixel circuit that can be used to test an entire display. In tests across the monitor:

Measure T1 and OLED current through the V _monitor line.

Condition 1: T1 is normal after the backplane test.

_{Itft_high} is the highest possible current of the TFT current for a specific data value.

_{Itft_low} is the lowest possible current of the TFT current for a particular data value.

I _{oled_high} is the highest possible current of the OLED current for a specific OLED voltage.

I _{oled_low} is the lowest possible current of the OLED current for a specific OLED voltage.

In another test:

Measure T1 and OLED current through monitor;

Condition 2: T1 is an open circuit after the backplane test.

In yet another test:

Measure T1 and OLED current through monitor;

Condition 3: T1 is shorted by backplane test.

Detected defects can be corrected by making compensation adjustments in the display. For defects that are darker than the surrounding pixels, the surrounding pixels can be used to provide the extra brightness needed for the video/image. There are different methods for providing this extra brightness, such as:

(1) Use all immediately adjacent pixels, dividing the extra brightness between each of them. The challenge with this approach is that, in most cases, the portion assigned to each pixel is not exactly generated by that pixel. Since the error produced by each surrounding pixel will be added to the total error, the error will be very large, which reduces the effect of the correction.

(2) Using one or two of the surrounding pixels to generate the extra brightness needed for the defective pixel, the position of the active pixel in the compensation can be switched to minimize local artifacts.

Over the lifetime of the display, some soft defects can cause always-on (always on) pixels, which are often very annoying to users. Real-time measurements of the panel can identify newly created normally-on pixels, and then additional voltage can be applied through the monitor line to turn off the OLED, which turns the OLED into a dark pixel. Also, the above described compensation methods can be used to reduce the visible impact of dark pixels.

Those skilled in the computer, software, and networking arts will appreciate that the method of extracting a baseline measurement of pixels in an array may be performed by a processor, such as controller 112 in FIG. 1 , or other device that may be By using one or more general-purpose computer systems, microprocessors, digital signal processors, microcontrollers, application-specific integrated circuits (ASICs), programmable logic circuits (PLDs), field-programmable logic devices (FPLDs), and field-programmable A logic gate array (FPGA) or the like is conveniently implemented and programmed according to the teachings as described and illustrated herein.

Additionally, two or more computing systems or devices may be substituted for any one controller described herein. Thus, the principles and advantages of distributed processing, such as redundancy and replication, may also be implemented, as desired, to increase the robustness and performance of the controllers described herein.

The operations of the exemplary baseline data determination method may be performed by machine readable instructions. In these examples, machine-readable instructions include algorithms executed by (a) a processor, (b) a controller, and/or (c) one or more other suitable processing devices. The algorithm may be embodied in software stored on a physical medium such as flash memory, CD-ROM, floppy disk, hard drive, digital video (universal) disk (DVD), or other storage device, however, those of ordinary skill in the art will readily understand Alternatively, all algorithms and/or portions of algorithms may be executed by a device other than a processor, and/or embodied in firmware or dedicated hardware in a well-known manner (e.g., by an application-specific integrated circuit (ASIC), Programmable Logic Device (PLD), Field Programmable Logic Device (FPLD), Field Programmable Gate Array (FPGA) and discrete logic, etc.). For example, any or all components of the baseline data determination method may be implemented by software, hardware, and/or firmware. Also, some or all of the representative machine readable instructions may be executed manually.

19 illustrates a system for inspecting an OLED display panel 1210 at one or more stages of its manufacture (eg, a TFT backplane, a fully assembled panel, or a fully finished and sealed panel). Display panel 1210 is connected to computer 1214 through measurement electronics 1211 and probe card 1212 to provide the ability to test and validate the panel at each processing step. For example, after the TFT backplane is completed, the probe card system can be used to measure the performance of the TFT backplane alone. If the TFT backplane is acceptable, then the panel 1210 is passed to the next step, which may be an OLED deposition stage. After OLED deposition is complete, the panel 1210 can be measured for proper deposition prior to sealing. After sealing, the panel 1210 can be measured again before it is sent to the assembly process.

As can be seen in FIG. 20, the illustrated display panel 1210 has probe pads 1220 formed along three of the four edges of the panel. Probe pads are also preferably formed inside the panel before the OLED deposition stage. The probe pads 1220 are used to provide test signals to a large number of pixel circuits on the display panel 1210 via bonding pads 1230 formed at the outer ends of various signal lines leading to the pixel circuits.

FIG. 21 illustrates the connection of probe pads 1220 to pads 1230 through a multiplexer (MUX) 1240, thereby reducing the number of probe pads required, which allows the pad pitch to be increased. To ensure that other signals connected to the probe pads 1220 are properly biased, the MUX 1240 needs to be able to connect each probe pad 1220 to a common signal (Vcom) for each set of signals (e.g., source and gate signals, etc. ).

FIG. 22 illustrates a MUX 1240 with common signal control and more than two panel signals for each probe pad 1220 . FIG. 22 illustrates h panel signals connected to one probe pad 1220, thus requiring 2h control signals for connection to the probe pad 1220 or to a common signal. The connection of the panel signal to the probe pad 122 is controlled by the first switches 1241 and 1242 , and the connection of the common signal Vcom to the panel signal is controlled by the second switches 1243 and 1244 .

A suitable pad pitch for full board probing is typically around 150 microns. As shown by the data in Table 2, the pad spacing used for the most conventional configurations meets the minimum pad spacing requirements. However, as also shown by the data in Table 2, using a multiplexing ratio of 2:1 or greater enables increased pad spacing, which will allow for simpler probe cards.

Table 2 Pad spacing for different display sizes and resolutions

As shown in FIG. 23, an electronic measurement system 1213 mounted on a probe card 1212 can measure the electrical characteristics of each TFT and each OLED device on the display panel 1210 and identify defects and unevenness. This data is provided to GUI 1214 where it can be used to fine-tune each process step for higher yield, faster process ramp-up and lower line monitoring costs. Examples of various fine-tunable processes are illustrated in FIG. 23, namely, sputtering and PECVD modules 1250, in-process annealing modules 1251, patterning modules 1252, laser repair modules 1253, inkjet printing modules 1254, and evaporation modules. 1255. The end result is a complete display panel 1256 .

The circuitry shown in Figure 23 acquires data from the measurement electronics 1213, analyzes the data and displays the data in various reports, tables and graphs. Some views are described in the table below.

various The circuits and algorithms of the U.S. Patent Application, the entire contents of which are hereby incorporated by reference, can be used to extract measurements of different parameters from a display panel at different stages of its manufacture.

The inspection system can detect many potential defects and problems (for example, under sputtering and PECVD steps, the inspection system can be used to identify possible causes of defects or problems, allowing immediate fine-tuning of the manufacturing process to correct problems ) for identification. Examples of such problems and their possible causes are as follows:

For defects not directly identifiable by a single measurement by the inspection system, the first measurement can reveal the problem and specify additional tests that will eventually identify the correct defect. An example is the identification of line defects that can be detected by any of the following steps:

1. Measure the current in different lines: if the current is higher than the threshold, the pixel is shorted.

2. A pulse is applied to measure the charge transfer: if the amount of charge transferred is less than a threshold, the line is open.

3. For signals connected to DC current (eg, V _dd and V _monitor ), the current can be sensed to detect open circuit defects.

Defects in thin film transistors (TFTs) can also be inspected. For example, where the pixel circuit in FIG. 24 has a signal WR that is measured as high (when _Vdata = high, and also when _Vdata = high and _Vdd = high), an additional test needs to be performed. Table 1 shows the different conditions and what the results mean.

To detect problems associated with intermediate annealing, the exact Vt and mobility of each TFT can be used to adjust the intermediate annealing parameters as follows:

The number and type of defects can be used to identify problems in patterning (grain, under/overexposure, etc.) as follows:

Defect location and defect type can be used to pinpoint areas suitable for laser repair (removing material) or ion beam deposition (adding material), as follows:

Uniformity data can also be used to continuously calibrate each printhead used for inkjet printing in real time. The system knows which printhead was used to print each pixel, and thus can detect problems with individual printheads. The printheads used to print those pixels can then be immediately adjusted as follows:

The evaporation process can be tuned using the exact failure mode of each OLED device as follows:

The electrical characteristics (collected during TFT and OLED inspection) can be loaded into a look-up table and used to correct for all TFT and OLED inhomogeneities.

Additional defects can be identified once both the OLED and TFT are deposited. The first measurements can reveal the problem and dictate additional tests that will ultimately identify the exact defect.

If test samples are produced at the perimeter of the panel, more details about the global process parameters can be extracted. Typically, this is done by taking test samples from a small portion of the display and placing them in an individual characterization system. However, using the present inspection system, for each panel, this can be done as part of the panel characteristics, as follows.

• Metal wires can be fabricated and tested for resistance. This enables testing of metal deposition steps and etch.

- Ability to test the properties and homogeneity of the semiconductor layers to be annealed.

• Structures can be constructed at various locations around the panel to test alignment.

• OLED structures can be used to test evaporation and inkjet printing steps.

Conventional diagnostic tools used in light modulating displays (eg, AMLCD) are not useful for emissive displays (eg, AMOLED). This is mainly due to the significant difference between modulating and emissive pixel structures. Additionally, emissive pixel circuitry is more complex and thus these details cannot be identified using conventional optical diagnostic tools.

While multiple tests are required for repair and defect analysis, to avoid the time delay required for a detailed scan of all semiconductor devices, a quick scan is performed to identify defective entities (in the case of arrays, pixels and signal Wire). If the detected defect is within an acceptable preselected threshold, the manufacturing process continues. If at least one defect category exceeds an acceptable threshold, a more detailed scan is performed to identify the defect in more detail to determine whether the detected defect can be repaired. If the answer is yes, the defect is repaired, and the manufacturing process then continues.

Thresholds can be dynamic. For example, if two different defects are detected, the threshold for each defect may be different than when only one defect is detected in the panel.

The detailed scan may be optimized based on the results of the quick scan. For example, if the quick scan does not detect any line defects, then the line test can be avoided in the detailed scan.

In a fast scan, a voltage (or voltages) or a current (or currents) of the pixel is measured. If the pixel's measurements are within an acceptable range, the pixel passes the fast scan. If the pixel's measured value is outside the acceptable range, then the pixel is marked as failed.

The measured voltage or current is preferably affected by most possible defects. For example, the current supplied to the light emitting element and/or the voltage at the connection between the pixel circuit and the emitting element are well suited as targets for fast scanning.

An example of a fast scan begins by defining the lowest level of reference current or voltage encountered in a normal pixel. Alternatively, the reference current or voltage may be lower than the lowest level encountered in a normal pixel by a defined difference. Then, the measured pixel current or voltage is compared with a reference level. A pixel passes this test if the measured value is greater than the reference value. If the measured value is less than the reference value, the pixel fails this test. The results of the tests may vary based on the measured parameters. For example, if the measured value is driving the TFT current, the TFT may be open, while if the measured value is the OLED current, the OLED may be shorted.

Alternatively, the pixel can pass the test if the measured value is less than the reference value. If the measured value is greater than the reference value, the pixel fails this test. Here, the results of the tests may be different based on the measured parameters. For example, if the measured value is driving the TFT current, the TFT may be open, while if the measured value is the OLED current, the OLED may be shorted.

The combination of both tests can find more defects.

Detailed scanning can be performed by using separate bias (monitor) lines as shown in FIG. 24 or by using a common bias (monitor) line as shown in FIG. 25 .

When line scanning is performed using separate monitoring lines, if the number of faulty pixels in a column or row is greater than a threshold, then that row or column is flagged as a possible faulty line. Other examples of identifying defect columns are as follows:

1. If a column or row is shorted to another column or row, you can measure the current in both of them (or drivers) when all columns (or rows) have the same voltage and measure when at least one of the lines has a different voltage current. In the case of a short circuit, the current required to drive both lines will be higher.

2. If two columns are shorted, programming one pixel in a row will affect the current/voltage of the other pixel (regardless of programming the other pixel with a different current/voltage such as zero). In this case, measuring the current/voltage of adjacent pixels can identify the shorted column (or row).

3. The quiescent current (voltage) flowing to each line can be measured under different bias conditions. This quiescent current (voltage) can be measured indirectly through its effect on the driver current. For example, if the driver operating current varies significantly (or is above a threshold) for a line as a function of the bias condition of a line, then this means that the line is shorted.

4. Measure the transient current (voltage). If the measured current is not within the threshold, then the line can be marked as open. For example, if a transient voltage (current) is applied to the monitor line, it will generate a transient current (voltage) as a function of parasitic capacitance. When the range of the parasitic capacitance is known, the range of the current (voltage) can be calculated. If the current (voltage) is outside this range, then one can mark the line as open. Another way to estimate the range of a signal is to take measurements across the panel, and outliers can be detected and flagged as opens (if less than the range) or shorts (if greater than the range).

5. The line is charged to a certain voltage. Knowing the extent of the parasitic capacitance of the line, the extent of the charge stored in the line can be estimated. Measuring the line charge stored in the line and comparing it to the range can indicate whether the line is shorted, open or normal. If the charge is less than the estimated range, then the line is open. If the charge is within the stated range, then the circuit is normal. If the charge does not change, then the line is shorted. Another way to estimate the range of charge is to take measurements across the panel, and outliers can be detected and flagged as opens (if less than the range) or shorts (if greater than the range).

When testing transistors T2 and T3 using separate monitor lines as shown in Figure 24, the test procedure can be used for other normally-off bias switches that connect the bias lines to signal. Here, the signal may be a signal from Vdd or a signal through a monitor line. Both static and dynamic tests can be used, as follows:

static:

1. Switch closed

2. The bias voltage is high or the bias is low

3. The switch is off

4. The bias voltage maintains its voltage (if the bias voltage is high during programming, it goes low and vice versa)

Dynamic: switch goes high and switches off after programming (bias voltage = low):

1. Switch closed

2. The bias voltage is high or the bias is low

3. The switch is off

4. The bias voltage changes (if the bias voltage is high during programming, it goes low and vice versa)

If at least one of the measured currents or one of the measured voltages is normally affected by the bias voltage, and the switch performance is the same for high and low bias voltages under static conditions, then the switch is likely to be open. If this is not the case, and the current or voltage is not the same for the corresponding cases in static and dynamic operation, then the switch may be short circuited.

The detailed scan steps for driving a transistor (eg, T1) are as follows:

Current or voltage at at least one operating point of the TFT is measured.

1. If the current (voltage) is high at all points, then T1 (driving TFT) is shorted.

2. If the current (voltage) is normal at all points, then T1 (driving TFT) is normal.

3. If the current (voltage) does not change and is similar to the zero operating point, and the switch test is working, then T1 (driving TFT) is open.

4. If the current is negative (or the direction is different from that of the TFT) (or the voltage is low), the OLED is short circuited.

Some of these conclusions can be drawn using measurements at only one point.

The detailed scanning steps of OLED are as follows:

The current or voltage at at least one operating point of the OLED is measured.

1. If the current is high (or voltage is low) (in the OLED direction), the OLED is shorted.

2. If the current (voltage) is normal, the OLED is normal.

3. If there is no change in current (voltage) similar to zero operating point, and the switch test is working, the OLED is open.

4. If the current is positive (or the direction is different from that of the OLED) (or the voltage is high), then the TFT is shorted.

When using a common monitor line as shown in Fig. 25, the above test procedure for line scanning can be applied. Furthermore, if a data line is shorted between two pixels that have a common monitor line, then both pixels will generate the same current (or voltage), regardless of which data line is used for the two pixels Doing programming is irrelevant. This can be used to identify shorted data line defects. If several pixels share a line for measurement and it is not possible for some pixels to separate this line from the element under test with any switch, then different methods are required to measure different defects.

For group testing, any of the above tests for driving TFTs and/or OLEDs can be used for groups of TFTs and/or OLEDs. The only difference is that the results will show the collective performance of the device. For example, it can identify that one of the driving TFTs or OLEDs in the group is defective.

For discrimination testing, the examples below use monitor lines shared by a small number of adjacent pixels in a row (controlled with the same RD and WR signals), and they can be applied to other similar structures.

To measure devices that can be turned off using other control signals (eg, a drive TFT through _Vdata ), the device in one pixel remains active, and the devices in the other pixels are turned off. In this case, a test similar to that used for pixels with separate lines can be performed. For example, measurement of a driving TFT in a pixel can be done as follows:

1. When the driving TFTs of other pixels connected to the same monitoring line are turned off, measure the current (or voltage) of the driving TFT (T1) at one (or more) operating points;

2. Repeat step (1) for all driving TFTs of pixels connected to the same monitoring line;

3. If the current (or voltage) is within the normal range, all driving TFTs are good;

4. If the measured current (voltage) of the pixel connected to the monitor line does not change and is similar to the zero operating point, the driving TFT of this pixel may be open circuit (assuming the switching TFT test passes);

5. If the measured currents (voltages) are high and their levels are not changed by the pixels sharing the monitor line, the driving TFT of the pixel may be short-circuited. For example, if T1_1 is shorted, when measuring the current of T1_1 (T1_2 is off), the current will be I _short . When measuring T1_2, the current will be I _short +I _{T1_2} . It can be seen that only changes in the operating point of T1_2 can affect the measured current;

6. If the current (voltage) of all subpixels is low but the current varies slightly at different operating points, the OLED may be shorted. For example, if the OLED connected to T1_1 is short-circuited, the measured currents of T1_1 and T1_2 will be I _{short −IT1_1} and I _{short −IT1_2 respectively} . By changing the operating point of the TFT, the measured current will change, but the current will be much lower than normal.

When testing a biased switch as an analog device, the switch's turn-on voltage is set to the voltage that pushes the switch into a saturation state of operation. Therefore, if the driving TFT or OLED is shorted to a fixed voltage, the current (or voltage) will not be able to saturate the measurement device, and the effect of adding other pixels' current (or voltage) to the line will be greater. For example, if T1_1 is shorted, the voltage at B1_1 will be approximately V _dd . When T1_1 is measured, the current will be IT3_1 since _{T3_1} is in saturation and controls the circuit. When measuring T1_2 (the voltage at node A_2 may be high enough to turn T1_2 fully on), the current will be I _{T3_1} + I _{T3_2} . So, based on these two measurements, T1_1 is probably shorted. The same operation can be used to determine if the OLED is shorted.

To reduce the effect of one bias of the device that may be shorted, the voltage connected to the OLED, such as Vss, can be set close to the voltage of the monitor line so that it has minimal effect on the TFT measurement. A similar setting for TFT shorting can be done by setting Vdd close to the voltage of the monitor line.

The influence of the OLED (or TFT) can be transferred to another device (eg driving the TFT). For example:

1. All drive TFTs in pixels sharing a bias line (monitor line) are turned off except for one pixel.

2. Enable the voltage at the electrodes of the OLED to be set by the OLED (eg the switches influencing the voltage are open eg T3_1 and T3_2 are off in the case of the pixel in Fig. 2).

3. Then, the current driving the TFT is measured.

4. If the OLED is open, the current to the drive TFT will be close to zero (or the voltage at the terminal of the drive TFT connected to the OLED will be high).

5. If the OLED is normal, the pixel circuit will be within the normal range.

6. If the OLED is shorted, another test may be needed (eg bias switch to use as a mock device).

While particular embodiments and applications of the present invention have been illustrated and described, it should be understood that the invention is not limited to the precise constructions and compositions described herein, and without departing from the invention as defined in the appended claims. Various modifications, changes and variations of the invention will be apparent from the foregoing description, within the spirit and scope of the invention.

This application claims priority to US Patent Application 14/291231 filed May 30, 2014, which is hereby incorporated by reference in its entirety.

Claims (9)

1. during the manufacture of the semiconductor devices based on array, detect a method for the defect of described semiconductor devices, described method comprises the steps:

The defect in the described entity forming described semiconductor devices is detected in the interstage manufacturing the polytype entity forming described semiconductor devices;

Determine whether the defect detected has exceeded the pre-selected threshold of the type of the described entity detecting defect;

If described in the defect that detects do not exceed described pre-selected threshold, then continue the manufacture of described semiconductor devices; And

If described in the defect that detects exceed described pre-selected threshold, then the type of the described defect detected is identified, repairs the defect that identifies and continue the manufacture of described semiconductor devices.

2. the method for claim 1, wherein the described semiconductor devices based on array is active matrix organic light-emitting device (AMOLED) display panel.

3. method as claimed in claim 1 or 2, wherein, described polytype main body at least comprises driving transistors, OLED and signal wire.

4. the method for claim 1, wherein described pre-selected threshold changes along with the number increase of the described defect detected.

5. the method for claim 1, wherein by according to detect defect described entity type and the described type of test to defect that customize identifies.

6. the method for claim 1, wherein in described entity, detect defect by following manner: measure voltage in single pixel or electric current and the pre-selected threshold of measured value and described voltage or electric current compared.

7. method as claimed in claim 6, wherein, the described electric current of measurement is the electric current of the luminescent device flowing to described pixel.

8. method as claimed in claim 6, wherein, the described voltage of measurement is the voltage of the junction of luminescent device in image element circuit and described pixel.

9. the method for claim 1, wherein, in described entity, defect is detected: based on the minimum level pre-chosen current of the curtage in normal pixel or the datum of voltage, and compared with the described datum of corresponding preliminary election by the curtage of measurement by following manner.