CN105225948B - A kind of igbt and preparation method thereof - Google Patents
A kind of igbt and preparation method thereof Download PDFInfo
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
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Abstract
本申请公开了一种绝缘栅双极晶体管及其制备方法，其中，所述绝缘栅双极晶体管包括：第一掺杂类型的半导体衬底；位于所述半导体衬底正面内部的第二掺杂类型的阱区；位于所述阱区朝向所述半导体衬底背面一侧，且载流子浓度大于所述半导体衬底的载流子存储层；位于所述阱区中心的沟槽；位于所述沟槽两侧，且位于所述阱区内部的第一掺杂类型的发射区；位于所述沟槽两侧，且位于所述半导体衬底表面的栅极；覆盖所述栅极和沟槽表面的发射极；位于所述半导体衬底背面内部的第二掺杂类型的集区；位于所述集区背离所述半导体衬底一侧的集电极。所述绝缘栅双极晶体管具有低导通压降，并且其生产成本较低。
The present application discloses an insulated gate bipolar transistor and a manufacturing method thereof, wherein the insulated gate bipolar transistor comprises: a semiconductor substrate of a first doping type; A type of well region; a carrier storage layer located on the back side of the well region facing the semiconductor substrate and having a carrier concentration higher than that of the semiconductor substrate; a trench located in the center of the well region; located in the well region The emitter region of the first doping type located on both sides of the trench and located inside the well region; the gate located on both sides of the trench and located on the surface of the semiconductor substrate; covering the gate and the trench An emitter on the surface of the groove; a collector of the second doping type located inside the back surface of the semiconductor substrate; a collector located on the side of the collector away from the semiconductor substrate. The IGBT has a low turn-on voltage drop, and its production cost is relatively low.
Description
技术领域technical field
本发明涉及半导体器件领域，更具体地说，涉及一种绝缘栅双极晶体管及其制备方法。The invention relates to the field of semiconductor devices, in particular to an insulated gate bipolar transistor and a preparation method thereof.
背景技术Background technique
绝缘栅双极晶体管(Insulate-Gate Bipolar Transistor，IGBT)是由巨型晶体管(Giant Transistor，GTR)和金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor-Field-Effect-Transistor，MOSFET)组成的复合全控型电压驱动式功率半导体器件，兼有 MOSFET的高输入阻抗和GTR的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于工业自动化领域。Insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor, IGBT) is a combination of giant transistor (Giant Transistor, GTR) and metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor-Field-Effect-Transistor, MOSFET) Fully-controlled voltage-driven power semiconductor devices have the advantages of high input impedance of MOSFET and low conduction voltage drop of GTR. They have the characteristics of high operating frequency, simple control circuit, high current density and low on-state voltage. They are widely used Used in the field of industrial automation.
如何进一步降低所述绝缘栅双极晶体管的导通压降是工业自动化不断发展所必然要面临的问题，有报道称，以N沟道增强型绝缘栅双极晶体管为例，在其P阱远离栅极一侧的衬底区域注入N型粒子形成载流子存储层，可以提高所述N沟道增强型绝缘栅双极晶体管的载流子浓度，从而提高所述N沟道增强型绝缘栅双极晶体管衬底的载流子传输能力，进一步达到降低所述N沟道增强型绝缘栅双极晶体管导通压降的目的。How to further reduce the turn-on voltage drop of the insulated gate bipolar transistor is an inevitable problem faced by the continuous development of industrial automation. It is reported that taking the N-channel enhancement type insulated gate bipolar transistor as an example, the The substrate region on the gate side is injected with N-type particles to form a carrier storage layer, which can increase the carrier concentration of the N-channel enhanced insulated gate bipolar transistor, thereby improving the N-channel enhanced insulated gate bipolar transistor. The carrier transport capability of the bipolar transistor substrate further achieves the purpose of reducing the turn-on voltage drop of the N-channel enhanced IGBT.
但是因为所述载流子存储层位于所述P阱下方，普通的粒子注入设备难以实现，而高能粒子注入设备的价格昂贵，而且使用和维护成本高。However, because the carrier storage layer is located under the P-well, common particle injection equipment is difficult to implement, and high-energy particle injection equipment is expensive, and the cost of use and maintenance is high.
发明内容Contents of the invention
本发明实施例提供了一种绝缘栅双极晶体管及其制备方法，以解决高能粒子注入形成所述载流子存储层成本过高的问题。Embodiments of the present invention provide an insulated gate bipolar transistor and a manufacturing method thereof, so as to solve the problem of high cost of forming the carrier storage layer by injecting high-energy particles.
一种绝缘栅双极晶体管的制备方法，包括：A method for preparing an insulated gate bipolar transistor, comprising:
提供第一掺杂类型的半导体衬底；providing a semiconductor substrate of a first doping type;
在所述半导体衬底的正面内部形成第二掺杂类型的阱区，并在所述半导体衬底的正面形成所述绝缘栅双极晶体管的栅极，所述栅极覆盖所述阱区部分表面；A well region of the second doping type is formed inside the front surface of the semiconductor substrate, and a gate of the insulated gate bipolar transistor is formed on the front surface of the semiconductor substrate, and the gate covers part of the well region surface;
在所述阱区表面形成第一掺杂类型的发射区；forming an emitter region of the first doping type on the surface of the well region;
对所述发射区进行刻蚀，在所述发射区内形成沟槽，所述沟槽贯穿所述发射区；Etching the emitting region, forming a groove in the emitting region, the groove passing through the emitting region;
通过所述沟槽向所述半导体衬底注入第一掺杂类型的粒子，在所述阱区背离所述栅极一侧形成载流子浓度大于所述半导体衬底载流子浓度的载流子存储层；Injecting particles of the first doping type into the semiconductor substrate through the groove, forming a carrier with a carrier concentration greater than that of the semiconductor substrate on the side of the well region away from the gate sub-storage layer;
形成所述绝缘栅双极晶体管的发射极；forming an emitter of the insulated gate bipolar transistor;
在所述半导体衬底的背面形成所述绝缘栅双极晶体管的背面结构。A back structure of the IGBT is formed on the back of the semiconductor substrate.
优选的，通过所述沟槽向所述半导体衬底注入第一掺杂类型的粒子的注入能量的取值范围为1E5eV-3E6eV，包括端点值，剂量的取值范围为1E13cm-2-1E15cm-2，包括端点值。Preferably, the range of implantation energy for implanting particles of the first doping type into the semiconductor substrate through the trench is 1E5eV-3E6eV, including the endpoint values, and the range of dose is 1E13cm -2 -1E15cm - 2 , including endpoint values.
优选的，对所述发射区进行刻蚀，在所述发射区内形成沟槽包括：Preferably, etching the emitting region, and forming a trench in the emitting region includes:
在所述发射区表面涂覆光刻胶；Coating photoresist on the surface of the emission area;
在所述半导体衬底正面覆盖掩膜板；Covering a mask plate on the front surface of the semiconductor substrate;
以所述掩膜版为掩膜，对所述光刻胶进行曝光并显影，形成图案化的光刻胶；Using the mask plate as a mask, exposing and developing the photoresist to form a patterned photoresist;
以所述图案化的光刻胶为掩膜，对所述发射区进行刻蚀，在所述发射区内形成沟槽，所述沟槽贯穿所述发射区；Using the patterned photoresist as a mask, etching the emitting region to form a groove in the emitting region, the groove passing through the emitting region;
清除残留的光刻胶。Remove residual photoresist.
优选的，所述第一掺杂类型为N型，第二掺杂类型为P型。Preferably, the first doping type is N-type, and the second doping type is P-type.
优选的，在所述半导体衬底的背面形成所述绝缘栅双极晶体管的背面结构包括：Preferably, forming the back structure of the IGBT on the back of the semiconductor substrate includes:
通过背面减薄工艺，对所述半导体衬底的背面进行减薄处理；Thinning the back of the semiconductor substrate through a back thinning process;
在减薄后的所述半导体衬底的背面注入第二掺杂类型的粒子并退火激活，形成第二掺杂类型集区；Implanting particles of a second doping type on the backside of the thinned semiconductor substrate and annealing and activating them to form a concentration region of a second doping type;
利用磁控溅射或热蒸发工艺在所述集区上形成集电极。A collector electrode is formed on the pool using a magnetron sputtering or thermal evaporation process.
优选的，通过背面减薄工艺，对所述半导体衬底的背面进行减薄处理之后，在减薄后的所述半导体衬底的背面注入第二掺杂类型的粒子并退火激活，形成第二掺杂类型集区之前还包括：Preferably, after thinning the backside of the semiconductor substrate through the backside thinning process, particles of the second doping type are implanted on the backside of the thinned semiconductor substrate and activated by annealing to form a second Doping type pools also previously included:
在减薄后的所述半导体衬底的背面进行粒子注入，在所述半导体衬底内形成缓冲层。Particle implantation is performed on the back side of the thinned semiconductor substrate to form a buffer layer in the semiconductor substrate.
一种绝缘栅双极晶体管，包括：An insulated gate bipolar transistor comprising:
第一掺杂类型的半导体衬底；a semiconductor substrate of a first doping type;
位于所述半导体衬底正面内部的第二掺杂类型的阱区；a well region of a second doping type located inside the front side of the semiconductor substrate;
位于所述阱区朝向所述半导体衬底背面一侧，且载流子浓度大于所述半导体衬底的载流子存储层；a carrier storage layer located on the side of the well region facing the back side of the semiconductor substrate and having a carrier concentration greater than that of the semiconductor substrate;
位于所述阱区中心的沟槽；a trench at the center of the well region;
位于所述沟槽两侧，且位于所述阱区内部的第一掺杂类型的发射区；An emitter region of the first doping type located on both sides of the trench and inside the well region;
位于所述沟槽两侧，且位于所述半导体衬底表面的栅极；a gate located on both sides of the trench and on the surface of the semiconductor substrate;
覆盖所述栅极和沟槽表面的发射极；an emitter covering the surface of the gate and trench;
位于所述半导体衬底背面内部的第二掺杂类型的集区；a concentration region of a second doping type located inside the backside of the semiconductor substrate;
位于所述集区背离所述半导体衬底一侧的集电极。A collector electrode located on a side of the collector region away from the semiconductor substrate.
优选的，所述绝缘栅双极晶体管还包括：Preferably, the insulated gate bipolar transistor further includes:
位于所述集区背离所述集电极一侧的缓冲层。A buffer layer located on the side of the collector region away from the collector.
优选的，所述阱区的厚度的取值范围为1μm-7μm，包括端点值。Preferably, the thickness of the well region ranges from 1 μm to 7 μm, inclusive.
优选的，所述发射区的厚度的取值范围为0.2μm-1.5μm，包括端点值。Preferably, the thickness of the emitting region ranges from 0.2 μm to 1.5 μm, both endpoints included.
本发明实施例提供了一种绝缘栅双极晶体管及其制备方法，其中，所述制备方法通过在所述发射区刻蚀出贯穿所述发射区的沟槽，并通过所述沟槽向所述半导体衬底注入第一掺杂类型的粒子，形成所述载流子存储层。所述载流子存储层提高了所述半导体衬底的载流子浓度，实现降低所述绝缘栅双极晶体管导通压降的目的。An embodiment of the present invention provides an insulated gate bipolar transistor and a manufacturing method thereof, wherein, in the manufacturing method, a trench penetrating through the emitting region is etched in the emitting region, and the The semiconductor substrate is implanted with particles of the first doping type to form the carrier storage layer. The carrier storage layer increases the carrier concentration of the semiconductor substrate to achieve the purpose of reducing the turn-on voltage drop of the insulated gate bipolar transistor.
而且本发明实施例所提供的所述制备方法在形成所述载流子存储层之前先在所述发射区刻蚀出沟槽，降低了所述第一掺杂类型的粒子的注入深度，因此采用普通的粒子注入设备即可完成所述第一掺杂类型的粒子的注入，而不需要采用高能粒子注入设备，从而降低了低导通压降的绝缘栅双极晶体管的生产成本。Moreover, in the preparation method provided by the embodiment of the present invention, grooves are etched in the emission region before forming the carrier storage layer, which reduces the implantation depth of the particles of the first doping type, so The implantation of the particles of the first doping type can be completed by using ordinary particle implantation equipment, without using high-energy particle implantation equipment, thereby reducing the production cost of the IGBT with low conduction voltage drop.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.
图1为本发明的一个实施例提供的一种绝缘栅双极晶体管的制备方法的流程图；Fig. 1 is the flowchart of the preparation method of a kind of insulated gate bipolar transistor provided by one embodiment of the present invention;
图2为本发明实施例提供的所述半导体衬底在完成所述沟槽刻蚀后的剖面结构示意图；Fig. 2 is a schematic cross-sectional structure diagram of the semiconductor substrate provided by the embodiment of the present invention after the trench etching is completed;
图3-4为本发明实施例提供的所述半导体衬底在完成所述载流子存储层注入后的剖面结构示意图；3-4 are schematic cross-sectional structural diagrams of the semiconductor substrate provided by the embodiment of the present invention after the injection of the carrier storage layer is completed;
图5为本发明实施例提供的所述半导体衬底在完成所述发射极制备后的剖面结构示意图；5 is a schematic cross-sectional structure diagram of the semiconductor substrate provided by the embodiment of the present invention after the emitter is prepared;
图6为本发明的一个优选实施例提供的一种绝缘栅双极晶体管的制备方法的流程图；FIG. 6 is a flow chart of a method for preparing an insulated gate bipolar transistor according to a preferred embodiment of the present invention;
图7为本发明的一个实施例提供的一种绝缘栅双极晶体管的剖面结构示意图；Fig. 7 is a schematic cross-sectional structure diagram of an insulated gate bipolar transistor provided by an embodiment of the present invention;
图8为本发明的一个优选实施例提供的一种绝缘栅双极晶体管的剖面结构示意图。FIG. 8 is a schematic cross-sectional structure diagram of an IGBT provided by a preferred embodiment of the present invention.
具体实施方式Detailed ways
正如背景技术所述，绝缘栅双极晶体管导通压降的降低可以大幅度降低所述大电流设备的功耗。因此，如何降低绝缘栅双极晶体管的导通压降成为研究人员的努力方向。As mentioned in the background art, the reduction of the turn-on voltage drop of the IGBT can greatly reduce the power consumption of the high-current device. Therefore, how to reduce the turn-on voltage drop of the IGBT has become the direction of efforts of researchers.
有鉴于此，本发明实施例提供了一种绝缘栅双极晶体管的制备方法，包括：In view of this, an embodiment of the present invention provides a method for manufacturing an insulated gate bipolar transistor, including:
提供第一掺杂类型的半导体衬底；providing a semiconductor substrate of a first doping type;
在所述半导体衬底的正面内部形成第二掺杂类型的阱区，并在所述半导体衬底的正面形成所述绝缘栅双极晶体管的栅极，所述栅极覆盖所述阱区部分表面；A well region of the second doping type is formed inside the front surface of the semiconductor substrate, and a gate of the insulated gate bipolar transistor is formed on the front surface of the semiconductor substrate, and the gate covers part of the well region surface;
在所述阱区表面形成第一掺杂类型的发射区；forming an emitter region of the first doping type on the surface of the well region;
对所述发射区进行刻蚀，在所述发射区内形成沟槽，所述沟槽贯穿所述发射区；Etching the emitting region, forming a groove in the emitting region, the groove passing through the emitting region;
通过所述沟槽向所述半导体衬底注入第一掺杂类型的粒子，在所述阱区背离所述栅极一侧形成载流子浓度大于所述半导体衬底载流子浓度的载流子存储层；Injecting particles of the first doping type into the semiconductor substrate through the groove, forming a carrier with a carrier concentration greater than that of the semiconductor substrate on the side of the well region away from the gate sub-storage layer;
形成所述绝缘栅双极晶体管的发射极；forming an emitter of the insulated gate bipolar transistor;
在所述半导体衬底的背面形成所述绝缘栅双极晶体管的背面结构。A back structure of the IGBT is formed on the back of the semiconductor substrate.
相应的，本发明实施例还提供了一种绝缘栅双极晶体管，包括：Correspondingly, an embodiment of the present invention also provides an insulated gate bipolar transistor, including:
第一掺杂类型的半导体衬底；a semiconductor substrate of a first doping type;
位于所述半导体衬底正面内部的第二掺杂类型的阱区；a well region of a second doping type located inside the front side of the semiconductor substrate;
位于所述阱区朝向所述半导体衬底背面一侧，且载流子浓度大于所述半导体衬底的载流子存储层；a carrier storage layer located on the side of the well region facing the back side of the semiconductor substrate and having a carrier concentration greater than that of the semiconductor substrate;
位于所述阱区中心的沟槽；a trench at the center of the well region;
位于所述沟槽两侧，且位于所述阱区内部的第一掺杂类型的发射区；An emitter region of the first doping type located on both sides of the trench and inside the well region;
位于所述沟槽两侧，且位于所述半导体衬底表面的栅极；a gate located on both sides of the trench and on the surface of the semiconductor substrate;
覆盖所述栅极和沟槽表面的发射极；an emitter covering the surface of the gate and trench;
位于所述半导体衬底背面内部的第二掺杂类型的集区；a concentration region of a second doping type located inside the backside of the semiconductor substrate;
位于所述集区背离所述半导体衬底一侧的集电极。A collector electrode located on a side of the collector region away from the semiconductor substrate.
本发明实施例提供的一种绝缘栅双极晶体管及其制备方法，其中，所述制备方法通过在所述发射区刻蚀出贯穿所述发射区的沟槽，并通过所述沟槽向所述半导体衬底注入第一掺杂类型的粒子，形成所述载流子存储层。所述载流子存储层提高了所述半导体衬底的载流子浓度，实现降低所述绝缘栅双极晶体管导通压降的目的。The embodiment of the present invention provides an insulated gate bipolar transistor and its preparation method, wherein, in the preparation method, a trench penetrating through the emission region is etched in the emission region, and the The semiconductor substrate is implanted with particles of the first doping type to form the carrier storage layer. The carrier storage layer increases the carrier concentration of the semiconductor substrate to achieve the purpose of reducing the turn-on voltage drop of the insulated gate bipolar transistor.
而且本发明实施例所提供的所述制备方法在形成所述载流子存储层之前先在所述发射区刻蚀出沟槽，降低了所述第一掺杂类型的粒子的注入深度，因此采用普通的粒子注入设备即可完成所述第一掺杂类型的粒子的注入，而不需要采用高能粒子注入设备，从而降低了低导通压降的绝缘栅双极晶体管的生产成本。Moreover, in the preparation method provided by the embodiment of the present invention, grooves are etched in the emission region before forming the carrier storage layer, which reduces the implantation depth of the particles of the first doping type, so The implantation of the particles of the first doping type can be completed by using ordinary particle implantation equipment, without using high-energy particle implantation equipment, thereby reducing the production cost of the IGBT with low conduction voltage drop.
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
本发明实施例提供了一种绝缘栅双极晶体管的制备方法，如图1所示，包括：An embodiment of the present invention provides a method for manufacturing an insulated gate bipolar transistor, as shown in FIG. 1 , including:
S101：提供第一掺杂类型的半导体衬底。S101: Provide a semiconductor substrate of a first doping type.
在本发明的一个实施例中，所述半导体衬底优选为单晶结构的硅衬底。但需要说明的是，在本发明的其他实施例中，所述半导体衬底的种类包括但不限于：单晶、多晶或非晶体结构的硅或锗、碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。但本发明对所述半导体衬底的具体类型不做限定，具体视实际情况而定。In one embodiment of the present invention, the semiconductor substrate is preferably a silicon substrate with a single crystal structure. But it should be noted that, in other embodiments of the present invention, the types of semiconductor substrates include but are not limited to: silicon or germanium with single crystal, polycrystalline or amorphous structure, silicon carbide, indium antimonide, telluride Lead, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. However, the present invention does not limit the specific type of the semiconductor substrate, which depends on the actual situation.
S102：在所述半导体衬底的正面内部形成第二掺杂类型的阱区，并在所述半导体衬底的正面形成所述绝缘栅双极晶体管的栅极，所述栅极覆盖所述阱区部分表面。S102: Form a well region of the second doping type inside the front surface of the semiconductor substrate, and form a gate of the insulated gate bipolar transistor on the front surface of the semiconductor substrate, the gate covering the well Partial surface.
在上述实施例的基础上，在本发明的又一个实施例中，所述第一掺杂类型为N型，第二掺杂类型为P型。但在本发明的其他实施例中，所述第一掺杂类型为P型，第二掺杂类型为N型。本发明对此并不做限定，具体视实际情况而定。On the basis of the above embodiments, in yet another embodiment of the present invention, the first doping type is N-type, and the second doping type is P-type. But in other embodiments of the present invention, the first doping type is P-type, and the second doping type is N-type. The present invention does not limit this, and it depends on the actual situation.
在上述实施例的基础上，在本发明的一个具体实施例中，在所述半导体衬底的正面内部形成第二掺杂类型的阱区包括：On the basis of the above embodiments, in a specific embodiment of the present invention, forming a well region of the second doping type inside the front surface of the semiconductor substrate includes:
在所述半导体衬底的正面形成氧化层；forming an oxide layer on the front side of the semiconductor substrate;
对所述氧化层的中心区域进行光刻；performing photolithography on the central region of the oxide layer;
在光刻区域注入第二掺杂类型的粒子；implanting particles of the second doping type in the photolithographic area;
对所述半导体衬底退火，形成所述阱区。annealing the semiconductor substrate to form the well region.
在上述实施例的基础上，在本发明的一个优选实施例中，所述阱区的厚度的取值范围为1μm-7μm，包括端点值。但本发明对所述阱区的厚度的具体取值并不做限定，具体视实际情况而定。On the basis of the above embodiments, in a preferred embodiment of the present invention, the thickness of the well region ranges from 1 μm to 7 μm, inclusive. However, the present invention does not limit the specific value of the thickness of the well region, which depends on the actual situation.
在上述实施例的基础上，在本发明的另一个实施例中，在所述半导体衬底正面形成所述绝缘栅双极晶体管的栅极包括：On the basis of the above embodiments, in another embodiment of the present invention, forming the gate of the IGBT on the front surface of the semiconductor substrate includes:
在所述半导体衬底的正面通过热氧化生长工艺形成一层栅氧化层；forming a gate oxide layer on the front side of the semiconductor substrate through a thermal oxidation growth process;
在所述栅氧化层背离所述半导体衬底一侧沉积一层多晶硅层；Depositing a polysilicon layer on the side of the gate oxide layer away from the semiconductor substrate;
在所述多晶硅层上涂覆光刻胶，并覆盖掩膜板；Coating photoresist on the polysilicon layer and covering the mask plate;
对所述多晶硅层进行曝光并显影，形成所述绝缘栅双极晶体管的栅极。Exposing and developing the polysilicon layer to form the gate of the IGBT.
需要说明的是，在本发明的一个具体实施例中，在所述栅氧化层背离所述半导体衬底一侧沉积一层多晶硅层的方法为化学气相沉底法。在本发明的其他实施例中，沉积所述多晶硅层还可以采用物理气相沉积法。本发明对此并不做限定，具体视实际情况而定。It should be noted that, in a specific embodiment of the present invention, the method of depositing a polysilicon layer on the side of the gate oxide layer away from the semiconductor substrate is a chemical vapor deposition method. In other embodiments of the present invention, physical vapor deposition may also be used to deposit the polysilicon layer. The present invention does not limit this, and it depends on the actual situation.
还需要说明的是，本发明实施例仅就形成所述绝缘栅双极晶体管的阱区和栅极提供了一种可行的实施方法，但其他形成所述阱区和所述栅极的方法均适用于本发明，本发明对此并不做限定，具体视实际情况而定。It should also be noted that the embodiment of the present invention only provides a feasible implementation method for forming the well region and the gate of the IGBT, but other methods for forming the well region and the gate are all It is applicable to the present invention, which is not limited in the present invention, and depends on the actual situation.
S103：在所述阱区表面形成第一掺杂类型的发射区。S103: Form an emitter region of the first doping type on the surface of the well region.
需要说明的是，在本发明的一个具体实施例中，通过在所述阱区表面注入第一掺杂类型的粒子并扩散形成所述发射区。由于粒子注入与扩散过程已为本领域技术人员所熟知，本发明在此并不做赘述。还需要说明的是，本发明对所述发射区的形成方式并不做限定，具体视实际情况而定。It should be noted that, in a specific embodiment of the present invention, the emission region is formed by implanting and diffusing particles of the first doping type on the surface of the well region. Since the particle injection and diffusion processes are well known to those skilled in the art, the present invention will not repeat them here. It should also be noted that, the present invention does not limit the formation method of the emission region, which depends on the actual situation.
在上述实施例的基础上，在本发明的一个优选实施例中，所述发射区的厚度的取值范围为0.2μm-1.5μm，包括端点值。但本发明对所述发射区的厚度的具体取值并不做限定，具体视实际情况而定。On the basis of the above-mentioned embodiments, in a preferred embodiment of the present invention, the range of the thickness of the emission region is 0.2 μm-1.5 μm, both endpoints included. However, the present invention does not limit the specific value of the thickness of the emission region, which depends on the actual situation.
S104：对所述发射区进行刻蚀，在所述发射区内形成沟槽，所述沟槽贯穿所述发射区。S104: Etching the emission region, forming a trench in the emission region, the trench passing through the emission region.
形成所述沟槽后的所述半导体衬底的剖面如图2所示，图中所示101代表所述半导体衬底，102代表所述栅极，103代表所述发射区，104代表所述阱区，105代表所述沟槽。The cross-section of the semiconductor substrate after the trench is formed is shown in Figure 2, in which 101 represents the semiconductor substrate, 102 represents the gate, 103 represents the emission region, and 104 represents the A well region, 105, represents the trench.
在上述实施例的基础上，在本发明的另一个具体实施例中，对所述发射区103进行刻蚀，在所述发射区103内形成沟槽105包括：On the basis of the above embodiments, in another specific embodiment of the present invention, etching the emission region 103, and forming the trench 105 in the emission region 103 includes:
在所述发射区103表面涂覆光刻胶；Coating photoresist on the surface of the emission region 103;
在所述半导体衬底101正面覆盖掩膜板；covering the front surface of the semiconductor substrate 101 with a mask;
以所述掩膜版为掩膜，对所述光刻胶进行曝光并显影，形成图案化的光刻胶；Using the mask plate as a mask, exposing and developing the photoresist to form a patterned photoresist;
以所述图案化的光刻胶为掩膜，对所述发射区103进行刻蚀，在所述发射区103内形成沟槽105，所述沟槽105贯穿所述发射区103；Etching the emission region 103 by using the patterned photoresist as a mask, forming a trench 105 in the emission region 103, and the trench 105 runs through the emission region 103;
清除残留的光刻胶。Remove residual photoresist.
需要说明的是，在本发明的其他实施例中，所述沟槽105由湿法刻蚀法形成，本发明对形成所述沟槽105所采用的刻蚀方法并不做限定，具体视实际情况而定。It should be noted that, in other embodiments of the present invention, the trench 105 is formed by a wet etching method, and the present invention does not limit the etching method used to form the trench 105, depending on the actual situation. It depends.
在上述实施例的基础上，在本发明的一个优选实施例中，所述沟槽105的深度大于所述发射区103的厚度，且小于所述阱区104的厚度。本发明对所述沟槽105的深度的具体取值不做限定，具体视实际情况而定。Based on the above embodiments, in a preferred embodiment of the present invention, the depth of the trench 105 is greater than the thickness of the emitter region 103 and smaller than the thickness of the well region 104 . The present invention does not limit the specific value of the depth of the groove 105, which depends on the actual situation.
S105：通过所述沟槽105向所述半导体衬底101注入第一掺杂类型的粒子，在所述阱区104背离所述栅极102一侧形成载流子浓度大于所述半导体衬底101载流子浓度的载流子存储层。S105: Inject particles of the first doping type into the semiconductor substrate 101 through the trench 105, and form a carrier concentration higher than that of the semiconductor substrate 101 on the side of the well region 104 away from the gate 102. carrier concentration in the carrier storage layer.
需要说明的是，所述载流子存储层提高了所述半导体衬底101的载流子浓度，优化了所述半导体衬底101的载流子分布，降低了所述半导体衬底101的电阻，从而达到降低所述绝缘栅双极晶体管的导通压降的目的。It should be noted that the carrier storage layer increases the carrier concentration of the semiconductor substrate 101, optimizes the carrier distribution of the semiconductor substrate 101, and reduces the resistance of the semiconductor substrate 101. , so as to achieve the purpose of reducing the turn-on voltage drop of the IGBT.
在上述实施例的基础上，在本发明的另一个优选实施例中，通过所述沟槽105向所述半导体衬底101注入第一掺杂类型的粒子的注入能量的取值范围为1E5eV-3E6eV，，包括端点值，剂量的取值范围为1E13cm-2-1E15cm-2，包括端点值。但本发明对通过所述沟槽105向所述半导体衬底101注入第一掺杂类型的粒子的注入能量和剂量的具体取值并不做限定，具体视实际情况而定。On the basis of the above embodiments, in another preferred embodiment of the present invention, the value range of the implantation energy for implanting the first doping type particles into the semiconductor substrate 101 through the trench 105 is 1E5eV- 3E6eV, including the endpoint value, the value range of the dose is 1E13cm -2 -1E15cm -2 , including the endpoint value. However, the present invention does not limit the specific value of the implantation energy and dose for implanting the first doping type particles into the semiconductor substrate 101 through the trench 105 , depending on the actual situation.
图3和图4为本发明的一个具体实施例提供的所述半导体衬底101在形成所述载流子存储层之后的剖面图。图中106代表所述载流子存储层。3 and 4 are cross-sectional views of the semiconductor substrate 101 after the carrier storage layer is formed according to a specific embodiment of the present invention. 106 in the figure represents the carrier storage layer.
所述载流子存储层106的注入深度由第一掺杂类型的粒子的注入能量和剂量的具体取值而定。本发明对此并不做限定，具体视实际情况而定。The implantation depth of the carrier storage layer 106 is determined by the specific value of the implantation energy and dose of the first doping type particles. The present invention does not limit this, and it depends on the actual situation.
S106：形成所述绝缘栅双极晶体管的发射极。S106: Form an emitter of the IGBT.
在本发明的一个具体实施例中，利用磁控溅射工艺形成所述绝缘栅双极晶体管的发射极。但在本发明的其他实施例中，利用热蒸发工艺形成所述发射极。本发明形成所述绝缘栅双极晶体管的发射极所采用的具体工艺不做限定具体视实际情况而定。In a specific embodiment of the present invention, the emitter of the IGBT is formed by a magnetron sputtering process. However, in other embodiments of the present invention, the emitter is formed using a thermal evaporation process. The specific process adopted for forming the emitter of the IGBT in the present invention is not limited and depends on the actual situation.
形成所述绝缘栅双极晶体管的发射极之后的所述半导体衬底101的剖面如图5所示。图中所示107代表所述发射极。可以清楚的看出，由于所述沟槽105的存在，所述发射极107很好的将所述发射区103与阱区104短路，避免了闩锁效应的发生。A cross section of the semiconductor substrate 101 after forming the emitter of the IGBT is shown in FIG. 5 . 107 shown in the figure represents the emitter. It can be clearly seen that due to the existence of the trench 105 , the emitter 107 well short-circuits the emitter region 103 and the well region 104 , thereby avoiding the latch-up effect.
S107：在所述半导体衬底101的背面形成所述绝缘栅双极晶体管的背面结构。S107: Form a back structure of the IGBT on the back of the semiconductor substrate 101 .
在上述实施例的基础上，在本发明的又一个具体实施例中，在所述半导体衬底101的背面形成所述绝缘栅双极晶体管的背面结构包括：On the basis of the above embodiments, in yet another specific embodiment of the present invention, forming the back structure of the IGBT on the back of the semiconductor substrate 101 includes:
通过背面减薄工艺，对所述半导体衬底101的背面进行减薄处理；Thinning the back of the semiconductor substrate 101 through a back thinning process;
在减薄后的所述半导体衬底101的背面注入第二掺杂类型的粒子并退火激活，形成第二掺杂类型集区；Implanting particles of a second doping type on the back of the thinned semiconductor substrate 101 and annealing to activate them to form a concentration region of a second doping type;
利用磁控溅射或热蒸发工艺在所述集区上形成集电极。A collector electrode is formed on the pool using a magnetron sputtering or thermal evaporation process.
需要说明的是，本发明对在所述集区上形成集电极所采取的工艺并不做限定，在本发明的其他实施例中，在所述集区上形成集电极的工艺为化学气相沉积工艺，具体视实际情况而定。It should be noted that the present invention does not limit the process of forming the collecting electrode on the collection area. In other embodiments of the present invention, the process of forming the collecting electrode on the collection area is chemical vapor deposition The process depends on the actual situation.
在上述实施例的基础上，在本发明的一个优选实施例中，通过背面减薄工艺，对所述半导体衬底101的背面进行减薄处理之后，在减薄后的所述半导体衬底101的背面注入第二掺杂类型的粒子并退火激活，形成第二掺杂类型集区之前还包括：On the basis of the above embodiments, in a preferred embodiment of the present invention, after thinning the back of the semiconductor substrate 101 through the back thinning process, the thinned semiconductor substrate 101 Particles of the second doping type are implanted on the back side and activated by annealing, and before forming the second doping type concentration region, it also includes:
在减薄后的所述半导体衬底101的背面进行粒子注入，在所述半导体衬底101内形成缓冲层。Particle implantation is performed on the back side of the thinned semiconductor substrate 101 to form a buffer layer in the semiconductor substrate 101 .
需要说明的是，当所述半导体衬底101为N型衬底时，形成所述缓冲层注入的粒子种类包括但不限于氢、磷，当所述半导体衬底101为P型衬底时，形成所述缓冲层注入的粒子种类包括但不限于铜。本发明对形成所述缓冲层注入的粒子的具体种类并不做限定，只要能够形成所述绝缘栅双极晶体管的缓冲层即可，具体视实际情况而定。It should be noted that, when the semiconductor substrate 101 is an N-type substrate, the types of particles implanted to form the buffer layer include but not limited to hydrogen and phosphorus; when the semiconductor substrate 101 is a P-type substrate, The species of particles implanted to form the buffer layer include but not limited to copper. The present invention does not limit the specific type of particles implanted to form the buffer layer, as long as the buffer layer of the IGBT can be formed, which depends on the actual situation.
还需要说明的是，所述缓冲层通过减少少数载流子的注入及提高开关过程中的载流子复合速度，提高了所述绝缘栅双极晶体管的关断速度。并且因为所述缓冲层的存在使所述绝缘栅双极晶体管的内建电场更加稳定，从而提升了所述绝缘栅双极晶体管的击穿电压。It should also be noted that the buffer layer increases the turn-off speed of the IGBT by reducing the injection of minority carriers and increasing the recombination speed of carriers during switching. And because the existence of the buffer layer makes the built-in electric field of the IGBT more stable, thereby increasing the breakdown voltage of the IGBT.
在上述实施例的基础上，本发明的一个具体优选实施例提供了一种绝缘栅双极晶体管的制备流程，如图6所示，包括：On the basis of the above embodiments, a specific preferred embodiment of the present invention provides a manufacturing process of an insulated gate bipolar transistor, as shown in FIG. 6 , including:
S201：提供N型硅衬底；S201: providing an N-type silicon substrate;
S202：在所述硅衬底的正面形成氧化层，并对所述氧化层进行光刻；S202: forming an oxide layer on the front surface of the silicon substrate, and performing photolithography on the oxide layer;
S203：在光刻区域注入P型粒子，并对所述硅衬底进行退火处理，形成所述阱区104；S203: Implanting P-type particles into the photolithography area, and annealing the silicon substrate to form the well region 104;
S204：在所述硅衬底的正面通过热氧化生长工艺形成一层栅氧化层，并在所述栅氧化层背离所述硅衬底一侧沉积一层多晶硅层；S204: forming a gate oxide layer on the front side of the silicon substrate through a thermal oxidation growth process, and depositing a polysilicon layer on the side of the gate oxide layer facing away from the silicon substrate;
S205：在所述多晶硅层上涂覆光刻胶，并覆盖掩膜板，对所述多晶硅层进行曝光并显影，形成所述绝缘栅双极晶体管的栅极102；S205: Coating a photoresist on the polysilicon layer and covering the mask, exposing and developing the polysilicon layer to form the gate 102 of the IGBT;
S206：在所述阱区104背离所述硅衬底一侧注入N型材料形成N型发射区103；S206: Implanting an N-type material on the side of the well region 104 away from the silicon substrate to form an N-type emitter region 103;
S207：在所述栅极102和发射区103表面涂覆光刻胶并覆盖掩膜板，以所述掩膜版为掩膜，对所述光刻胶进行曝光并显影，形成图案化的光刻胶；以所述图案化的光刻胶为掩膜，对所述发射区103进行刻蚀，在所述发射区103内形成预设深度的沟槽105；S207: Coating photoresist on the surface of the gate 102 and the emission region 103 and covering the mask plate, using the mask plate as a mask, exposing and developing the photoresist to form a patterned photoresist Resist: using the patterned photoresist as a mask to etch the emission region 103 to form a groove 105 with a preset depth in the emission region 103;
S208：通过所述沟槽105向所述硅衬底注入N型粒子，在所述阱区104背离所述栅极102一侧形成载流子浓度大于所述半导体衬底101载流子浓度的载流子存储层106；S208: Inject N-type particles into the silicon substrate through the trench 105, and form a well region 104 with a carrier concentration greater than the carrier concentration of the semiconductor substrate 101 on the side of the well region 104 away from the gate 102. carrier storage layer 106;
S209：在所述硅衬底正面形成所述绝缘栅双极晶体管的发射极107；S209: Forming the emitter 107 of the IGBT on the front surface of the silicon substrate;
S210：通过背面减薄工艺，对所述硅衬底的背面进行减薄处理；S210: Thinning the backside of the silicon substrate through a backside thinning process;
S211：在减薄后的所述硅衬底的背面注入磷原子，形成所述缓冲层；S211: Implanting phosphorus atoms on the backside of the thinned silicon substrate to form the buffer layer;
S212：在减薄后的所述硅衬底的背面注入P型粒子并退火激活，形成P型集区，利用磁控溅射工艺在所述集区上形成集电极。S212: Implanting P-type particles on the backside of the thinned silicon substrate and annealing and activating to form a P-type collection area, and forming a collector on the collection area by using a magnetron sputtering process.
本发明实施例提供的所述制备方法，通过在所述发射区103刻蚀出贯穿所述发射区的沟槽105，并通过所述沟槽105向所述半导体衬底101注入第一掺杂类型的粒子，形成所述载流子存储层106。所述载流子存储层106提高了所述半导体衬底101的载流子浓度，实现降低所述绝缘栅双极晶体管导通压降的目的。In the preparation method provided by the embodiment of the present invention, a groove 105 penetrating through the emission region is etched in the emission region 103, and a first dopant is implanted into the semiconductor substrate 101 through the groove 105. type of particles, forming the carrier storage layer 106 . The carrier storage layer 106 increases the carrier concentration of the semiconductor substrate 101 to achieve the purpose of reducing the turn-on voltage drop of the IGBT.
而且本发明实施例所提供的所述制备方法在形成所述载流子存储层106之前先在所述发射区103刻蚀出沟槽105，降低了所述第一掺杂类型的粒子的注入深度，因此采用普通的粒子注入设备即可完成所述第一掺杂类型的粒子的注入，而不需要采用高能粒子注入设备，从而降低了低导通压降的绝缘栅双极晶体管的生产成本。Moreover, in the preparation method provided by the embodiment of the present invention, the groove 105 is etched in the emitter region 103 before the formation of the carrier storage layer 106, which reduces the injection of the first doping type particles. depth, so ordinary particle implantation equipment can be used to complete the implantation of the particles of the first doping type, without the need for high-energy particle implantation equipment, thereby reducing the production cost of IGBTs with low conduction voltage drop .
相应的，本发明还提供了一种绝缘栅双极晶体管，如图7所示，包括：Correspondingly, the present invention also provides an insulated gate bipolar transistor, as shown in FIG. 7 , including:
第一掺杂类型的半导体衬底101；a semiconductor substrate 101 of a first doping type;
位于所述半导体衬底101正面内部的第二掺杂类型的阱区104；A well region 104 of the second doping type located inside the front surface of the semiconductor substrate 101;
位于所述阱区104朝向所述半导体衬底101背面一侧，且载流子浓度大于所述半导体衬底101的载流子存储层106；The carrier storage layer 106 located on the side of the well region 104 facing the back side of the semiconductor substrate 101 and having a higher carrier concentration than the semiconductor substrate 101;
位于所述阱区104中心的沟槽105；a trench 105 located at the center of the well region 104;
位于所述沟槽105两侧，且位于所述阱区104内部的第一掺杂类型的发射区103；An emitter region 103 of the first doping type located on both sides of the trench 105 and inside the well region 104;
位于所述沟槽105两侧，且位于所述半导体衬底101表面的栅极102；a gate 102 located on both sides of the trench 105 and on the surface of the semiconductor substrate 101;
覆盖所述栅极102和沟槽105表面的发射极107；The emitter 107 covering the surface of the gate 102 and the trench 105;
位于所述半导体衬底101背面内部的第二掺杂类型的集区201；A concentration region 201 of the second doping type located inside the back surface of the semiconductor substrate 101;
位于所述集区201背离所述半导体衬底101一侧的集电极202。The collector electrode 202 located on the side of the collector region 201 away from the semiconductor substrate 101 .
在本发明的一个实施例中，所述半导体衬底101优选为单晶结构的硅衬底。但需要说明的是，在本发明的其他实施例中，所述半导体衬底101包括但不限于：单晶、多晶或非晶体结构的硅或锗、碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。但本发明对所述半导体衬底101的具体类型不做限定，具体视实际情况而定。In one embodiment of the present invention, the semiconductor substrate 101 is preferably a silicon substrate with a single crystal structure. But it should be noted that, in other embodiments of the present invention, the semiconductor substrate 101 includes, but is not limited to: silicon or germanium, silicon carbide, indium antimonide, lead telluride with single crystal, polycrystalline or amorphous structure , indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors, or combinations thereof. However, the present invention does not limit the specific type of the semiconductor substrate 101, which depends on the actual situation.
在上述实施例的基础上，在本发明的又一个实施例中，所述第一掺杂类型为N型，第二掺杂类型为P型。但在本发明的其他实施例中，所述第一掺杂类型为P型，第二掺杂类型为N型。本发明对此并不做限定，具体视实际情况而定。On the basis of the above embodiments, in yet another embodiment of the present invention, the first doping type is N-type, and the second doping type is P-type. But in other embodiments of the present invention, the first doping type is P-type, and the second doping type is N-type. The present invention does not limit this, and it depends on the actual situation.
在上述实施例的基础上，在本发明的一个优选实施例中，所述阱区104的厚度的取值范围为1μm-7μm，包括端点值。但本发明对所述阱区104的厚度的具体取值并不做限定，具体视实际情况而定。Based on the above embodiments, in a preferred embodiment of the present invention, the thickness of the well region 104 ranges from 1 μm to 7 μm, both endpoints included. However, the present invention does not limit the specific value of the thickness of the well region 104, which depends on the actual situation.
在上述实施例的基础上，在本发明的另一个优选实施例中，所述发射区103的厚度的取值范围为0.2μm-1.5μm，包括端点值。但本发明对所述发射区103的厚度的具体取值并不做限定，具体视实际情况而定。On the basis of the above embodiments, in another preferred embodiment of the present invention, the thickness of the emission region 103 ranges from 0.2 μm to 1.5 μm, both endpoints included. However, the present invention does not limit the specific value of the thickness of the emitting region 103, which depends on the actual situation.
在上述实施例的基础上，在本发明的又一个优选实施例中，所述沟槽105的深度大于所述发射区103的厚度，且小于所述阱区104的厚度。本发明对所述沟槽105的深度的具体取值不做限定，具体视实际情况而定。Based on the above embodiments, in another preferred embodiment of the present invention, the depth of the trench 105 is greater than the thickness of the emitter region 103 and smaller than the thickness of the well region 104 . The present invention does not limit the specific value of the depth of the groove 105, which depends on the actual situation.
在上述实施例的基础上，在本发明的一个具体实施例中，所述绝缘栅双极晶体管还包括：On the basis of the above embodiments, in a specific embodiment of the present invention, the insulated gate bipolar transistor further includes:
位于所述集区201背离所述集电极202一侧的缓冲层。A buffer layer located on the side of the collector region 201 away from the collector electrode 202 .
如图8所示，图中所示203代表所述缓冲层。As shown in FIG. 8 , 203 in the figure represents the buffer layer.
需要说明的是，所述缓冲层203通过减少少数载流子的注入及提高开关过程中的载流子复合速度，提高了所述绝缘栅双极晶体管的关断速度。并且因为所述缓冲层203的存在使所述绝缘栅双极晶体管的内建电场更加稳定，从而提升了所述绝缘栅双极晶体管的击穿电压。It should be noted that the buffer layer 203 improves the turn-off speed of the IGBT by reducing the injection of minority carriers and increasing the recombination speed of carriers during the switching process. And because the existence of the buffer layer 203 makes the built-in electric field of the IGBT more stable, thereby increasing the breakdown voltage of the IGBT.
还需要说明的是，为了表示方便，图7和图8中均为标出所述栅极102、发射极107和集电极202的引出电极。It should also be noted that, for the convenience of illustration, the extraction electrodes of the grid 102 , the emitter 107 and the collector 202 are marked in FIG. 7 and FIG. 8 .
综上所述，本发明实施例提供的一种绝缘栅双极晶体管及其制备方法，其中，所述制备方法通过在所述发射区103刻蚀出贯穿所述发射区的沟槽105，并通过所述沟槽105向所述半导体衬底101注入第一掺杂类型的粒子，形成所述载流子存储层106。所述载流子存储层106提高了所述半导体衬底101的载流子浓度，实现降低所述绝缘栅双极晶体管导通压降的目的。To sum up, the embodiment of the present invention provides an insulated gate bipolar transistor and its manufacturing method, wherein, in the manufacturing method, a trench 105 penetrating through the emitting region is etched in the emitting region 103, and The first doping type particles are implanted into the semiconductor substrate 101 through the trench 105 to form the carrier storage layer 106 . The carrier storage layer 106 increases the carrier concentration of the semiconductor substrate 101 to achieve the purpose of reducing the turn-on voltage drop of the IGBT.
而且本发明实施例所提供的所述制备方法在形成所述载流子存储层106之前先在所述发射区103刻蚀出沟槽105，降低了所述第一掺杂类型的粒子的注入深度，因此采用普通的粒子注入设备即可完成所述第一掺杂类型的粒子的注入，而不需要采用高能粒子注入设备，从而降低了低导通压降的绝缘栅双极晶体管的生产成本。Moreover, in the preparation method provided by the embodiment of the present invention, the groove 105 is etched in the emitter region 103 before the formation of the carrier storage layer 106, which reduces the injection of the first doping type particles. depth, so ordinary particle implantation equipment can be used to complete the implantation of the particles of the first doping type, without the need for high-energy particle implantation equipment, thereby reducing the production cost of IGBTs with low conduction voltage drop .
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related information, please refer to the description of the method part.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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| CN100452428C (en) * | 2003-11-12 | 2009-01-14 | 丰田自动车株式会社 | trench gate field effect device |
| CN101582443A (en) * | 2008-05-13 | 2009-11-18 | 三菱电机株式会社 | Semiconductor device |
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| JP2001332728A (en) * | 2000-05-22 | 2001-11-30 | Fuji Electric Co Ltd | IGBT |
| CN100452428C (en) * | 2003-11-12 | 2009-01-14 | 丰田自动车株式会社 | trench gate field effect device |
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