CN105159384A - Self-feedback control circuit - Google Patents

Abstract

A self-feedback control circuit is connected with a controller area network bus to control a high voltage output level and a low voltage output level of an output end, wherein the self-feedback control circuit comprises a controller area driving circuit and a copy circuit. The replica circuit is connected in parallel with the controller area driving circuit and has an upper feedback circuit and a lower feedback circuit. The upper feedback circuit and the lower feedback circuit are connected to a common point, and the replica circuit generates a feedback signal from the common point, so that the feedback signal can be controlled by the upper feedback circuit and the lower feedback circuit respectively and transmitted to two transistors of the controller area driving circuit, thereby completing the DC level control of the high and low voltage output levels.

Description

Self-feedback control circuit

technical field

The invention relates to a control circuit; in particular, it relates to a self-feedback control circuit which can be widely used in application systems such as a controller local area network bus and has double feedback paths.

Background technique

Controller Area Network (CAN) is a specification formulated in the early 1990s and standardized (ISO11898-1) in 1993, and is widely used in various vehicles and electronic devices. Generally speaking, a controller area network (CAN) includes a serial bus, which provides a high level of security and efficient real-time control, and also has a mechanism for error detection and priority determination, so that under such a mechanism, network messages The transmission becomes more reliable and efficient. Judging from the current development, the existing controller local area network not only has a high degree of flexible adjustment capability, but also can add stations to the existing network without making corrections and adjustments on software and hardware. , the transmission of its information is not built on a special type of platform, which increases the convenience when upgrading the network.

Generally speaking, FIG. 1 discloses a structure diagram of a controller area network bus in the prior art, wherein, for example, there are two stations in the controller area network, which are a station 21 and a station 23, via a control transceiver (CAN-Transceiver) 11 They are commonly connected to the bus 30 and transmit differential signals through a high voltage output level CANH and a low voltage output level CANL to achieve control signal transmission. In the existing digital logic, as shown in Figure 2, when the high-voltage output level CANH and the low-voltage output level CANL are both 2.5 volts, the output digital signal is "1". As for, if When the high voltage output level CANH jumps to 3.5 volts, and the low voltage output level CANL drops to 1.5 volts, the output digital signal represents "0". Among them, in today's fine division of labor, in order to maintain the DC stability of the high-voltage output level CANH and the low-voltage output level CANL, the prior art such as US Pat. Circuit design, the driving circuit is mainly composed of an output circuit and a preamplifier, and a single loop control circuit is used to control the driving voltage source of the preamplifier, so that the output equivalent resistance (Ron) on one side of the circuit can be Equivalent to the equivalent resistance of the output stage on the other side, so as to achieve the effect of DC voltage regulation control.

However, it is worth noting that in order to achieve such a circuit design, a large number of electronic circuit components must be used in both the system design end and the chip design end, and at most it can only start with different connection methods in the logic circuit. to circumvent. Under such circumstances, it will not only make the design of the overall circuit extremely difficult, but also greatly increase the number of components and circuit cost, which is not economical and cost-effective.

Therefore, the inventor feels that the above-mentioned defects can be improved, and based on the relevant experience in this field for many years, carefully observes and studies, and cooperates with the application of theories, and proposes a novel design that can effectively improve the above-mentioned defects. The invention discloses a self-feedback control circuit, and its specific structure and implementation will be described in detail below.

Contents of the invention

In order to solve the problems existing in the prior art, an object of the present invention is to provide a self-feedback control circuit, which is the first to disclose a completely innovative circuit design, and through this design to achieve precise control of the output stage DC voltage signal .

Another object of the present invention is to provide a self-feedback control circuit, which utilizes a replica circuit which includes an upper and a lower feedback circuit to generate a feedback signal from a common state point, so that the feedback signal can be automatically Feedback controls the gates of the upper and lower transistors, thereby completing the DC level control of the output stage voltage.

Another object of the present invention is to provide a self-feedback control circuit, which can be widely used in other industrial control systems in addition to the controller area network bus, so as to maintain the stability of the output stage DC differential signal .

Therefore, according to the self-feedback control circuit disclosed in the present invention, it is connected to a controller area network bus to control a high voltage output level and a low voltage output level of the controller area network bus. According to an embodiment of the present invention, the self-feedback control circuit includes a controller area driving circuit and a replica circuit. Wherein, the controller area drive circuit is connected to the controller area network bus, and includes a first transistor, a second transistor, a first passive component and a second passive component, and the first transistor and the first passive component are serially connected in series. Connected between an input power supply and the high voltage output level, the second transistor and the second passive component are sequentially connected in series between a ground terminal and the low voltage output level.

The duplication circuit is connected in parallel to the drive circuit in the controller area, and the duplication circuit has an upper feedback circuit and a lower feedback circuit, wherein the upper feedback circuit and the lower feedback circuit are connected to a common point, and the duplication circuit is from then on The common state point generates a feedback signal, so that the feedback signal can be transmitted to the first transistor and the second transistor of the controller area driving circuit through the upper feedback circuit and the lower feedback circuit respectively, thereby completing the output DC level control of high voltage output level and low voltage output level.

According to an embodiment of the present invention, the upper feedback circuit further includes a third transistor, a third passive component and a third resistor, and the third transistor, the third passive component and the third resistor are sequentially connected to the input between the power supply and the common state point. The lower feedback circuit further includes a fourth transistor, a fourth passive component and a fourth resistor, and the fourth transistor, the fourth passive component and the fourth resistor are sequentially connected in series between the ground terminal and the common point. Under this design, the third transistor is connected to the first transistor of the controller area driving circuit, and the fourth transistor is connected to the second transistor of the controller area driving circuit.

Furthermore, according to an embodiment of the present invention, wherein the resistance of the third resistor is designed to be n times that of an output resistor in the controller area network bus, the currents of the third transistor and the third passive component are respectively the controller area The first transistor of the drive circuit is 1/n times the first passive component. Similarly, the resistance of the fourth resistor is designed to be n times that of an output resistor in the controller area network bus, and the current of the fourth transistor and the fourth passive component is the second transistor and the first transistor of the controller area drive circuit. 1/n times of two passive components, n is a positive integer.

Therefore, through the ingenious design of the self-feedback control circuit disclosed in the present invention, it can successfully fix the voltage difference between the high-voltage output level and the low-voltage output level of the output stage to 2 volts, and the direct current of the sum of the voltages The deviation value is controlled below 100 millivolts, and the stability of the DC voltage signal is maintained, thereby realizing precise control of the output stage DC level signal and achieving the purpose of the invention.

In the following, a detailed description will be made through specific embodiments and accompanying drawings, so that it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

FIG. 1 is a structure diagram of a controller area network bus in the prior art.

FIG. 2 is a waveform diagram of an output stage voltage signal of a controller area network bus in the prior art.

FIG. 3 is a schematic structural diagram of a self-feedback control circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an internal circuit of a self-feedback control circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the operation of the self-feedback control circuit according to the embodiment of the present invention.

FIG. 6 is a schematic waveform diagram of a self-feedback control circuit applied to a controller area network bus according to an embodiment of the present invention.

FIG. 7 is a schematic circuit diagram of a self-feedback control circuit according to another embodiment of the present invention.

Explanation of reference signs: 1-self-feedback control circuit; 11-control transceiver; 20-controller local area network bus; 21-platform; 22-up feedback circuit; 22'-up feedback circuit; 23-platform; 24-lower feedback circuit; 24'-lower feedback circuit; 30-bus; 100-controller area drive circuit; 100'-controller area drive circuit; 200-copy circuit; M1, M2, M3, M4, M5 , M6, M7, M8-transistors; D1, D2, D3, D4-passive components; R0, R3, R4-resistors.

Detailed ways

The above description about the content of the present invention and the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and provide further explanation of the patent application scope of the present invention. Regarding the characteristics, implementation and effects of the present invention, preferred embodiments are described in detail below in conjunction with the drawings.

Please refer to FIG. 3 , which is a schematic structural diagram of a self-feedback control circuit according to an embodiment of the present invention. As shown in FIG. 3 , the self-feedback control circuit 1 disclosed by the present invention is electrically coupled to a controller area network bus (ControllerAreaNetworkBUS, CANBUS) 20 . Wherein, the controller area network bus 20 transmits differential signals through a high voltage output level CANH and a low voltage output level CANL, and transmits differential signals between the high voltage output level CANH and an intermediate output level SPLIT , and between the intermediate output level SPLIT and the low-voltage output level CANL, respectively, an output resistor R0 (or terminal resistor) is connected in series. Generally speaking, the resistance value of the output resistor R0 can be selected as 60 ohms, for example, to form an impedance of 120 ohms after the two output resistors R0 are connected in series. However, those who are familiar with this technical field can design by themselves according to actual circuit requirements, which is not intended to limit the scope of the present invention.

According to an embodiment of the present invention, the self-feedback control circuit 1 includes a controller area driving circuit 100 and a replica circuit 200 connected in parallel to the controller area driving circuit 100 . Please refer to FIG. 4 , which is a schematic diagram of the internal circuit of the self-feedback control circuit disclosed in the embodiment of the present invention. As shown in the figure, the controller area driving circuit 100 is electrically coupled to the controller area network bus 20, and the controller area driving circuit 100 includes a first transistor M1, a second transistor M2, and a first passive device D1 , and a second passive component D2, wherein the first transistor M1 and the first passive component D1 are sequentially connected in series between an input power supply VDD and a high voltage output level CANH, the second transistor M2 and the second passive component D2 is sequentially connected in series between a ground terminal GND and the low voltage output level CANL.

The replica circuit 200 is connected in parallel with the controller area driving circuit 100 and has a double-loop structure, which includes an upper feedback circuit 22 and a lower feedback circuit 24 . Wherein, the upper feedback circuit 22 and the lower feedback circuit 24 are connected to a common state point VCM, and the replica circuit 200 generates a feedback signal FB from the common state point VCM, so that the feedback signal FB can be passed through the upper feedback signal FB respectively. The granting circuit 22 and the lower feedback circuit 24 are controlled and transmitted to the first transistor M1 and the second transistor M2, thereby completing the DC level control of the high voltage output level CANH and the low voltage output level CANL.

FIG. 5 discloses a schematic diagram of the operation of the self-feedback control circuit of the embodiment of the present invention. Please also refer to FIG. 4. In detail, the upper feedback circuit 22 includes a third transistor M3, a third passive component D3 and A third resistor R3, and the lower feedback circuit 24 includes a fourth transistor M4, a fourth passive component D4 and a fourth resistor R4, wherein the third transistor M3, the third passive component D3 and the third resistor R3 The fourth transistor M4, the fourth passive device D4 and the fourth resistor R4 are serially connected between the ground terminal GND and the common point VCM in sequence. In the description of this example, the present invention adopts that both the first transistor M1 and the third transistor M3 are P-type metal oxide semiconductor field effect transistors (Pmetal oxide semiconductor, PMOS), and the second transistor M2 and the fourth transistor M4 are both N-type transistors. The metal oxide semiconductor field effect transistor (NMOS), the first passive device D1 , the second passive device D2 , the third passive device D3 and the fourth passive device D4 are each diodes, as an illustration of an embodiment of the present invention.

According to an embodiment of the present invention, in this case, the third transistor M3 is connected to and controls the gate of the first transistor M1 , and the fourth transistor M4 is connected to and controls the gate of the second transistor M2 . In addition, for the further design and selection of the circuit, regarding the impedance and size of each component, the present invention designs that the resistance value of the third resistor R3 should be n times that of the output resistor R0, and the third transistor M3 and the first The currents of the three passive devices D3 are each 1/n times that of the first transistor M1 and the first passive device D1, and n is a positive integer. Similarly, as far as the lower feedback circuit 24 is concerned, the resistance of the fourth resistor R4 should be n times that of the output resistor R0, and the currents of the fourth transistor M4 and the fourth passive component D4 are also equal to the currents of the second transistor M2 and the fourth transistor M2 respectively. 1/n times of the second passive component D2, where n is a positive integer. From this point of view, the present invention mainly uses the ingenious design of the upper and lower loops 22, 24 of the replica circuit 200 for signal feedback, and simultaneously matches the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M1. Between the transistor M4, the first passive component D1, the second passive component D2, the third passive component D3, the fourth passive component D4, the third resistor R3, the fourth resistor R4, and the output resistor R0, the resistance value and size of each component The multiple relationship setting is used to complete the DC level control of the high-voltage output level CANH and the low-voltage output level CANL of the output stage, and realize the inventive purpose of the present invention.

FIG. 6 discloses a schematic waveform diagram of a self-feedback control circuit applied to a controller area network bus according to an embodiment of the present invention. From the waveform diagram shown in Figure 6, it can be clearly seen that when the architecture design of the self-feedback control circuit disclosed in the present invention is applied, the voltage value of the intermediate output level SPLIT can be successfully made to be the high voltage output level CANH Half of the sum of the low voltage output level CANL, that is, the control intermediary output level SPLIT=(CANH+CANL)/2. At the same time, for the differential signal of the output stage of the controller area network bus, the voltage difference T1 between the high-voltage output level CANH and the low-voltage output level CANL can also be controlled to be fixed within a range, for example: Between 1.5 volts and 3 volts, preferably 2 volts. In addition, when the overall circuit is alternately switched between the active mode (Dominant mode) and the passive mode (Recessive mode), the deviation value (Offset) of the DC voltage sum of the high voltage output level CANH and the low voltage output level CANL U1 and U2 can be controlled below 100 millivolts (mV). Therefore, according to the evidence and data disclosed above, the self-feedback control circuit disclosed in the present invention can indeed implement an effective DC level for the voltage of the output stage. Control, and can be widely used in application systems such as controller area network bus (CANBUS) or other industrial control systems. It is actually a well-designed self-feedback control circuit design with excellent performance.

On the other hand, FIG. 7 discloses a schematic circuit diagram of a self-feedback control circuit according to another embodiment of the present invention. Different from the previous embodiment ( FIG. 4 ), in consideration of the overall circuit withstand voltage and control, the controller region driving circuit 100 ′ in this embodiment may further include at least one fifth transistor M5 and At least one sixth transistor M6, wherein the fifth transistor M5 is connected in series between the first transistor M1 and the first passive component D1, and the sixth transistor M6 is connected in series between the second transistor M2 and the second passive component D2 . Furthermore, the number of the fifth transistor M5 can be one alone or more than one can be connected in series at the same time. Similarly, the number of the sixth transistor M6 can also be selected to be one alone or more than one can be connected in series at the same time. In FIG. 7 shown in this embodiment, the present invention is described by taking the controller area driving circuit 100' including a single fifth transistor M5 and a sixth transistor M6 as an example, but it is not intended to limit the invention of the present invention. category. In other words, if a person familiar with this technical field chooses to connect the plurality of fifth transistors M5 or the plurality of sixth transistors M6 in series after considering the withstand voltage design of the circuit, it should fall within the scope of the present invention.

Therefore, in another embodiment of the present invention, corresponding to the fifth transistor M5, the upper feedback circuit 22' further includes at least one seventh transistor connected in series between the third transistor M3 and the third passive component D3. The transistor M7, wherein both the fifth transistor M5 and the seventh transistor M7 are P-type metal oxide semiconductor field effect transistors (PMOS), and the number of the seventh transistor M7 should correspond to the number of the fifth transistor M5. Similarly, corresponding to the sixth transistor M6, the lower feedback circuit 24' further includes at least one eighth transistor M8 connected in series between the fourth transistor M4 and the fourth passive device D4, wherein the sixth transistor M6 and The eighth transistors M8 are all N-type metal oxide semiconductor field effect transistors (NMOS), and the number of the eighth transistors M8 should also correspond to the number of the sixth transistors M6. In addition, the current of the seventh transistor M7 is designed to be 1/n times that of the fifth transistor M5, and the current of the eighth transistor M8 is designed to be 1/n times that of the sixth transistor M6, where n is a positive integer.

Therefore, in summary, according to the self-feedback control circuit disclosed in the present invention, it is a novel and unique circuit design, which not only can statically control the output voltage of the controller local area network bus, but also make the The differential signal output in the active mode can be maintained at about 2 volts, and the surge can still be controlled within the specification range when the circuit is switched between the active mode and the passive mode through dynamic control. From this point of view, compared with the prior art, the present invention not only has the advantages of low complexity, low cost and high efficiency in circuit design, but also enables the overall circuit to have an excellent DC level control function, Compared with the prior art, it has excellent industrial applicability and competitiveness.

The above description is only illustrative, rather than restrictive, to the present invention. Those of ordinary skill in the art understand that many modifications and changes can be made without departing from the spirit and scope defined by the following appended claims. Or equivalent, but all will fall within the protection scope of the present invention.

Claims (16)

1. a self-feedback control circuit, connects a CAN bus, and to control a high voltage output level and a low-voltage output level of this CAN bus, it is characterized in that, this self-feedback control circuit includes:

One controller region driving circuit, connect this CAN bus, this controller region driving circuit includes a first transistor, a transistor seconds, one first passive component and one second passive component, wherein this first transistor and this first passive component are sequentially serially connected with between an input power and this high voltage output level, and this transistor seconds and this second passive component are sequentially serially connected with between an earth terminal and this low-voltage output level; And

One duplicate circuit, this controller region driving circuit in parallel, this duplicate circuit to have on one feedback loop and once feedback loop, and feedback loop and this lower feedback loop are connected to a common-mode point jointly on this, wherein, this duplicate circuit produces a feedback signal from this common-mode point, make this feedback signal be sent to this first transistor and this transistor seconds via feedback loop on this and this lower feedback loop respectively, to complete, the DC level of this high voltage output level and this low-voltage output level is controlled.

2. self-feedback control circuit according to claim 1, it is characterized in that, this CAN bus more includes at least two output resistances, wherein this output resistance is series between this high voltage output level and intermediary's output level, and another this output resistance is series between this intermediary's output level and this low-voltage output level.

3. self-feedback control circuit according to claim 2, it is characterized in that, on this, feedback loop more includes a third transistor, one the 3rd passive component and one the 3rd resistance, this third transistor, the 3rd passive component and the 3rd resistance are sequentially serially connected with between this input power and this common-mode point, and this third transistor connects this first transistor of this controller region driving circuit.

4. self-feedback control circuit according to claim 3, it is characterized in that, this lower feedback loop more includes one the 4th transistor, one the 4th passive component and one the 4th resistance, 4th transistor, the 4th passive component and the 4th resistance are sequentially serially connected with between this earth terminal and this common-mode point, and the 4th transistor connects this transistor seconds of this controller region driving circuit.

5. self-feedback control circuit according to claim 4, it is characterized in that, the resistance of the 3rd resistance is n times of this output resistance, the electric current of this third transistor and the 3rd passive component is this first transistor of this controller region driving circuit and 1/n times of this first passive component separately, and n is positive integer.

6. self-feedback control circuit according to claim 5, it is characterized in that, the resistance of the 4th resistance is n times of this output resistance, the electric current of the 4th transistor AND gate the 4th passive component is this transistor seconds of this controller region driving circuit and 1/n times of this second passive component separately, and n is positive integer.

7. self-feedback control circuit according to claim 6, is characterized in that, this first transistor and this third transistor are P type metal-oxide half field effect transistor.

8. self-feedback control circuit according to claim 6, is characterized in that, this transistor seconds and the 4th transistor are N-type metal-oxide half field effect transistor.

9. self-feedback control circuit according to claim 6, is characterized in that, this first passive component, this second passive component, the 3rd passive component and the 4th passive component are a diode separately.

10. self-feedback control circuit according to claim 4, wherein this controller region driving circuit more comprises at least one 6th transistor of at least one 5th transistor AND gate, this at least one 5th strings of transistors is connected between this first transistor and this first passive component, and this at least one 6th strings of transistors is connected between this transistor seconds and this second passive component.

11. self-feedback control circuits according to claim 10, it is characterized in that, on this, feedback loop more comprises at least one 7th transistor, it is serially connected with between this third transistor and the 3rd passive component, and the magnitude setting of this at least one 7th transistor is to should the quantity of at least one 5th transistor.

12. self-feedback control circuits according to claim 11, is characterized in that, the 5th transistor AND gate the 7th transistor is P type metal-oxide half field effect transistor.

13. self-feedback control circuits according to claim 12, is characterized in that, the current design of the 7th transistor is 1/n times of the 5th transistor of this controller region driving circuit, and n is positive integer.

14. self-feedback control circuits according to claim 11, it is characterized in that, this lower feedback loop more comprises at least one 8th transistor, it is serially connected with between the 4th transistor AND gate the 4th passive component, and the magnitude setting of this at least one 8th transistor is to should the quantity of at least one 6th transistor.

15. self-feedback control circuits according to claim 14, is characterized in that, the 6th transistor AND gate the 8th transistor is N-type metal-oxide half field effect transistor.

16. self-feedback control circuits according to claim 15, wherein the current design of the 8th transistor is 1/n times of the 6th transistor of this controller region driving circuit, and n is positive integer.