CN105097911A - HEMT device with junction type semiconductor layer - Google Patents

Abstract

The invention belongs to the technical field of semiconductors, and in particular relates to a HEMT device with a junction semiconductor layer. The device of the present invention mainly grows a junction semiconductor layer on the upper surface of the barrier layer between the gate and drain, and the junction semiconductor layer and the barrier layer form two-dimensional hole gas (2DHG). The gate metal and the junction semiconductor layer form a rectification structure to avoid the gate-2DHG-2DEG leakage current when a positive voltage is applied to the gate. At the same time, an isolation layer is used between the drain electrode and the junction semiconductor to block 2DHG; on the other hand, the gate The 2DHG and 2DEG between the drains form a polarized superjunction, which assists in depleting the drift region in the blocking state, effectively improving the electric field concentration effect at the drain end of the device gate. At the same time, in the P-type doped region and the N-type doped region The contact part of the device will introduce a new electric field spike, which will make the electric field distribution on the surface of the device more uniform, thereby increasing the off-state breakdown voltage of the device. The invention is particularly applicable to HEMT devices.

Description

A HEMT device with a junction semiconductor layer

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a HEMT (High Electron Mobility Transistor, High Electron Mobility Transistor) device with a junction semiconductor layer.

Background technique

The wide bandgap semiconductor gallium nitride (GaN) has the characteristics of high critical breakdown electric field (~3.3×106V/cm), high electron mobility (~2000cm2/V s), and the heterojunction based on GaN material has high electronic The mobility transistor (HEMT) also has a high-concentration (~1013cm-2) two-dimensional electron gas (2DEG) channel, which makes GaNHEMT devices have high reverse blocking voltage, low forward conduction resistance, and high operating frequency. The application field of high current, low power consumption and high voltage switching devices has great application prospects.

The key to power switching devices is to achieve high breakdown voltage, low on-resistance and high reliability. The breakdown of HEMT devices is mainly caused by the leakage current of the gate Schottky junction and the leakage current through the buffer layer. To improve the withstand voltage of the device, the thickness and quality of the buffer layer need to be increased in the vertical direction, which is mainly determined by the technological level; the length of the drift region needs to be increased in the lateral direction, which not only increases the chip area and cost of the device (or circuit), but also increases the cost. More seriously, the on-resistance of the device increases, which in turn leads to a sharp increase in power consumption, and the switching speed of the device is also reduced.

In order to make full use of the excellent characteristics of GaN materials such as high critical breakdown electric field and improve device withstand voltage, researchers in the industry have conducted many studies. Among them, the field plate technology is a common terminal technology used to improve the withstand voltage of the device. The literature (J.Li, et.al. "Highbreakdownvoltage GaNHFET with fieldplate" IEEE Electron Lett., vol.37, no.3, pp.196-197, February. 2001.) A field plate shorted to the gate is used, as shown in Figure 1, the introduction of the field plate can reduce the curvature effect of the main junction and the electric field spike, thereby improving the withstand voltage. However, the introduction of the field plate will increase the parasitic capacitance of the device, which will affect the high frequency and switching characteristics of the device. (AkiraNakajima, et.al. "GaN-BasedSuperHeterojunctionFieldEffectTransistorsUsingthePolarizationJunctionConcept" IEEE ElectronDeviceLetters, vol.32, no.4, pp.542-544, 2011) Using the idea of polarized superjunction, a GaN on the top layer of the layer, and two-dimensional hole gas (2DHG) is formed at its interface. The 2DHG and the 2DEG below form a natural "superjunction". To achieve the purpose of improving the withstand voltage, as shown in Figure 2. However, the top-layer GaN forms an ohmic contact with the gate electrode, and when the gate is conducting forward, a gate leakage current will be generated when the gate voltage is high, which limits the gate voltage swing.

For AlGaN/GaN HEMT devices, enhancement mode (normally off) HEMT devices have more advantages than depletion mode (normally on) HEMT devices, and its implementation technology is also a matter of great concern to researchers. Literature (W.Saito, et.al., "Recessed-gatestructure approachtoward normally off high-voltageAlGaN/GaNHEMTforpowerelectronicsapplications," IEEETrans.ElectronDevices, vol.53, no.2, pp.356-362, 2006) reported the use of a trench gate structure to achieve a Quasi-enhanced high-voltage AlGaN/GaN HEMT, as shown in Figure 3, the recessed gate etching can effectively deplete the 2DEG concentration under the gate and greatly increase the threshold voltage, but the recessed gate etching needs to precisely control the etching depth and reduce the Etch damage caused by plasma treatment.

Contents of the invention

What the present invention aims to solve is to propose a HEMT device with a junction semiconductor layer in view of the above problems.

To achieve the above object, the present invention adopts the following technical solutions:

A HEMT device with a junction semiconductor layer, comprising a substrate 1, a buffer layer 2 arranged on the upper surface of the substrate 1 and a barrier layer 3 arranged on the upper surface of the buffer layer 2, the buffer layer 2 and the barrier layer The contact surface of 3 forms a first heterojunction with a two-dimensional electron gas channel; the two ends of the upper surface of the barrier layer 3 respectively have a source electrode 4 and a drain electrode 5, and the middle part of the upper surface of the barrier layer 3 has a gate structure; the upper surface of the barrier layer 3 between the source electrode 4 and the gate structure has a dielectric passivation layer 10, and the upper surface of the barrier layer 3 between the drain electrode 5 and the gate structure has a junction semiconductor layer 8; the contact surface of the junction semiconductor layer 8 and the barrier layer 3 forms a second heterojunction with two-dimensional hole gas; it is characterized in that the junction semiconductor layer 8 is composed of a P-type doped region 81 and An N-type doped region 82 is formed, the P-type doped region 81 is connected to the gate structure, and an isolation layer 11 capable of blocking two-dimensional hole gas is provided between the N-type doped region 82 and the drain electrode 5; The gate structure is composed of an insulating gate dielectric 7 and a metal gate electrode 6. The insulating gate dielectric 7 is respectively connected to the dielectric passivation layer 10, the barrier layer 3 and the P-type doped region 81, and its cross-sectional shape is U type structure, the metal gate electrode 6 is located in the insulating gate dielectric 7, the metal gate electrode 6 extends along the lateral direction of the device and covers the upper surface of the insulating gate dielectric 7; the metal gate electrode 6 also extends to the P-type doped A rectifying structure 9 is formed between the upper surface of the impurity region 81 and the junction semiconductor layer 8 .

In the general technical solution of the present invention, a junction semiconductor layer is grown on the upper surface of the barrier layer between the gate and drain, and the junction semiconductor layer and the barrier layer form a two-dimensional hole gas (2DHG). The gate metal and the junction semiconductor layer form a rectification structure to avoid the gate-2DHG-2DEG leakage current when a positive voltage is applied to the gate. At the same time, an isolation layer is used between the drain electrode and the junction semiconductor to block 2DHG; on the other hand, the gate The 2DHG and 2DEG between the drains form a polarized superjunction, which assists in the depletion of the drift region in the blocking state, effectively improving the electric field concentration effect at the drain end of the device gate. At the same time, in the P-type doped region and the N-type doped region The contact part of the device will introduce a new electric field spike, which will make the electric field distribution on the surface of the device more uniform, thereby increasing the off-state breakdown voltage of the device.

Further, the upper surface of the junction semiconductor layer 8 between the metal gate electrode 6 and the drain electrode 5 has a second dielectric passivation layer 13, and the drain electrode 5 faces the metal along the upper surface of the second dielectric passivation layer 13. The direction of the gate electrode 6 is extended to form a drain field plate electrode 12 .

The purpose of the above solution is to effectively reduce the electric field peak at the drain end through the introduction of the leakage field plate 12 and avoid premature breakdown of the leakage current.

Further, the gate structure is a planar insulating gate structure, and the lower surface of the insulating gate dielectric 7 is connected to the upper surface of the barrier layer 3 .

Further, the gate structure is a recessed insulated gate structure, and the bottom of the insulated gate dielectric 7 is located in the barrier layer 3 .

Further, the gate structure is a recessed insulated gate structure, and the lower surface of the insulating gate dielectric 7 is connected to the upper surface of the buffer layer 2 .

Further, it is characterized in that, the rectifying structure 9 is that the metal gate electrode 6 contacts the P-type doped region 81 to form a Schottky barrier contact.

Further, the upper surface of the connection between the P-type doped region 81 and the gate structure is doped with an N-type semiconductor to form a PN junction rectification, and the rectification structure 9 is an ohmic contact between the metal gate electrode 6 and the PN junction rectification.

Further, the isolation layer 11 is a physical isolation layer or an ion implantation isolation layer.

In the above scheme, the physical isolation layer refers to etching away the part between the junction semiconductor layer 8 and the drain electrode 5, so as to isolate the junction semiconductor layer 8 from the drain electrode 5; An N-type semiconductor is implanted between the semiconductor layer 8 and the drain electrode 5 to form a heavily doped N-type isolation layer.

Further, the material used for the insulating gate dielectric 7 is Al2O3 or other single-layer or multi-layer insulating dielectric materials; the material used for the junction semiconductor layer 8 is Si, SiC, GaN, AlN, AlGaN, InGaN, InAlN One or a combination of several; the buffer layer 2 and the barrier layer 3 are made of one or a combination of GaN, AlN, AlGaN, InGaN, InAlN; the material used for the substrate 1 is One or a combination of sapphire, silicon, SiC, AlN or GaN.

The beneficial effect of the present invention is that the electric field concentration effect at the drain end of the device gate is effectively improved, and at the same time, a new electric field peak is introduced at the contact part between the P-type doped region and the N-type doped region, so that the electric field distribution on the surface of the device is more accurate. uniform, thereby increasing the off-state breakdown voltage of the device.

Description of drawings

Figure 1 is a HEMT device structure with a field plate;

Fig. 2 is a polarized superjunction HEMT device structure electrically connected to the gate electrode;

3 is a HEMT device structure with a grooved insulating gate structure;

Fig. 4 is the HEMT device structure of embodiment 1;

Fig. 5 is the HEMT device structure of embodiment 2;

Fig. 6 is the HEMT device structure of embodiment 3;

Fig. 7 is the HEMT device structure of embodiment 4;

Fig. 8 is the HEMT device structure of embodiment 5;

Fig. 9 is the HEMT device structure of embodiment 6;

Fig. 10 is a comparison diagram of the reverse withstand voltage between the junction superheterojunction HEMT device structure proposed by the present invention and the traditional MOS-HEMT structure;

Fig. 11 is a comparison diagram of the electric field distribution between the junction superheterojunction HEMT device structure proposed by the present invention and the traditional MOS-HEMT structure during reverse withstand voltage.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

Example 1

As shown in FIG. 4 , this example includes a substrate 1, a buffer layer 2 disposed on the upper surface of the substrate 1, and a barrier layer 3 disposed on the upper surface of the buffer layer 2. The contact between the buffer layer 2 and the barrier layer 3 A first heterojunction with a two-dimensional electron gas channel (2DEG) is formed on the surface; the two ends of the upper surface of the barrier layer 3 have a source electrode 4 and a drain electrode 5 respectively, and the middle part of the upper surface of the barrier layer 3 has a gate structure; the upper surface of the barrier layer 3 between the source electrode 4 and the gate structure has a dielectric passivation layer 10, and the upper surface of the barrier layer 3 between the drain electrode 5 and the gate structure has a junction semiconductor layer 8; the contact surface between the junction semiconductor layer 8 and the barrier layer 3 forms a second heterojunction with two-dimensional hole gas (2DHG); it is characterized in that the junction semiconductor layer 8 is doped by P type region 81 and N-type doped region 82, the P-type doped region 81 is connected to the gate structure, the N-type doped region 82 and the drain electrode 5 have a partition capable of blocking two-dimensional hole gas layer 11; the gate structure is composed of an insulating gate dielectric 7 and a metal gate electrode 6, and the insulating gate dielectric 7 is respectively connected with the dielectric passivation layer 10, the barrier layer 3 and the P-type doped region 81, and its cross section The shape is a U-shaped structure, the metal gate electrode 6 is located in the insulating gate dielectric 7, the metal gate electrode 6 extends along the lateral direction of the device and covers the upper surface of the insulating gate dielectric 7; the metal gate electrode 6 also extends to A rectification structure 9 is formed between the upper surface of the P-type doped region 81 and the junction semiconductor layer 8; the rectification structure 9 is formed by contacting the metal gate electrode 6 with the P-type doped region 81 to form a Schottky barrier contact. Layer 11 is to block 2DHG by ion implantation.

The working principle of this example is as follows: First, the rectification structure and the P-type region of the junction semiconductor layer form a Schottky barrier to avoid the leakage current of the gate-2DHG-2DEG when a positive voltage is applied to the gate. At the same time, the isolation structure adopts ion The injection method blocks 2DHG; secondly, the junction semiconductor layer/barrier layer/buffer layer forms a polarized superjunction structure. In the blocking state, 2DHG assists in depleting the drift region, which effectively improves the electric field concentration effect at the drain end of the device gate. The electric field distribution on the surface of the device is made more uniform, and the withstand voltage is greatly improved.

Example 2

As shown in FIG. 5 , the difference between this example and Example 1 is that the rectification structure 9 of the device in this example is PN junction rectification, and other structures are the same as those of Example 1. The rectifier structure and the P-type region of the junction semiconductor layer form a PN junction, which prevents the leakage current of the gate-2DHG-2DEG from being caused by a positive voltage on the gate, resulting in premature breakdown of the device.

Example 3

As shown in Figure 6, the difference between this example and Example 1 is that the isolation layer 11 uses grooves to block the 2DHG, which is used to avoid the leakage current of the gate-2DHG-2DEG caused by the positive voltage on the gate. Early breakdown.

Example 4

As shown in Figure 7, the difference between this example and Example 1 is that the device of this example forms a dielectric passivation layer 10 above the junction semiconductor layer 8, and the dielectric passivation layer 10 between the gate and drain is on the drain side. A drain field plate 12 is formed above, and is electrically connected to the drain electrode 5 . The use of a dielectric passivation layer can improve the surface state of the device and suppress the current collapse. The material of the dielectric passivation layer can be the same material as the gate dielectric and formed at the same time, or common dielectric materials such as SiNx, Al2O3, AlN, etc. can be used. At the same time, the introduction of the leakage field plate 12 can effectively reduce the electric field peak at the drain end, and avoid premature breakdown of the leakage.

Example 5

As shown in FIG. 8 , the difference between this example and Example 1 is that the gate structure of the device in this example is a grooved insulated gate structure. The recessed insulating gate structure etches all the barrier layer under the gate to realize an enhanced device. Recessed gate etching can effectively deplete the 2DEG concentration under the gate and greatly increase the threshold voltage, but all etching of the barrier layer under the gate will cause damage to the interface of the buffer layer and affect the electrical performance of the device.

Example 6

As shown in Figure 9, the difference between this example and Example 5 is that the recessed insulated gate structure partially etches the lower barrier layer to realize an enhanced device. Compared with Example 5, the lower barrier layer part Etching can avoid the interface damage caused by etching to a certain extent.

The HEMT device of the present invention can adopt one or more combination in sapphire, silicon, silicon carbide (SiC), aluminum nitride (AlN) or gallium nitride (GaN) as the material of substrate layer 1; Can adopt GaN One or more of AlN, AlGaN is used as the material of the buffer layer 2; one or more of GaN, AlN, AlGaN, InGaN, and InAlN can be used as the material of the barrier layer 3; One or a combination of Si, SiC, GaN, AlN, AlGaN, InGaN, InAlN is used as the material of the junction semiconductor layer 8; for the passivation layer 10, the material commonly used in the industry is SiNx, and Al2O3 can also be used , AlN and other dielectric materials, the insulating gate dielectric 7 can use the same material as the passivation layer; the source electrode 4 and the drain electrode 5 generally use metal alloys, commonly used are Ti/Al/Ni/Au or Mo/Al/Mo/Au etc.; the gate electrode 6 generally adopts a metal alloy with a relatively large work function, such as Ni/Au or Ti/Au.

Fig. 10 and Fig. 11 are respectively the comparison diagrams of the reverse withstand voltage and the comparison diagram of the electric field distribution during the reverse withstand voltage between the junction superheterojunction HEMT device structure proposed by the present invention and the traditional MOS-HEMT structure. Using SentaurusTCAD software for simulation, the two structures have a device lateral dimension of 10.5 μm, a gate length of 1.5 μm, and a gate-to-drain distance of 5 μm. The 548V is increased to 880V, and the breakdown voltage is increased by 60%.

Claims (10)

1. A HEMT device with a junction semiconductor layer, comprising a substrate (1), a buffer layer (2) arranged on the substrate (1) upper surface and a barrier layer (2) arranged on the buffer layer (2) upper surface 3), the contact surface of the buffer layer (2) and the barrier layer (3) forms a first heterojunction with a two-dimensional electron gas channel; the two ends of the upper surface of the barrier layer (3) respectively have The source electrode (4) and the drain electrode (5), the middle part of the upper surface of the barrier layer (3) has a gate structure; the upper surface of the barrier layer (3) between the source electrode (4) and the gate structure has a dielectric Passivation layer (10), the upper surface of the barrier layer (3) between the drain electrode (5) and the gate structure has a junction semiconductor layer (8); the junction semiconductor layer (8) and the barrier The contact surface of the layer (3) forms a second heterojunction with two-dimensional hole gas; it is characterized in that the junction semiconductor layer (8) is composed of a P-type doped region (81) and an N-type doped region ( 82), the P-type doped region (81) is connected to the gate structure, and there is a blocking layer capable of blocking two-dimensional hole gas between the N-type doped region (82) and the drain electrode (5). (11); the grid structure is made of an insulating gate dielectric (7) and a metal gate electrode (6), and the insulating gate dielectric (7) is respectively connected with a dielectric passivation layer (10), a barrier layer (3) and a metal gate electrode (6). The P-type doped region (81) is connected, and its cross-sectional shape is a U-shaped structure, the metal gate electrode (6) is located in the insulating gate dielectric (7), the metal gate electrode (6) extends along the lateral direction of the device and Covering the upper surface of the insulating gate dielectric (7); the metal gate electrode (6) also extends to the upper surface of the P-type doped region (81) and forms a rectifying structure (9) with the junction semiconductor layer (8) . 2. A kind of HEMT device with junction type semiconductor layer according to claim 1, is characterized in that, the upper part of junction type semiconductor layer (8) between described metal gate electrode (6) and drain electrode (5) The surface has a second dielectric passivation layer (13), and the drain electrode (5) extends along the upper surface of the second dielectric passivation layer (13) toward the direction of the metal gate electrode (6), forming a drain field plate electrode (12) . 3. A kind of HEMT device with junction semiconductor layer according to claim 1, is characterized in that, described gate structure is planar insulating gate structure, and the lower surface of described insulating gate dielectric (7) and barrier layer (3) The upper surface connection. 4. A kind of HEMT device with junction semiconductor layer according to claim 1, it is characterized in that, described gate structure is grooved insulating gate structure, and the bottom of described insulating gate dielectric (7) is positioned at barrier layer (3). 5. A kind of HEMT device with junction semiconductor layer according to claim 1, is characterized in that, described gate structure is grooved insulating gate structure, and the lower surface of described insulating gate dielectric (7) and buffer layer (2) is connected to the upper surface. 6. A kind of HEMT device with junction semiconductor layer according to any one of claims 1 to 5, characterized in that, the rectification structure (9) is a metal gate electrode (6) and a P-type doped region ( 81) The contact forms a Schottky barrier contact. 7. A kind of HEMT device with junction semiconductor layer according to any one of claims 1 to 5, characterized in that the upper surface of the P-type doped region (81) connected to the gate structure is doped with The N-type semiconductor forms a PN junction for rectification, and the rectification structure (9) is that the metal gate electrode (6) forms an ohmic contact with the PN junction for rectification. 8. A HEMT device with a junction semiconductor layer according to claim 5, characterized in that, the isolation layer (11) is a physical isolation layer or an ion implantation isolation layer. 9. A HEMT device with a junction semiconductor layer according to claim 6, characterized in that the isolation layer (11) is a physical isolation layer or an ion implantation isolation layer. 10. A kind of HEMT device with junction semiconductor layer according to claim 8 or 9, is characterized in that, the material that described insulating gate dielectric (7) adopts is Al2O3; Described junction semiconductor layer (8) adopts The material is one or a combination of Si, SiC, GaN, AlN, AlGaN, InGaN, InAlN; the buffer layer (2) and the barrier layer (3) are made of GaN, AlN, AlGaN, InGaN , one or a combination of InAlN; the material used for the substrate (1) is one or a combination of sapphire, silicon, SiC, AlN or GaN.