CN105097534A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- CN105097534A CN105097534A CN201410198540.5A CN201410198540A CN105097534A CN 105097534 A CN105097534 A CN 105097534A CN 201410198540 A CN201410198540 A CN 201410198540A CN 105097534 A CN105097534 A CN 105097534A
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Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to a method of manufacturing a semiconductor device. The invention brings forward a novel method of removing a virtual gate oxide layer in a Core area. A sacrificial layer is adopted to cover an IO device area to remove a virtual gate oxide layer in a Core area, so a semiconductor device is prevented from being damaged and then is improved in performance. The manufacturing method is suitable for manufacturing planar semiconductor devices and FinFET devices.
Description
Technical field
The present invention relates to semiconductor device technology, particularly, the present invention relates to a kind of method making semiconductor device.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.At present, because in pursuit high device density, high-performance and low cost, semi-conductor industry has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 20nm or be following, the preparation of semiconductor device is subject to the restriction of various physics limit.
The main devices of integrated circuit (IC) especially in very lagre scale integrated circuit (VLSIC) is mos field effect transistor (MOS), along with semiconductor integrated circuit industrial technology maturation day by day,
Developing rapidly of ultra-large integrated circuit, has the component density that more high-performance and more powerful integrated circuit requirement are larger, and all parts, between element or the size of each element self, size and space also need to reduce further.For having the CMOS of more advanced technology node, rear high K/ metal gates (high-kandmetallast) technology has been widely used in cmos device, to avoid high-temperature processing technology to the damage of device.Meanwhile, need the equivalent oxide thickness (EOT) reducing cmos device gate dielectric, such as, be contracted to about 1.1nm.At rear high K (high-klast, HKlastprocess) in technology, in order to arrive the thickness of less EOT, chemical oxide boundary layer (chemicaloxideIL) is adopted to replace hot gate oxide layers (thermalgateoxide).
In current " after rear high K/ metal gates (high-K & gatelast) " technology, concrete processing step is, at removal dummy gate with after forming metal valley, in metal valley, fill sacrifice layer and perform flatening process, then, adopt photo etched mask to cover IO region and expose core region, remove the sacrifice layer in core region and dummy gate oxide layer.
Using " post tensioned unbonded prestressed concrete (high-K & gatelast) " technique to be formed in the method for metal gates, adopting in the process of the sacrifice layer in dry etching removal core region and dummy gate oxide layer and will damage semiconductor device and the performance reducing device in core region.If only make not use sacrifice layer with photoresist, because photoresist has poor filling capacity and removal capacity, photoresist is by the metal valley that remains in core region and IO region.
Therefore, a kind of manufacture method of new semiconductor device is needed, to solve the problems of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to effectively solve the problem, the present invention proposes a kind of method making semiconductor device, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises first area and second area; Form dummy gate oxide layer on the semiconductor substrate; Described dummy gate oxide layer is formed dummy gate material layer; Etch described dummy gate material layer and described dummy gate oxide layer, to form the first dummy gate in described first area, in described second area, form the second dummy gate; Form interlayer dielectric layer on the semiconductor substrate; Perform flatening process, to expose described first dummy gate and described second dummy gate; Etching removes the described dummy gate material layer in described second area, to expose described dummy gate oxide layer; Form the first includes high-k dielectric and sacrifice layer successively on the semiconductor substrate; Return etching and remove the described sacrifice layer be positioned on described interlayer dielectric layer; Remove in described first includes high-k dielectric in described first area and described second area the first includes high-k dielectric be positioned on described interlayer dielectric layer; Remove the described dummy gate material layer in described first area, to expose described dummy gate oxide layer; Remove the described sacrifice layer in described second area, to expose described first includes high-k dielectric; The described dummy gate oxide layer removed in described first area exposes described Semiconductor substrate, to form groove; Form the second includes high-k dielectric on the semiconductor substrate.
Exemplarily, the step of boundary layer is formed after being also included in the described groove of formation in the bottom of described groove.
Exemplarily, the material of described boundary layer is oxide, and the thickness range of described boundary layer is 5 dust to 10 dusts.
Exemplarily, the thickness of described dummy gate oxide layer is 10 dust to 100 dusts.
Exemplarily, the material of described dummy gate material layer is the silicon of amorphous silicon, polysilicon or doping, and the thickness of described dummy gate material layer is 500 dust to 1500 dusts.
Exemplarily, the material of described sacrifice layer is DUO or amorphous carbon.
Exemplarily, described first area is nucleus, and described second area is input and output region.
Exemplarily, the thickness of described first includes high-k dielectric is 10 dust to 50 dusts, and the thickness of described second includes high-k dielectric is 10 dust to 50 dusts.
Exemplarily, wet etching or the described sacrifice layer removed without plasma dry etch in described second area is adopted.
Exemplarily, wet etching or the described dummy gate oxide layer removed without plasma dry etch in described first area is adopted.
In sum, the present invention proposes the method for dummy gate oxide layer in a kind of removal Core region newly, employing sacrifice layer covering I/O device region removes the dummy gate oxide layer in Core region, to avoid problem semiconductor device being produced to damage, finally improve the performance of semiconductor device.Manufacture method of the present invention is applicable to the manufacture craft of planar semiconductor device and the manufacture craft of FinFET.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1G is a kind of cross sectional representation of the semiconductor device structure using the method for " post tensioned unbonded prestressed concrete (high-K & gatelast) " to make;
The cross-sectional view of the device that the correlation step that Fig. 2 A-2I is the semiconductor device using the method for " post tensioned unbonded prestressed concrete (high-K & gatelast) " to make according to one embodiment of the present invention obtains;
Fig. 3 is the process chart of the semiconductor device using the method making of " post tensioned unbonded prestressed concrete (high-K & gatelast) " according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that the preparation method of semiconductor device of the present invention to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
As shown in Figure 1A-1G, for the cross sectional representation of the semiconductor device structure that one uses the method for " post tensioned unbonded prestressed concrete (high-K & gatelast) " to make, as shown in Figure 1A, Semiconductor substrate 100 comprises corearea (nucleus) and IOarea (input and output region), forms the first dummy gate oxide layer 101 on a semiconductor substrate 100.
As shown in Figure 1B, described first dummy gate oxide layer 101 is formed the photoresist layer 102 of patterning, the photoresist layer 102 of described patterning covers described IO region and exposes described core region, expose Semiconductor substrate according to the first dummy gate oxide layer 101 that the photoresist layer 102 of patterning is removed in core region, then remove the photoresist layer 102 of described patterning.
As shown in Figure 1 C, the described Semiconductor substrate in described core region is formed the second dummy gate oxide layer 103.
As shown in figure ip, described Semiconductor substrate 100 forms dummy gate material layer 104, etch described dummy gate material layer 104, described first dummy gate oxide layer 101 and the second dummy gate oxide layer 103, to form dummy gate 105A in core region on a semiconductor substrate 100 and IO region, 105B, dummy gate 105A comprises the first dummy gate oxide layer 101 and dummy gate material layer 104, dummy gate 105B comprises the second dummy gate oxide layer 103 and dummy gate material layer 104, at dummy gate 105A, the both sides of 105B form side wall, then, form contact hole etching stop-layer 106 and interlayer dielectric layer 107 on a semiconductor substrate, perform cmp (CMP) and make contact hole etching stop-layer 106, interlayer dielectric layer 107 and dummy gate 105A, the top of 105B flushes.
As referring to figure 1e, the dummy gate material layer 104 in removal dummy gate 105A, 105B, to expose the first dummy gate oxide layer 101, second dummy gate oxide layer 103 and side wall, forms groove 108A, 108B.
As shown in fig. 1f, on a semiconductor substrate 100 formed sacrifice layer 109, sacrifice layer 109 filling groove 108A, 108B and cover side wall, contact hole etching stop-layer 106 and interlayer dielectric layer 107.Sacrifice layer 109 is formed the photoresist layer 110 of patterning, and the photoresist layer 110 of patterning covers IO region and exposes Core region.
As shown in Figure 1 G, dry etching is then adopted to remove sacrifice layer in core region to expose the second dummy gate oxide layer 103.
When the sacrifice layer adopting dry etching to remove in core region, by the device in damage core region, as shown in Figure 1 G, therefore, the method for this making semiconductor device can not solve the problems of the prior art.
Below in conjunction with Fig. 2 A-2I, the preparation method of semiconductor device of the present invention is described in detail.First with reference to Fig. 2 A, provide Semiconductor substrate 200, described Semiconductor substrate 200 has active area;
Particularly, can be at least one in following mentioned material in Semiconductor substrate 200 described in an embodiment of the present invention: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferred silicon-on-insulator (SOI) in an embodiment of the present invention, described silicon-on-insulator (SOI) comprises and is followed successively by support substrates, oxide insulating layer and semiconductor material layer from the bottom up, but is not limited to above-mentioned example.
Can be formed with doped region and/or isolation structure in described substrate, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
N trap or P well structure is formed in described substrate, described substrate selects P type substrate in one embodiment of this invention, particularly, the P type substrate that those skilled in the art select this area conventional, then in described P type substrate, form N trap, in an embodiment of the present invention, first in described P type substrate, form N trap window, in described N trap window, carry out ion implantation, then perform annealing steps and advance to form N trap.
In a specific embodiment of the present invention, Semiconductor substrate 200 comprises core region and IO region.
Then, the core region and IO region of described Semiconductor substrate 200 are formed the dummy gate oxide layer 201 of I/O device.The thickness of described dummy gate oxide layer 201 is 10 dust to 100 dusts.Thermal oxidation technology can be adopted to form dummy gate oxide layer 201.
As shown in Figure 2 B, described dummy gate oxide layer 201 deposits dummy gate material layer, described grid material (that is, has from every cubic centimetre about 1 × 10 including but not limited to the polysilicon of silicon, amorphous silicon, polysilicon, doping and polysilicon-Ge alloy material
18to about 1 × 10
22the doping content of individual foreign atom) and polycide (polycide) material (polysilicon/metal silicide laminated material of doping).
Similarly, any one formation previous materials of several methods can also be adopted.Limiting examples comprises chemical vapor deposition method, Technology for Heating Processing or physical gas-phase deposition.Usually, described grid material comprise have thickness from about 500 dusts the polycrystalline silicon material to the doping of about 1500 dusts.
The formation method of described polysilicon gate material can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH4), and the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350mTorr, as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Then described dummy gate material layer and described dummy gate oxide layer 201 are etched, to obtain dummy gate 202A, 202B, particularly, in an embodiment of the present invention, first on described dummy gate material layer, form the photoresist layer of patterning, described photoresist layer defines the shape of described dummy gate and the size of critical size, with described photoresist layer for dummy gate material layer described in mask etch and dummy gate oxide layer 201, form dummy gate 202A, 202B, dry etching can be selected, etching dummy gate material layer is closed in wet etching or dry-wet mixing, wherein said etching technics stops the described second grid oxide layer below dummy gate material layer, to ensure not having dummy gate oxide layer described in loss.Then remove described photoresist layer, the minimizing technology of described photoresist layer can select oxidative ashing method, can also select additive method conventional in this area, not repeat them here.
At described dummy gate 202A, 202B upper formation skew sidewall 203, particularly, conformal deposited (conformaldeposition) offsets the material layer of sidewall over the substrate, with at described dummy gate 202A, the cover layer that 202B upper formation thickness is identical or roughly the same, substrate and dummy gate 202A is removed in etching, after the material layer of the skew sidewall on 202B horizontal plane, form skew sidewall 203, described skew sidewall 203 thickness that conformal deposited is formed is homogeneous, described polysilicon sidewall can clearly be determined the critical size of described first skew sidewall, the critical size of described metal gates is clearly determined in step below.
As preferably, in an embodiment of the present invention, in order to make the thickness of the formation of acquisition skew sidewall 203 more homogeneous, clearly determine the critical size of described metal gates, described skew sidewall 203 material layer selects the method deposition of ald (ALD) to be formed, when selecting the material layer of method deposition first skew sidewall of ald (ALD), the thickness that the sidewall of horizontal plane and dummy gate 202A, 202B is formed is all the same, more homogeneous, ensure that the performance of described semiconductor device; Described in an embodiment of the present invention, the first skew sidewall 203 selects oxide, preferential oxidation silicon, and described oxide is formed by the method for ald (ALD).
Perform the step that LDD injects, the method for described formation LDD can be ion implantation technology or diffusion technology.The ionic type that described LDD injects according to the electrical decision of the semiconductor device that will be formed,
Namely the device formed is nmos device, then the foreign ion mixed in LDD injection technology is one in phosphorus, arsenic, antimony, bismuth or combination; If the device formed is PMOS device, then the foreign ion injected is boron.According to the concentration of required foreign ion, ion implantation technology can a step or multistep complete.
Then at described grid both sides source-drain area growth stress layer, in CMOS transistor, usually the stressor layers with tension stress is formed on the nmos transistors, form the stressor layers with compression on the pmos transistors, the performance of cmos device can be passed through by described action of pulling stress in NMOS, and action of compressive stress improves in PMOS.In nmos pass transistor, usually select SiC as tension stress layer in prior art, in PMOS transistor, usually select SiGe as compressive stress layer.
As preferably, when growing described SiC as tension stress layer, can epitaxial growth over the substrate, form lifting source and drain after ion implantation, when forming described SiGe layer, usually in described substrate, form groove, then in described groove, deposition forms SiGe layer.More preferably, in described substrate, " ∑ " connected in star is formed.
In one embodiment of this invention, source-drain area described in dry etching can be selected to form groove, can CF be selected in described dry etching
4, CHF
3, add N in addition
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is preferably 5-60s, is more preferably 5-30s.Then epitaxial growth SiGe layer in described groove; Described extension can select the one in reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, molecular beam epitaxy.
Then on described dummy gate 202A, 202B, form clearance wall 204, described grid gap wall 204 can be SiO
2, in SiN, SiOCN a kind of or their combinations form.As an optimal enforcement mode of the present embodiment, described grid gap wall 204 is silica, silicon nitride forms jointly, concrete technology is: form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer on a semiconductor substrate, then adopts engraving method to form grid gap wall.The thickness of described grid gap wall is 5-50nm.
Then ion implantation technology is performed, to form regions and source/drain in the Semiconductor substrate around grid.And then carry out rapid thermal annealing process, utilize the high temperature of 900 to 1050 DEG C to activate the doping in regions and source/drain, and repair the lattice structure of semiconductor substrate surface impaired in each ion implantation technology simultaneously.In addition, also visible product demand and functionally to consider, separately forms lightly doped drain (LDD) respectively between regions and source/drain and each grid.
Then stress memory effect (Stressmemorizationtechnique is performed; be called for short SMT); to introduce stress in described device preparation technology; particularly; after device source and drain is injected; deposition one deck silicon nitride film protective layer (caplayer); and then source and drain annealing is carried out; in source and drain annealing process; can produce the thermal stress between silicon nitride film protective layer, polysilicon gate and side wall and internal stress effect, described stress can by memory among polysilicon gate.Then, described silicon nitride film protective layer is removed in etching, but the stress of memory in polysilicon gate, among the raceway groove that still can be transmitted to semiconductor device.Described stress is useful to raising nmos device electron mobility.
Then, Deposit contact hole etching stopping layer (CESL) 205 in described Semiconductor substrate 200, described contact etch stop layer (CESL) 205 can comprise in SiCN, SiN, SiC, SiOF, SiON one or more, in one embodiment of this invention, preferably form layer of sin over the substrate, then on described SiN, continue deposition one deck SiC, to form described contact etch stop layer 205, wherein said contact etch stop layer 205 is not limited to above-mentioned one combination.
Interlevel dielectric deposition 206 (ILD) is in Semiconductor substrate and dummy gate 202A, 202B.Described interlayer dielectric layer 206 can be silicon oxide layer, comprise the material layer having doping or unadulterated silica utilizing thermal chemical vapor deposition (thermalCVD) manufacturing process or high-density plasma (HDP) manufacturing process to be formed, the silex glass (USG) of such as undoped, phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer also can be the tetraethoxysilane (BTEOS) of spin cloth of coating-type glass (spin-on-glass, SOG) of doped with boron or Doping Phosphorus, the tetraethoxysilane (PTEOS) of Doping Phosphorus or doped with boron.
After interlevel dielectric deposition 206, a planarisation step can also be comprised further, flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.Described planarisation step stops on described dummy gate 202A, 202B.
As illustrated in figs. 2 c and 2d, after performing planarisation step, remove the dummy gate material layer of the described dummy gate 202B in IO region to expose dummy gate oxide layer 201, particularly, select dry etching or wet etching or dry-wet mixing to close etching in the present invention and expose dummy gate oxide layer 201 and skew sidewall 203, to form groove 208 with the dummy gate material layer removed in described dummy gate structure 202B;
Exemplarily, described Semiconductor substrate 200 forms the photoresist layer 207 of patterning, the photoresist layer of described patterning covers Core region and exposes IO region, removes the dummy gate material layer in IO region according to the photoresist layer etching of patterning.Then, the photoresist layer 207 of described patterning is removed.
When selecting dry etching, HBr can be selected as main etch gas; Also comprise the O as etching make-up gas
2or Ar, it can improve the quality of etching.Or select wet etching, when selecting wet etching, select in KOH and tetramethyl aqua ammonia (TMAH) one or more, KOH is selected to etch in the present invention, preferred mass mark is that the KOH of 5-50% etches in the present invention, the strict temperature controlling this etching process simultaneously, preferably etch temperature is 20-60 DEG C in this step.
As shown in Figure 2 E, described Semiconductor substrate 200 forms includes high-k dielectric 209, described includes high-k dielectric covers bottom and the side of groove 207 in core region and IO region and IO region.The material of high-k dielectrics can be chosen as but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO
3(BST), Al
2o
3, Si
3n
4, nitrogen oxide or other be applicable to material.The technique that CVD, ALD or PVD etc. can be adopted to be applicable to forms includes high-k dielectric.The thickness range of includes high-k dielectric is 10 dust to 50 dusts.
As shown in Figure 2 F, described includes high-k dielectric 209 forms sacrifice layer 210, the groove 207 that described sacrifice layer 210 covers core region and IO region and fills in IO region.
Exemplarily, described sacrifice layer 210 has the ability of excellent filling groove and the performance being easy to remove from groove.The material of described sacrifice layer can be but be not limited to organic material, and described organic material comprises deep UV and absorbs oxidation (DUO, DeepUltraVioletLightAbsorbingOxide) material, amorphous carbon or other materials be applicable to.
As shown in Figure 2 G, return etching and remove the sacrifice layer 210 be positioned on described interlayer dielectric layer 206, to expose described includes high-k dielectric 209, the sacrifice layer 210 and includes high-k dielectric 209 top that are arranged in described IO region flush.In one example, dry etch process is adopted to perform described time etch step, described dry etching has high selectivity between sacrifice layer and other layers, and other layer described comprises includes high-k dielectric, skew sidewall, clearance wall, dummy gate material layer and interlayer dielectric layer etc.
As illustrated in figure 2h, remove in described includes high-k dielectric 209 in core region and described IO region the includes high-k dielectric 209 be positioned on described interlayer dielectric layer 206, to expose Semiconductor substrate 200, in IO region, the bottom of groove 207 and side are formed with includes high-k dielectric 209, expose the dummy gate 202A in core region.Then, remove the dummy gate material layer in core region, to expose dummy gate oxide layer in core region 201 and skew sidewall 203, form groove 211, the includes high-k dielectric be positioned on described interlayer dielectric layer 206 can be adopted in the includes high-k dielectric in dry etching removal core region and IO region, dry etching or wet etching or dry-wet mixing is adopted to close the dummy gate material layer etching and remove in core region again, then, sacrifice layer 210 in removal IO region is to expose described includes high-k dielectric 209, form groove 212, can adopt without the sacrifice layer 210 in plasma dry etch or wet etching or dry-wet mixing conjunction etching removal IO region.
In the present invention one specific embodiment, adopt the dummy gate material layer in dry etching removal core region, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.After the dummy gate material layer adopting dry etching to remove in core region, soft wet-cleaned (softWET) step can be performed to remove the residue in groove.Such as, or can adopt the dummy gate material layer in wet etching removal core region, wet etch method can adopt hydrofluoric acid solution, buffer oxide etch agent or hydrofluoric acid cushioning liquid.Or, dry-wet mixing can be adopted to close etching.
As shown in figure 2i, the dummy gate oxide layer 201 that etching is removed in Core region exposes described Semiconductor substrate 200 to form groove 213 in Core region.Described etching technics can adopt without plasma dry etch, wet etching or close without plasma soma-wet mixing the technique that etching etc. is applicable to.Wherein, when adopting wet etching to perform described etching technics, described wet etching needs to provide enough over etching to guarantee not having oxidized residual thing bottom the groove 213 formed.When adopting dry etching to perform described etching technics, described in be dry-etched in reaction chamber etching under the condition not having plasma and remove the dummy gate oxide layer 201 in Core region, to avoid the damage to silicon semiconductor substrate raceway groove.
Then, it can be thermal oxide layer, oxynitride layer, chemical oxide layer or other thin layers be applicable to that the bottom deposit of the groove 213 in Core region forms boundary layer (IL) 214, IL layer.The technique that CVD, ALD or PVD etc. can be adopted to be applicable to forms boundary layer.The thickness range of boundary layer is 5 dust to 10 dusts.Deposition forms includes high-k dielectric 215 on semiconductor substrate 200, and includes high-k dielectric 215 covers interlayer dielectric layer 206, skew sidewall 203, clearance wall 204, etching stop layer, and groove 213, the bottom of groove 212 and side.The material of high-k dielectrics can be chosen as but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3 (BST), Al2O3, Si3N4, nitrogen oxide or other materials be applicable to.The technique that CVD, ALD or PVD etc. can be adopted to be applicable to forms includes high-k dielectric.The thickness range of includes high-k dielectric is 10 dust to 50 dusts.
With reference to Fig. 3, illustrated therein is the process chart of an embodiment of the present invention, comprise the following steps particularly:
Step 301 provides Semiconductor substrate, and described Semiconductor substrate comprises core region and IO region, and described Semiconductor substrate has trap and STI, forms dummy gate oxide layer on the semiconductor substrate;
Step 302 forms dummy gate material layer in dummy gate oxide layer, etch described dummy gate material layer and dummy gate oxide layer to form dummy gate respectively in core region and IO region, then skew sidewall and clearance wall is formed in the both sides of described dummy gate, form interlayer dielectric layer on the semiconductor substrate, perform flatening process;
Step 303 forms the photoresist layer of patterning on the semiconductor substrate, and the photoresist layer of described patterning exposes IO region overlay core region;
Step 304 removes the dummy gate material layer in IO region according to the photoresist layer of described patterning, removes the photoresist layer of described patterning;
Step 305 forms the first includes high-k dielectric on the semiconductor substrate;
Step 306 forms sacrifice layer in described first includes high-k dielectric;
Step 307 time etches described sacrifice layer to expose described first includes high-k dielectric;
Step 308 removes in the first includes high-k dielectric in core region, IO region the dummy gate material layer being arranged in the first includes high-k dielectric on interlayer dielectric layer and core region, removes the sacrifice layer in IO region;
Step 309 dummy gate oxide layer removed in core region is exposed Semiconductor substrate and is formed groove, forms boundary layer, then, form the second includes high-k dielectric on the semiconductor substrate in the bottom of described groove.
In sum, the present invention proposes the method for dummy gate oxide layer in a kind of removal Core region newly, employing sacrifice layer covering I/O device region removes the dummy gate oxide layer in Core region, to avoid problem semiconductor device being produced to damage, finally improve the performance of semiconductor device.Manufacture method of the present invention is applicable to the manufacture craft of planar semiconductor device and the manufacture craft of FinFET.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. make a method for semiconductor device, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises first area and second area;
Form dummy gate oxide layer on the semiconductor substrate;
Described dummy gate oxide layer is formed dummy gate material layer;
Etch described dummy gate material layer and described dummy gate oxide layer, to form the first dummy gate in described first area, in described second area, form the second dummy gate;
Form interlayer dielectric layer on the semiconductor substrate;
Perform flatening process, to expose described first dummy gate and described second dummy gate;
Etching removes the described dummy gate material layer in described second area, to expose described dummy gate oxide layer;
Form the first includes high-k dielectric and sacrifice layer successively on the semiconductor substrate;
Return etching and remove the described sacrifice layer be positioned on described interlayer dielectric layer;
Remove in described first includes high-k dielectric in described first area and described second area the first includes high-k dielectric be positioned on described interlayer dielectric layer;
Remove the described dummy gate material layer in described first area, to expose described dummy gate oxide layer;
Remove the described sacrifice layer in described second area, to expose described first includes high-k dielectric;
The described dummy gate oxide layer removed in described first area exposes described Semiconductor substrate, to form groove;
Form the second includes high-k dielectric on the semiconductor substrate.
2. method according to claim 1, is characterized in that, is also included in the step forming boundary layer after forming described groove in the bottom of described groove.
3. method according to claim 2, is characterized in that, the material of described boundary layer is oxide, and the thickness range of described boundary layer is 5 dust to 10 dusts.
4. method according to claim 1, is characterized in that, the thickness of described dummy gate oxide layer is 10 dust to 100 dusts.
5. method according to claim 1, is characterized in that, the material of described dummy gate material layer is the silicon of amorphous silicon, polysilicon or doping, and the thickness of described dummy gate material layer is 500 dust to 1500 dusts.
6. method according to claim 1, is characterized in that, the material of described sacrifice layer is DUO or amorphous carbon.
7. method according to claim 1, is characterized in that, described first area is nucleus, and described second area is input and output region.
8. method according to claim 1, is characterized in that, the thickness of described first includes high-k dielectric is 10 dust to 50 dusts, and the thickness of described second includes high-k dielectric is 10 dust to 50 dusts.
9. method according to claim 1, is characterized in that, the described sacrifice layer adopting wet etching or remove without plasma dry etch in described second area.
10. method according to claim 1, is characterized in that, the described dummy gate oxide layer adopting wet etching or remove without plasma dry etch in described first area.
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| CN107887335A (en) * | 2017-11-14 | 2018-04-06 | 上海华力微电子有限公司 | A kind of metal gates preparation method |
| CN107978562A (en) * | 2016-10-24 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| WO2022061737A1 (en) * | 2020-09-25 | 2022-03-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming same |
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| US20080173947A1 (en) * | 2007-01-23 | 2008-07-24 | Yong-Tian Hou | Hybrid process for forming metal gates |
| CN103094211A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semi-conductor device |
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| US20010027005A1 (en) * | 2000-03-29 | 2001-10-04 | Masaru Moriwaki | Semiconductor device and method for fabricating the device |
| CN1773707A (en) * | 2004-01-06 | 2006-05-17 | 台湾积体电路制造股份有限公司 | Integrated circuit and its manufacturing method |
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| WO2022061737A1 (en) * | 2020-09-25 | 2022-03-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming same |
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