CN105068961A - Ethernet interface management circuit - Google Patents
Ethernet interface management circuit Download PDFInfo
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- CN105068961A CN105068961A CN201510578628.4A CN201510578628A CN105068961A CN 105068961 A CN105068961 A CN 105068961A CN 201510578628 A CN201510578628 A CN 201510578628A CN 105068961 A CN105068961 A CN 105068961A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention provides an Ethernet interface management circuit. According to a transferring module, a first power supply port and a processor are electrically connected with a first power source, and a second power supply port and an Ethernet interface module are electrically connected with a second power source. The transferring module is used for controlling the data transmission direction between the processor and the Ethernet interface module according to control signals. The processor and the Ethernet interface module which are located in different voltage domains can select the corresponding power sources according to the self needs. Circuit connection is flexible, the problem that the signal level margin is insufficient due to direct connection of the processor and the Ethernet interface module in the prior art is further solved, and the quality of communication signals is guaranteed.
Description
Technical field
The present invention relates to network connection management field, particularly relate to a kind of Ethernet interface management circuit.
Background technology
10G ethernet PHY (the PhysicalLayer of current main flow, Physical layer) MIIM (MediumIndependentInterfaceManagement of chip, Media Independent Interface management bus) optional 1.2V and the 2.5V level of interface support, and the MIIM interface of general CPU only supports 3.3V level, the MIIM interface of this MIIM interface and 10GPHY chip of just causing general CPU is in different power domain.Existing implementation is powered by the power pin 2.5V of the MIIM interface of 10GPHY chip, and namely the MIIM interface level of PHY chip is that the MIIM interface of 2.5V, CPU and the MIIM interface direct of 10GPHY chip connect in succession.The MIIM interface power of existing technical disadvantages: one: 10GPHY is that 1.2V power supply and 2.5V power supply are optional, and in existing technology, the MIIM interface power of 10GPHY chip only supports 2.5V, does not support 1.2V, limits the design of the flexible more options of PHY power supply.Its two: 3.3VLVTTL and the LVTTL level standard of 2.5V be:
3.3VLVTTL：Vcc：3.3V；VOH>＝2.4V；VOL<＝0.4V；VIH>＝2V；VIL<＝0.8V。
2.5VLVTTL：Vcc：2.5V；VOH>＝2.0V；VOL<＝0.2V；VIH>＝1.7V；VIL<＝0.7V。
Wherein, Vcc represents voltage, and VOH represents output high level voltage, and VOL represents output low level voltage, and VIH represents putting high level voltage, and VIL represents input low level voltage.Namely when PHY chip sends high level signal to CPU, the high signal that PHY chip sends is VOH>=2V, and the criterion that CPU receives high level is VIH>=2V, and two indices can coordinate, but without allowance.If the transmission range between CPU to PHY is long, or a CPU manages multiple PHY, when line load is heavier, the attenuation and distortion of signal will be caused, when making the VOH sent from signal PHY chip arrive CPU, due to the decay of signal, 2V can not be reached, namely the allowance of level is inadequate, easily produces error code.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of Ethernet interface management circuit, inconsistent and cause the inflexible problem of PHY chip Power Management Design for solving the power supply of CPU and the power supply of PHY chip in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of Ethernet interface management circuit, comprising: processor; Ethernet interface module, is communicated with described processor by bus; Transit module, be electrically connected with described processor and described ethernet interface module, comprise control port, the first power supply port and the second power supply port, described control port receives a control signal, described first power supply port is electrically connected one first power supply with described processor, described second power supply port is electrically connected a second source with described ethernet interface module, described transit module in order to according to described control signal, the data transfer direction between control processor and described ethernet interface module.
Optionally, described Ethernet interface management circuit also comprises: CPLD module, is electrically connected with described transit module, provides described control signal for the described control port to described transit module.
Optionally, described CPLD module is connected with described bus, to produce described control signal according to the parsing to the communication protocol of the bus between described processor and described ethernet interface module.
Optionally, the analysis result of described CPLD module to the communication protocol of described bus comprises lead code, frame start mark, operational code, ethernet interface module internal register addresses, State Transferring territory, read/write status zone bit.
Optionally, it is from described processor to described ethernet interface module that described control signal is defaulted as controlling described data transfer direction, and when judging described read/write status zone bit as reading, make described transit module according to described control signal, make described data transfer direction be from described ethernet interface module to described processor.
Optionally, described processor also in order to produce a clock signal, and transmits described clock signal by described transit module to described ethernet interface module.
Optionally, the transmission direction that described transit module controls described clock signal remains from described processor to described ethernet interface module.
Optionally, described transit module is SN74AVC2T245 chip.
Optionally, communicated by Media Independent Interface bus between described processor with described ethernet interface module.
Optionally, the first power supply is 3.3V power supply, and described second source is 1.2V or 2.5V power supply.
As mentioned above, Ethernet interface management circuit of the present invention, transit module is made to be electrically connected one first power supply by described first power supply port with described processor, and be electrically connected a second source by described second power supply port with described ethernet interface module, described transit module in order to according to described control signal, the data transfer direction between control processor and described ethernet interface module.The processor and the described ethernet interface module that make to be in different voltage domain can according to self needs, select corresponding power supply, circuit connects more flexible, also solve processor and ethernet interface module in prior art and be directly connected the inadequate problem of the signal level margin that causes, ensure that the quality of signal of communication.
Accompanying drawing explanation
Fig. 1 is shown as a kind of Ethernet interface management circuit of the present invention module diagram in one embodiment.
Fig. 2 is shown as the sequential chart of DIR2 in the process that the circuit shown in Fig. 2 runs in one embodiment.
Fig. 3 is shown as a kind of Ethernet interface management circuit of the present invention circuit theory diagrams in one embodiment.
Element numbers explanation
1 Ethernet interface management circuit
11 processors
12 ethernet interface modules
13 transit modules
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.It should be noted that, when not conflicting, the feature in following examples and embodiment can combine mutually.
It should be noted that, the diagram provided in following examples only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in diagram but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
MIIM (ManagementInterface, Media Independent Interface) bus is the management interface of CPU to 10G ethernet PHY chip, MIIM has two signal wires, management data clock MDC (ManagementDataClock) and management data signal MDIO (ManagementDataInput/Output).CPU can configure the register information of PHY by MIIM bus, the operating rate of such as PHY, interface transmission medium are selected and the selection of mode of operation, and the content of registers that also can read PHY by MIIM bus obtains the work state information of PHY.
Optional 1.2V and the 2.5V level of MIIM interface support of the 10G ethernet PHY chip of current main flow, if the power pin 1.2V of PHY chip MIIM interface powers, MIIM bus just supports 1.2V level; If the power pin 2.5V of PHY chip MIIM interface powers, MIIM bus just supports 2.5V level.And the MIIM interface of general CPU only supports 3.3V level, the MIIM interface of this MIIM interface and 10GPHY chip of just causing general CPU is in different power domain.And in order to communicate normally with described CPU, need the power supply selecting ethernet PHY chip to be 2.5V, and due to the LVTTL level standard of 3.3VLVTTL and 2.5V be:
3.3VLVTTL：Vcc：3.3V；VOH>＝2.4V；VOL<＝0.4V；VIH>＝2V；VIL<＝0.8V。
2.5VLVTTL：Vcc：2.5V；VOH>＝2.0V；VOL<＝0.2V；VIH>＝1.7V；VIL<＝0.7V。
Wherein, Vcc represents voltage, and VOH represents output high level voltage, and VOL represents output low level voltage, and VIH represents putting high level voltage, and VIL represents input low level voltage.Namely when PHY chip sends high level signal to CPU, the high signal that PHY chip sends is VOH>=2V, and the criterion that CPU receives high level is VIH>=2V, and two indices can coordinate, but without allowance.If the transmission range between CPU to PHY is long, or a CPU manages multiple PHY, when line load is heavier, the attenuation and distortion of signal will be caused, when making the VOH sent from signal PHY chip arrive CPU, due to the decay of signal, 2V can not be reached, namely the allowance of level is inadequate, easily produces error code.
So present invention proposes this Ethernet interface management circuit making described CPU and PHY chip be in same power domain, refer to Fig. 1, be shown as a kind of Ethernet interface management circuit of the present invention module diagram in one embodiment.Described Ethernet interface management circuit 1 comprises processor 11, ethernet interface module 12 and transit module 13.
Described ethernet interface module 12 is communicated with described processor 11 by bus; In the present embodiment, described bus is MIIM bus.
Described transit module 13 is electrically connected with described processor 11 and described ethernet interface module 12, comprise control port, the first power supply port and the second power supply port, described control port receives a control signal, described first power supply port is electrically connected one first power supply with described processor, described second power supply port is electrically connected a second source with described ethernet interface module, described transit module 13 in order to according to described control signal, the data transfer direction between control processor 11 and described ethernet interface module 12.The processor 11 being in different voltage domain can be made according to self needs, can to select corresponding power supply with described ethernet interface module 12, and such as, described first power supply is 3.3V power supply, and described second source is 1.2V or 2.5V power supply.Namely when power supply 3.3V chosen by described processor 11, described ethernet interface module 12 can select 1.2V power supply or 2.5V power supply, circuit connects comparatively flexible, and ensures there are enough level margin between processor 11 and ethernet interface module 12, ensure that the quality of signal of communication.
In another specific embodiment, described Ethernet interface management circuit 1 also comprises: CPLD module (CPLD, ComplexProgrammableLogicDevice), be electrically connected with described transit module 13, for providing described control signal to the described control port of described transit module 13.And described CPLD can produce described control signal according to the parsing of the communication protocol of the bus between described processor 11 and described ethernet interface module 12.The analysis result of described CPLD to the communication protocol of described bus comprises lead code, frame start mark, operational code, ethernet interface module internal register addresses, State Transferring territory, read/write status zone bit.It is from described processor 11 to described ethernet interface module 12 that described control signal is defaulted as controlling described data transfer direction, and when judging described read/write status zone bit as reading, make described transit module 13 according to described control signal, make described data transfer direction be from described ethernet interface module 13 to described processor 12.
Concrete, in an embody rule, described ethernet interface module 12 for model be the PHY Ethernet chip of BCM8705, described transit module 13 for model be the dual power supply driving chip of SN74AVC2T245, described processor 11 is a CPU.Described CPLD in order to resolve the signal of communication of the MDIO pin of described processor, and produces described control signal according to analysis result.Concrete, refer to table 1, be shown as the sequential allocation list of MDIO, wherein " Pre " is lead code, comprises ' 1 ' data of 32-bit; " ST " be frame start mark, be 2-bit " 00 "; " OP " is 2-bit operational code, and " 10 " are read operations, and " 01 " is write operation; " PRTAD " is 5-bitPHY chip address, and PHY chip arranges PHY address by hardware pins; " REGAD " is 5-bitPHY chip internal register address; " TA " is State Transferring territory, altogether 2bit.If read operation, then 1bit sends high-impedance state by CPU, and 2bit sends " 0 " bit by PHY chip, and as being write operation, then CPU sends " TA " signal of 2-bit " 10 ".
| Operation | Pre | ST | OP | PRTAD | REGAD | TA | DATA | IDLE |
| READ | 1..1 | 00 | 10 | AAAAA | TTTTT | Z0 | 16bits Data | Z..Z |
| WRITE | 1..1 | 00 | 01 | AAAAA | TTTTT | 10 | 16bits Data | Z..Z |
Table 1
And the principle of work flow process that CPLD resolves MDIO is specially:
The sequential chart of the DIR2 shown in composition graphs 2, CPLD is default composes high level ' 1 ' by DIR2, and the data of control MDIO enter from the A2 port of SN74AVC2T245, and B2 port exports, and data flow to PHY chip from CPU.First CPLD searches for lead code, following search frame beginning flag position, then judge that whether operation is for reading, if for reading, the DIR2 continuing 9 clock period of maintenance is ' 1 ', the address of PHY and register address are continued to be sent in PHY chip by CPU, again DIR2 is put ' 0 ', the data of control MDIO enter from the B2 port of SN74AVC2T245, A2 port exports, the 16bit data of the 2bit ' 0 ' in " TA " State Transferring territory sent here by PHY and the appointment register of reading give CPU, terminate after ' 0 ' state lasting 17 clock period of DIR2, DIR2 is put default value ' 1 ', the next instruction cycle to be searched such as to enter.When CPU carries out write operation to PHY chip, MDIO data flow remains from CPU to PHY chip, and CPLD puts ' 1 ' to DIR2 all the time.
Namely during this period, as shown in Figure 2, DIR2 is in write operation process, and DIR2 is ' 1 ', and when read operation, DIR2 is for low from the 2nd bit of " TA ", and continuing 17 bit position durations altogether, is ' 1 ' At All Other Times.CPLD, by the parsing of the signal of communication of the MDIO pin of CPU, produces the direction that control signal controls twin voltage driving chip, makes to carry out normal data transmission between CPU and PHY chip.
In one embodiment, described processor 11 is also in order to produce a clock signal, and transmit described clock signal by described transit module 13 to described ethernet interface module 12, the transmission direction that described transit module 13 controls described clock signal remains from described processor 11 to described ethernet interface module 12.
Please consult Fig. 3 further, be shown as a kind of Ethernet interface management circuit of the present invention circuit theory diagrams in one embodiment.
Wherein, described circuit comprises a CPU and a CPLD logic chip, the PHY Ethernet chip of described ethernet interface module to be model be BCM8705, the dual power supply driving chip of described transit module to be model be SN74AVC2T245.
Wherein, concrete circuit connects: the SCL pin of described CPU, SDA pin, MDC pin, and MDIO pin respectively with the SCL pin of described CPLD, SDA pin, MDC pin, and the electrical connection of MDIO pin, the SCL pin of described CPU, SDA pin, MDC pin, and MDIO pin, and the SCL pin of described CPLD, SDA pin, MDC pin, and MDIO pin is connected respectively after a resistance and is connected with the first power electric, the MDIO_DR pin of described CPLD is electrically connected with the DR2 pin of described SN74AVC2T245 chip, described CPLD is produced described control signal in order to resolve the information of its MDIO pin reception and is sent on the DR2 pin of described SN74AVC2T245 by described MDIO_DR pin.
And, the A1 pin of described SN74AVC2T245 chip is electrically connected with the MDC pin of described CPU, the B1 pin of described SN74AVC2T245 chip is electrically connected with the MDC pin of described BCM8705 chip, the DR1 pin of described SN74AVC2T245 chip and VCCA pin connect described first power supply, and the VCC pin of described CPU and the VCC pin of described CPLD logic chip all connect described first power supply.When the DR1 pin of described SN74AVC2T245 chip receives high level, signal flows to B1 from A1, contrary, when DR1 pin receives low level, signal flows to A1 from B1, and MDC signal is one way signal, signal flows to, so make described DR1 be in high level state always, even the data transfer direction between A1 and B1 of described SN74AVC2T245 chip is A1 to B1, realize the connection of the clock signal of CPU and PHY chip.
And, the MDIO pin of described CPU is electrically connected with the A2 pin of described SN74AVC2T245 chip, and the B2 pin of described SN74AVC2T245 chip is electrically connected with the MDIO pin of described BCM8705 chip, the VCCB pin of described SN74AVC2T245 chip is all connected same second source with the VCC pin of described BCM8705 chip, described SN74AVC2T245 chip, according to the parsing of the signal received described DR2, selects the data transfer direction between pin A2 and pin B2.Wherein, when the DR2 pin of described SN74AVC2T245 chip receives high level, signal flows to B1 from A1, contrary, and when DR2 pin receives high level, signal flows to A1 from B1.MDIO is two-way signaling, therefore the DIR2 pin of the control direction signal of SN74AVC2T245 needs to flow to according to the signal of reality to control, direction control signal DIR2 is produced by CPLD, MIIM bus between CPU and PHY has also received CPLD, CPLD resolves the information on MDIO signal, produces the control signal of input DIR2 pin according to analysis result.Preferably, described first power supply is 3.3V, and described second source is 1.2V or 2.5V that can select flexibly, and described resistance is 1.5K ohm.
Further, described BCM8705 chip is electrically connected with an Ethernet physical interface, be such as SFP optical module, and TX+, TX-, RX+, RX-of described BCM8705 are electrically connected with TX+, TX-, RX+, RX-of described SFP optical module respectively, in order to accept the network insertion of external devices.
In sum, Ethernet interface management circuit of the present invention, transit module is made to be electrically connected one first power supply by described first power supply port with described processor, and be electrically connected a second source by described second power supply port with described ethernet interface module, described transit module in order to according to described control signal, the data transfer direction between control processor and described ethernet interface module.The processor and the described ethernet interface module that make to be in different voltage domain can according to self needs, select corresponding power supply, circuit connects flexibly, also solve processor and ethernet interface module in prior art and be directly connected the inadequate problem of the signal level margin that causes, ensure that the quality of signal of communication.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. an Ethernet interface management circuit, is characterized in that, comprising:
Processor;
Ethernet interface module, is communicated with described processor by bus;
Transit module, be electrically connected with described processor and described ethernet interface module, comprise control port, the first power supply port and the second power supply port, described control port receives a control signal, described first power supply port is electrically connected one first power supply with described processor, described second power supply port is electrically connected a second source with described ethernet interface module, described transit module in order to according to described control signal, the data transfer direction between control processor and described ethernet interface module.
2. Ethernet interface management circuit according to claim 1, is characterized in that, described Ethernet interface management circuit also comprises:
CPLD module, is electrically connected with described transit module, provides described control signal for the described control port to described transit module.
3. Ethernet interface management circuit according to claim 1, it is characterized in that, described CPLD module is connected with described bus, to produce described control signal according to the parsing to the communication protocol of the bus between described processor and described ethernet interface module.
4. Ethernet interface management circuit according to claim 3, it is characterized in that, the analysis result of described CPLD module to the communication protocol of described bus comprises lead code, frame start mark, operational code, ethernet interface module internal register addresses, State Transferring territory, read/write status zone bit.
5. Ethernet interface management circuit according to claim 4, it is characterized in that, it is from described processor to described ethernet interface module that described control signal is defaulted as controlling described data transfer direction, and when judging described read/write status zone bit as reading, make described transit module according to described control signal, make described data transfer direction be from described ethernet interface module to described processor.
6. Ethernet interface management circuit according to claim 1, is characterized in that: described processor also in order to produce a clock signal, and transmits described clock signal by described transit module to described ethernet interface module.
7. Ethernet interface management circuit according to claim 6, is characterized in that: the transmission direction that described transit module controls described clock signal remains from described processor to described ethernet interface module.
8. the Ethernet interface management circuit according to any one of claim 1 ~ 7, is characterized in that, described transit module is SN74AVC2T245 chip.
9. the Ethernet interface management circuit according to any one of claim 1 ~ 7, is characterized in that, is communicated between described processor with described ethernet interface module by Media Independent Interface bus.
10. the Ethernet interface management circuit according to any one of claim 1 ~ 7, is characterized in that, the first power supply is 3.3V power supply, and described second source is 1.2V or 2.5V power supply.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912494A (en) * | 2016-04-11 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | MIIM bus circuit |
| CN109580997A (en) * | 2018-11-30 | 2019-04-05 | 泸州威恩德科技有限公司 | Test fixture, test device and test macro |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101059691A (en) * | 2007-05-24 | 2007-10-24 | 北京天航信民航通信网络发展有限公司 | Automatic metering controller |
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Power quality analyzer and power quality analysis method for digital power system |
| US20090006659A1 (en) * | 2001-10-19 | 2009-01-01 | Collins Jack M | Advanced mezzanine card for digital network data inspection |
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN202679392U (en) * | 2012-06-19 | 2013-01-16 | 华自科技股份有限公司 | Embedded type communication management machine |
| CN202759472U (en) * | 2012-09-03 | 2013-02-27 | 北京东土科技股份有限公司 | Industrial Ethernet switch |
| CN104037941A (en) * | 2014-06-05 | 2014-09-10 | 中国海洋石油总公司 | Control protection system for flexible direct-current power transmission system |
-
2015
- 2015-09-11 CN CN201510578628.4A patent/CN105068961B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090006659A1 (en) * | 2001-10-19 | 2009-01-01 | Collins Jack M | Advanced mezzanine card for digital network data inspection |
| CN101059691A (en) * | 2007-05-24 | 2007-10-24 | 北京天航信民航通信网络发展有限公司 | Automatic metering controller |
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Power quality analyzer and power quality analysis method for digital power system |
| CN202679392U (en) * | 2012-06-19 | 2013-01-16 | 华自科技股份有限公司 | Embedded type communication management machine |
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN202759472U (en) * | 2012-09-03 | 2013-02-27 | 北京东土科技股份有限公司 | Industrial Ethernet switch |
| CN104037941A (en) * | 2014-06-05 | 2014-09-10 | 中国海洋石油总公司 | Control protection system for flexible direct-current power transmission system |
Non-Patent Citations (1)
| Title |
|---|
| TEXAS INSTRUMENTS INCORPORATED: "DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS", 《HTTP://WWW.FARNELL.COM/DATASHEETS/1863675.PDF》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912494A (en) * | 2016-04-11 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | MIIM bus circuit |
| CN109580997A (en) * | 2018-11-30 | 2019-04-05 | 泸州威恩德科技有限公司 | Test fixture, test device and test macro |
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